MC74LVXT8053D [ONSEMI]
Analog Multiplexer/Demultiplexer; 模拟复用器/解复用器![MC74LVXT8053D](http://pdffile.icpdf.com/pdf1/p00033/img/icpdf/MC74LVXT8053_170934_icpdf.jpg)
型号: | MC74LVXT8053D |
厂家: | ![]() |
描述: | Analog Multiplexer/Demultiplexer |
文件: | 总12页 (文件大小:246K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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High–Performance Silicon–Gate CMOS
The MC74LVXT8053 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
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(from V
to GND).
CC
The LVXT8053 is similar in pinout to the high–speed HC4053A,
and the metal–gate MC14053B. The Channel–Select inputs determine
which one of the Analog Inputs/Outputs is to be connected by means
of an analog switch to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with
TTL–type input thresholds. The input protection circuitry on this
device allows overvoltage tolerance on the input, allowing the device
to be used as a logic–level translator from 3.0V CMOS logic to 5.0V
CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while
operating at the higher–voltage power supply.
16–LEAD SOIC
D SUFFIX
CASE 751B
16–LEAD TSSOP
DT SUFFIX
CASE 948F
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
V
Y
X
X1
13
X0
12
A
B
C
9
CC
16
15
14
11
10
The MC74LVXT8053 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74LVXT8053 to be used to interface 5V circuits to 3V circuits.
1
2
3
4
5
6
7
8
This device has been designed so that the ON resistance (R ) is more
on
Y1
Y0
Z1
Z
Z0 Enable NC GND
linear over input voltage than R of metal–gate CMOS analog switches.
on
For detailed package marking information, see the Marking
Diagram section on page 11 of this data sheet.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
FUNCTION TABLE – MC74LVXT8053
• Analog Power Supply Range (V
– GND) = 2.0 to 6.0 V
CC
Control Inputs
• Digital (Control) Power Supply Range (V
CC
– GND) = 2.0 to 6.0 V
Select
• Improved Linearity and Lower ON Resistance Than Metal–Gate
Enable
C
B
A
ON Channels
Counterparts
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
X0
• Low Noise
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
• In Compliance With the Requirements of JEDEC Standard No. 7A
L
LOGIC DIAGRAM
H
H
H
H
X
Triple Single–Pole, Double–Position Plus Common Off
L
H
H
X
12
X0
X1
14
X
Y
Z
13
X SWITCH
NONE
2
1
X = Don’t Care
Y0
Y1
15
4
ANALOG
INPUTS/OUTPUTS
COMMON
OUTPUTS/INPUTS
Y SWITCH
Z SWITCH
ORDERING INFORMATION
5
3
Z0
Z1
Device
Package
SOIC
Shipping
11
10
9
A
B
C
MC74LVXT8053D
MC74LVXT8053DR2
MC74LVXT8053DT
48 Units/Rail
2500 Units/Reel
96 Units/Rail
CHANNEL-SELECT
INPUTS
PIN 16 = V
CC
PIN 8 = GND
SOIC
6
ENABLE
TSSOP
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
MC74LVXT8053DTR2 TSSOP 2500 Units/Reel
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
March, 2000 – Rev. 2
MC74LVXT8053/D
MC74LVXT8053
MAXIMUM RATINGS*
Symbol
Parameter
(Referenced to GND)
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage
– 0.5 to + 7.0
V
IS
Analog Input Voltage
– 0.5 to V
+ 0.5
V
CC
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to V
+ 0.5
V
in
CC
I
–20
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
in out
Unused inputs must always be
tied to an appropriate logic voltage
T
Storage Temperature Range
– 65 to + 150
260
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
level (e.g., either GND or V
).
CC
Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
Analog Input Voltage
Min
2.0
Max
Unit
V
V
CC
(Referenced to GND)
6.0
V
IS
0.0
V
V
V
CC
V
in
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
V
CC
V
IO
*
1.2
V
T
A
– 55
+ 85
C
t , t
r f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
ns/V
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
*For voltage drops across switch greater than 1.2 V (switch on), excessive V
be drawn; i.e., the current out of the switch may contain both V
CC
current may
and switch input
CC
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
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2
MC74LVXT8053
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
= Per Spec
Unit
–55 to 25°C ≤85°C ≤125°C
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
R
R
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
on
on
V
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
= Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IL
in
I
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
V
in
= V
or GND,
CC
5.5
± 0.1
± 1.0
± 1.0
µA
µA
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
= V or GND; V = 0 V
5.5
4
40
160
CC
V
IS
CC
IO
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
85 C
V
CC
V
– 55 to
25 C
Symbol
Parameter
Test Conditions
Unit
125 C
R
Maximum “ON” Resistance
Ω
V
V
|I |
S
= V or V
IL
3.0
4.5
5.5
40
30
25
45
32
28
50
37
30
on
in
IS
IH
= V
to GND
CC
10.0 mA (Figures 1, 2)
V
V
|I |
S
= V or V
IL
3.0
4.5
5.5
30
25
20
35
28
25
40
35
30
in
IS
IH
= V
or GND (Endpoints)
CC
10.0 mA (Figures 1, 2)
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
|I |
S
= V or V
IH
3.0
4.5
5.5
15
8.0
8.0
20
12
12
25
15
15
Ω
on
in
IS
IL
= 1/2 (V
– GND)
CC
10.0 mA
I
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V or V
IL IH
;
5.5
5.5
5.5
0.1
0.1
0.1
0.5
1.0
1.0
1.0
2.0
2.0
µA
off
in
= V
or GND;
IO
CC
Switch Off (Figure 3)
Maximum Off–Channel
Leakage Current,
Common Channel
V
V
= V or V ;
IL
in
IO
IH
or GND;
CC
= V
Switch Off (Figure 4)
I
on
Maximum On–Channel
Leakage Current,
Channel–to–Channel
V
in
= V or V ;
IL IH
µA
Switch–to–Switch =
V or GND; (Figure 5)
CC
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3
MC74LVXT8053
AC CHARACTERISTICS (C = 50 pF, Input t = t = 3 ns)
L
r
f
Guaranteed Limit
V
CC
V
Symbol
Parameter
Unit
–55 to 25°C
≤85°C
≤125°C
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
PZL
PZH
C
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
35
50
1.0
10
35
50
1.0
10
35
50
1.0
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
I/O
C
pF
PD
Typical @ 25°C, V
= 5.0 V
CC
Power Dissipation Capacitance (Figure 13)*
45
2
* Used to determine the no–load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74LVXT8053
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
V
CC
V
Symbol
Parameter
Condition
= 1MHz Sine Wave; Adjust f Voltage to Obtain
Unit
25°C
BW
Maximum On–Channel Bandwidth
or Minimum Frequency Response
(Figure 6)
f
MHz
in
in
0dBm at V ; Increase f Frequency Until dB
OS
in
3.0
4.5
5.5
120
120
120
Meter Reads –3dB;
R
= 50Ω, C = 10pF
L
L
—
—
Off–Channel Feedthrough Isolation
(Figure 7)
f
= Sine Wave; Adjust f Voltage to Obtain 0dBm
in
3.0
4.5
5.5
–50
–50
–50
dB
in
at V
IS
f
in
= 10kHz, R = 600Ω, C = 50pF
L L
3.0
4.5
5.5
–37
–37
–37
f
in
= 1.0MHz, R = 50Ω, C = 10pF
L L
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
V
≤ 1MHz Square Wave (t = t = 3ns); Adjust R
3.0
4.5
5.5
25
105
135
mV
PP
in
r
f
L
at Setup so that I = 0A;
S
Enable = GND
R = 600Ω, C = 50pF
L L
3.0
4.5
5.5
35
145
190
R
= 10kΩ, C = 10pF
L
L
—
Crosstalk Between Any Two
Switches (Figure 12)
f
= Sine Wave; Adjust f Voltage to Obtain 0dBm
in
3.0
4.5
5.5
–50
–50
–50
dB
in
at V
IS
f
= 10kHz, R = 600Ω, C = 50pF
L L
in
3.0
4.5
5.5
–60
–60
–60
f
in
= 1.0MHz, R = 50Ω, C = 10pF
L
L
THD
Total Harmonic Distortion
(Figure 14)
f
= 1kHz, R = 10kΩ, C = 50pF
%
in
THD = THD
L
L
– THD
measured
source
V
IS
V
IS
V
IS
= 2.0V
= 4.0V
= 5.0V
sine wave
sine wave
sine wave
3.0
4.5
5.5
0.10
0.08
0.05
PP
PP
PP
*Limits not tested. Determined by design and verified by qualification.
45
40
35
30
25
20
15
10
5
125°C
85°C
25°C
–55°C
0
0
1.0
2.0
V , INPUT VOLTAGE (VOLTS)
3.0
4.0
IN
Figure 1a. Typical On Resistance, V
= 3.0 V
CC
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5
MC74LVXT8053
35
30
25
20
15
30
25
125°C
85°C
25°C
125°C
20
85°C
25°C
–55°C
15
–55°C
10
10
5
5
0
0
0
1.0
2.0
3.0
4.0
5.0
0
1.0
2.0
3.0
4.0
5.0
6.0
V , INPUT VOLTAGE (VOLTS)
IN
V , INPUT VOLTAGE (VOLTS)
IN
Figure 1b. Typical On Resistance, V
CC
= 4.5 V
Figure 1c. Typical On Resistance, V
= 5.5 V
CC
PLOTTER
PROGRAMMABLE
POWER
MINI COMPUTER
DC ANALYZER
SUPPLY
–
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
GND
Figure 1. On Resistance Test Set–Up
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6
MC74LVXT8053
V
CC
V
CC
V
V
CC
CC
16
16
GND
GND
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
V
CC
V
CC
COMMON O/I
NC
COMMON O/I
V
6
8
6
8
IH
IH
Figure 2. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 3. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
V
CC
16
V
OS
V
CC
V
CC
16
0.1µF
A
dB
METER
f
in
ON
ON
N/C
R
L
GND
C *
L
COMMON O/I
OFF
V
CC
ANALOG I/O
V
IL
6
8
6
8
*Includes all probe and jig capacitance
Figure 4. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 5. Maximum On Channel Bandwidth,
Test Set–Up
V
CC
16
V
CC
16
V
IS
V
OS
0.1µF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
ANALOG I/O
R
L
R
L
C *
L
POINT
R
L
C *
L
R
L
6
8
6
8
V
CC
V ≤ 1 MHz
in
11
t = t = 3 ns
r
f
V
V
IL
IH
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
IH
Figure 6. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 7. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
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7
MC74LVXT8053
V
CC
16
V
CC
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
50%
ANALOG I/O
GND
L
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In
to Analog Out
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
t
t
POSITION 1 WHEN TESTING t
POSITION 2 WHEN TESTING t
AND t
AND t
f
r
PHZ
PLZ
PZH
PZL
1
2
V
CC
90%
50%
10%
ENABLE
V
CC
16
GND
1kΩ
V
CC
t
t
PZL PLZ
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
V
OL
t
t
V
PZH PHZ
IH
V
IL
6
8
V
OH
90%
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delays, Enable to
Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
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MC74LVXT8053
V
CC
V
IS
A
V
CC
16
16
R
L
V
OS
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1µF
OFF
R
L
R
L
C *
L
C *
L
V
CC
R
L
6
8
6
8
11
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 12. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 13. Power Dissipation Capacitance,
Test Set–Up
0
–10
–20
–30
–40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
16
V
OS
0.1µF
TO
f
in
DISTORTION
METER
ON
R
L
C *
L
–50
–60
–70
–80
–90
–100
DEVICE
SOURCE
6
8
*Includes all probe and jig capacitance
1.0
2.0
3.125
FREQUENCY (kHz)
Figure 14a. Total Harmonic Distortion, Test Set–Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at connected). However, tying unused analog inputs and
V
CC
or GND logic levels. V being recognized as a logic outputs to V or GND through a low value resistor helps
CC CC
high and GND being recognized as a logic low. In this
example:
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
V
= +5V = logic high
CC
GND = 0V = logic low
The maximum analog voltage swing is determined by the
supply voltages V . The positive peak analog voltage
V
– GND = 2 to 6 volts
CC
CC
When voltage transients above V
should not exceed V . Similarly, the negative peak analog
and/or below GND
CC
CC
are anticipated on the analog channels, external Germanium
voltage should not go below GND. In this example, the
difference between V
and GND is five volts. Therefore,
or Schottky diodes (D ) are recommended as shown in
CC
x
using the configuration of Figure 15, a maximum analog
signal of five volts peak–to–peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
Figure 16. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
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MC74LVXT8053
V
V
CC
CC
+5V
V
CC
16
ON/OFF
D
D
x
16
x
+5V
0V
+5V
0V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
D
x
x
GND
GND
TO EXTERNAL LSTTL COMPATIBLE
6
8
11
10
9
CIRCUITRY 0 to V
IH
DIGITAL SIGNALS
8
Figure 15. Application Example
Figure 16. External Germanium or
Schottky Clipping Diodes
+3V
16
+5V
16
+3V
+5V
+3V
+5V
ANALOG
SIGNAL
ANALOG
ANALOG
SIGNAL
ANALOG
ON/OFF
ON/OFF
SIGNAL
SIGNAL
GND
GND
GND
GND
1.8 – 2.5V
6
8
11
10
9
6
8
11
10
9
1.8 – 2.5V
CIRCUITRY
1.8 – 2.5V
CIRCUITRY
MC74VHC1GT50 BUFFERS
= 3.0V
V
CC
a. Low Voltage Logic Level Shifting Control
b. 2–Stage Logic Level Shifting Control
Figure 17. Interfacing Low Voltage CMOS Inputs
11
10
9
13
LEVEL
SHIFTER
A
B
C
X1
12
14
1
X0
X
LEVEL
SHIFTER
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 18. Function Diagram, LVXT8053
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MC74LVXT8053
MARKING DIAGRAMS
(Top View)
16 15 14 13 12 11 10
9
8
16
15
14
13
12
11
6
10
9
8
LVXT
8051
LVXT8051
AWLYWW*
ALYW*
1
2
3
4
5
7
1
2
3
4
5
6
7
16–LEAD SOIC
D SUFFIX
16–LEAD TSSOP
DT SUFFIX
CASE 751B
CASE 948F
*See Applications Note #AND8004/D for date code and traceability information.
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
http://onsemi.com
11
MC74LVXT8053
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
S
0.15 (0.006) T U
K
Y14.5M, 1982.
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
–V–
N
A
B
C
D
F
G
H
J
J1
K
K1
L
4.90
4.30
–––
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
––– 0.047
0.15 0.002 0.006
0.75 0.020 0.030
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
DETAIL E
0.65 BSC
0.18
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
DETAIL E
H
SEATING
PLANE
–T–
D
G
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