MC74VHC08MR2 [ONSEMI]
AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, EIAJ, SOIC-14;
| 型号： | MC74VHC08MR2 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, EIAJ, SOIC-14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC08
Quad 2-Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2−input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
Features
14
• High Speed: t = 4.3 ns (Typ) at V = 5.0 V
PD
CC
14
VHC08G
AWLYWW
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
CC
A
1
• High Noise Immunity: V
= V
= 28% V
NIL CC
NIH
SOIC−14
D SUFFIX
CASE 751A
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
1
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
14
OLP
14
VHC
08
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
ALYW
ꢀ
1
ꢀ
• ESD Performance:
1
TSSOP
Human Body Model > 2000 V;
Machine Model > 200 V
DT SUFFIX
CASE 948G
• Chip Complexity: 24 FETs or 6 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
14
74VHC08
ALYWG
1
A1
3
SOEIAJ−14
M SUFFIX
CASE 965
Y1
2
1
B1
4
A2
6
Y2
5
B2
A
= Assembly Location
= Year
Y = AB
9
WL, L = Wafer Lot
Y
WW, W = Work Week
A3
8
Y3
10
B3
12
G or ꢀ = Pb−Free Package
A4
11
(Note: Microdot may be in either location)
Y4
13
B4
Figure 1. Logic Diagram
FUNCTION TABLE
V
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
CC
Inputs
Output
14
A
B
Y
L
L
L
H
L
L
L
H
H
L
H
H
1
2
3
4
5
6
7
A1
B1
Y1
A2
B2
Y2 GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Pinout: 14−Lead Packages
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 8
MC74VHC08/D
MC74VHC08
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
–0.5 to V +0.5
V
out
IK
CC
I
−20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
50
CC
†
†
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages
TSSOP Package
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
–65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
−
SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
V
in
5.5
V
V
DC Output Voltage
Operating Temperature
Input Rise and Fall Time
0
V
V
out
CC
T
−55
+125
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
f
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
= −55°C to 125°C
V
CC
V
Min
Typ
Max
Min
1.50
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
2.0
0.50
CC
0.50
CC
V
V
IL
Input Voltage
3.0 to 5.5
V
x 0.3
V
x 0.3
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
OH
V
in
= V or V
IH
IL
3.0
4.5
2.58
3.94
2.48
3.80
I
I
= −4.0 mA
= −8.0 mA
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
= 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
OL
V
in
= V or V
IH
IL
3.0
4.5
0.36
0.36
0.44
0.44
I
OL
I
OL
= 4.0 mA
= 8.0 mA
I
Maximum Input
Leakage Current
V
V
= 5.5 V or GND
0 to 5.5
5.5
0.1
2.0
1.0
mA
mA
in
in
I
Maximum Quiescent
Supply Current
= V or GND
20.0
CC
in
CC
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2
MC74VHC08
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T = −55°C to 125°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Unit
t
,
Maximum Propagation
Delay,
A or B to Y
V
V
6.2
8.7
8.8
12.3
1.0
1.0
10.5
14.0
ns
PLH
CC
L
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
4.3
5.8
5.9
7.9
1.0
1.0
7.0
9.0
CC
L
C = 50 pF
L
C
Maximum Input
Capacitance
4
10
10
pF
in
Typical @ 25°C, V = 5.0 V
CC
18
C
Power Dissipation Capacitance (Note 1)
pF
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC
CC(OPR
CC
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.8
−0.8
3.5
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
−0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
TEST
POINT
V
CC
A or B
50%
OUTPUT
DEVICE
UNDER
TEST
GND
C *
L
t
t
PLH
PHL
Y
50% V
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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3
MC74VHC08
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC08DR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC74VHC08DTR2G
MC74VHC08MELG
TSSOP−14*
2500 Units / Tape & Reel
2000 Units / Tape & Reel
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
MC74VHC08
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45ꢁ
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
1.27 BSC
0.19
0.10
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
0 ꢁ
5.80
0.25
7ꢁ
0 ꢁ
7ꢁ
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
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5
MC74VHC08
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
K1
DIM MIN
MAX
MIN MAX
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
J J1
−−− 0.047
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0 ꢁ
8 ꢁ
0 ꢁ
8 ꢁ
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74VHC08
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
ꢁ
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
---
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
---
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0
0.90 0.028
1.42 ---
0.323
0.033
0.059
0.13 (0.005)
E
L
0.10 (0.004)
L
E
10ꢁ
ꢁ
M
0
10ꢁ
0.035
0.056
ꢁ
Q
0.70
---
1
Z
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MC74VHC08/D
相关型号：
MC74VHC125MELG
AHC/VHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, EIAJ, PLASTIC, SOIC-14
ONSEMI
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