MC74VHC1G125DTT1G [ONSEMI]
Noninverting 3-State Buffer; 同相三态缓冲器![MC74VHC1G125DTT1G](http://pdffile.icpdf.com/pdf1/p00089/img/icpdf/MC74VHC1_466884_icpdf.jpg)
型号: | MC74VHC1G125DTT1G |
厂家: | ![]() |
描述: | Noninverting 3-State Buffer |
文件: | 总6页 (文件大小:71K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MC74VHC1G125
Noninverting 3−State Buffer
The MC74VHC1G125 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G125 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G125 to be used to interface 5.0 V circuits to
3.0 V circuits.
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MARKING
DIAGRAMS
SC−88A/SOT−353/SC−70
DF SUFFIX
W0d
CASE 419A
Features
• These are Pb−Free Devices
Pin 1
d = Date Code
• High Speed: t = 3.5 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 58; Equivalent Gates = 15
W0d
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
Pin 1
d = Date Code
PIN ASSIGNMENT
1
2
3
4
5
OE
IN A
1
2
3
5
V
CC
OE
IN A
GND
GND
OUT Y
V
CC
4
OUT Y
FUNCTION TABLE
OE Input
A Input
Y Output
L
H
X
L
L
L
H
Z
Figure 1. Pinout (Top View)
H
ORDERING INFORMATION
OE
IN A
EN
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
September, 2004 − Rev. 12
MC74VHC1G125/D
MC74VHC1G125
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
V
IN
V
V
OUT
V
= 0
CC
V
−0.5 to V + 0.5
High or Low State
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OUT CC
OK
OUT
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power Dissipation in Still Air
Thermal Resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
JA
T
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage Temperature
260
L
T
+150
−65 to +150
°C
J
T
stg
°C
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
I
LatchUp Performance
Above V and Below GND at 125°C (Note 4)
$500
mA
LatchUp
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
V
CC
V
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
V
CC
V
CC
= 3.3 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
r
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
MC74VHC1G125
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
V
V
OH
IN
IH
IL
IL
IL
IL
IL
I
OH
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
Maximum Low−Level
Output Voltage
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IH
I
OL
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum 3−State
Leakage Current
V
V
= V or V
5.5
±0.25
±0.1
1.0
$2.5
±1.0
20
$2.5
$1.0
40
mA
mA
mA
OZ
IN
IH
= V or GND
OUT
CC
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
IN
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
CC
CC
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation
Delay,
Input A to Y
V
V
V
= 3.3 ± 0.3 V C = 15 pF
4.5
6.4
8.0
11.5
9.5
13.0
12.0
16.0
ns
PLH
t
CC
CC
CC
L
C = 50 pF
L
PHL
= 5.0 ± 0.5 V C = 15 pF
3.5
4.5
5.5
7.5
6.5
8.5
8.5
10.5
(Figures 3 and 4)
L
C = 50 pF
L
,
Maximum Output
Enable Time,
Input OE to Y
= 3.3 ± 0.3 V C = 15 pF
4.5
6.4
8.0
11.5
9.5
13.0
11.5
15.0
ns
ns
PZL
t
L
R = 1000 W
C = 50 pF
L
PZH
L
V
CC
= 5.0 ± 0.5 V C = 15 pF
3.5
4.5
5.1
7.1
6.0
8.0
8.5
10.5
(Figures 4 and 5)
L
R = 1000 W
C = 50 pF
L
L
,
Maximum Output
Disable Time,
Input OE to Y
V
CC
= 3.3 ± 0.3 V C = 15 pF
6.5
8.0
9.7
13.2
11.5
15.0
14.5
18.0
PLZ
L
t
R 1000 W
C = 50 pF
L
PHZ
L
V
CC
= 5.0 ± 0.5 V C = 15 pF
4.8
7.0
6.8
8.8
8.0
10.0
10.0
12.0
(Figures 4 and 5)
L
R = 1000 W
C = 50 pF
L
L
C
Maximum Input
Capacitance
4.0
10
10
10
pF
pF
IN
C
Maximum 3−State Out-
put Capacitance (Output
in High Impedance
State)
6.0
OUT
Typical @ 25°C, V = 5.0 V
CC
8.0
C
Power Dissipation Capacitance (Note 5)
pF
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G125
SWITCHING WAVEFORMS
V
CC
OE
50%
V
CC
GND
50%
t
t
PZL
PLZ
A
Y
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
50% V
Y
CC
V
V
+ 0.3V
OL
50% V
CC
t
t
PZH
PHZ
− 0.3V
OH
50% V
Y
CC
HIGH
IMPEDANCE
Figure 4. Switching Wave Forms
Figure 5.
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
PHZ
PZH.
C *
L
C *
L
TEST
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
Device Nomenclature
DEVICE ORDERING INFORMATION
Temp
Range
Identifier
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Circuit
Indicator
Device
Function
Package
Suffix
Device
Order Number
Tape and
Reel Size
†
Technology
SC−88A/SOT−353
/SC−70
178 mm (7”)
3000 Unit
MC74VHC1G125DFT1
MC74VHC1G125DFT1G
MC74VHC1G125DFT2
MC74VHC1G125DFT2G
MC74VHC1G125DTT1
MC74VHC1G125DTT1G
MC
MC
MC
MC
MC
MC
74
74
74
74
74
74
VHC1G
125
125
125
125
125
125
DF
DF
DF
DF
DT
DT
T1
T1
T2
T2
T1
T1
SC−88A/SOT−353
/SC−70
178 mm (7”)
3000 Unit
VHC1G
VHC1G
VHC1G
VHC1G
VHC1G
(Pb−Free)
SC−88A/SOT−353
/SC−70
178 mm (7”)
3000 Unit
TSC−88A/SOT−353
/SC−70
178 mm (7”)
3000 Unit
(Pb−Free)
TSOP−5/SOT−23
/SC−59
178 mm (7”)
3000 Unit
TSOP−5/SOT−23
/SC−59
178 mm (7”)
3000 Unit
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G125
PACKAGE DIMENSIONS
SC70−5/SC−88A/SOT−353
DF SUFFIX
5−LEAD PACKAGE
CASE 419A−02
ISSUE G
NOTES:
A
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
0.2 (0.008)
B
D 5 PL
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
K
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G125
PACKAGE DIMENSIONS
SOT23−5/TSOP−5/SC59−5
DT SUFFIX
5−LEAD PACKAGE
CASE 483−02
ISSUE C
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
B
C
S
1
2
L
G
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
J
A
B
C
D
G
H
J
K
L
M
S
2.90
1.30
0.90
0.25
0.85
3.10 0.1142 0.1220
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.05 (0.002)
H
M
K
0.013 0.100 0.0005 0.0040
0.10
0.20
1.25
0
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
10
0
10
_
_
_
_
2.50
3.00 0.0985 0.1181
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
mm
inches
ǒ
Ǔ
0.7
0.028
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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Order Literature: http://www.onsemi.com/litorder
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For additional information, please contact your
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MC74VHC1G125/D
相关型号:
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MC74VHC1G126DFT4
AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
ONSEMI
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