MC74VHC1G126 [ONSEMI]
Noninverting 3−State Buffer; 同相三态缓冲器
| 型号： | MC74VHC1G126 |
| 厂家： | 
ONSEMI |
| 描述： | Noninverting 3−State Buffer |
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1G126
Noninverting 3−State Buffer
The MC74VHC1G126 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G126 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G126 to be used to interface 5.0 V circuits to
3.0 V circuits.
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MARKING
DIAGRAMS
5
5
1
W2 M G
SC−88A/SOT−353/SC−70
DF SUFFIX
G
Features
1
5
• High Speed: t = 3.5 ns (Typ) at V = 5.0 V
CASE 419A
PD
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
5
W2 AYW G
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 58; Equivalent Gates = 15
• Pb−Free Packages are Available
G
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
1
CASE 483
W2
M
A
= Device Code
= Date Code*
= Assembly Location
= Year
Y
5
1
2
3
V
CC
OE
IN A
GND
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
4
OUT Y
PIN ASSIGNMENT
1
2
3
4
5
OE
Figure 1. Pinout (Top View)
IN A
GND
OUT Y
V
CC
OE
IN A
EN
OUT Y
FUNCTION TABLE
OE Input
A Input
Y Output
Figure 2. Logic Symbol
L
H
X
H
H
L
L
H
Z
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 13
MC74VHC1G126/D
MC74VHC1G126
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
CC
V
V
IN
V
V
= 0
CC
V
OUT
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power dissipation in still air
Thermal resistance
SC−88A, TSOP−5
SC−88A, TSOP−5
200
D
q
333
JA
T
Lead temperature, 1 mm from case for 10 s
Junction temperature under bias
Storage temperature
260
L
J
T
+150
−65 to +150
°C
T
stg
°C
V
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
DC Supply Voltage
CC
V
DC Input Voltage
5.5
V
IN
V
DC Output Voltage
V
V
OUT
CC
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
f
CC
CC
Device Junction Temperature versus
Time to 0.1% Bond Failures
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
MC74VHC1G126
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
(V)
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
IH
V
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
IL
V
Minimum High−Level
Output Voltage
V
= V or V
= −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
V
V
V
OH
IN
IH
IL
IL
IL
IL
IL
I
OH
V
= V or V
IN
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
Maximum Low−Level
Output Voltage
V
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IN
IH
I
= 50 mA
OL
V
= V or V
IN
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
I
Maximum 3−State
Leakage Current
V
V
= V or V
5.5
0.25
2.5
1.0
20
2.5
1.0
40
mA
mA
mA
OZ
IN
IH
= V or GND
OUT
CC
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
IN
IN
IN
Maximum Quiescent
Supply Current
V
= V or GND
5.5
1.0
CC
CC
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
r f
load
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Maximum Propagation
Delay,
Input A to Y
V
V
V
= 3.3 0.3 VC = 15 pF
4.5
6.4
8.0
11.5
9.5
13.0
12.0
16.0
ns
PLH
CC
CC
CC
L
C = 50 pF
L
PHL
= 5.0 0.5 VC = 15 pF
3.5
4.5
5.5
7.5
6.5
8.5
8.5
10.5
L
(Figures 3. and 5.)
C = 50 pF
L
t
,
Maximum Output
Enable Time,
Input OE to Y
= 3.3 0.3 VC = 15 pF
4.5
6.4
8.0
11.5
9.5
13.0
11.5
15.0
ns
ns
PZL
L
t
R = 1000 W
C = 50 pF
L
PZH
L
V
= 5.0 0.5 VC = 15 pF
3.5
4.5
5.1
7.1
6.0
8.0
8.5
10.5
CC
L
(Figures 4. and 5.)
R = 1000 W
C = 50 pF
L
L
t
,
Maximum Output
Disable Time,
V
= 3.3 0.3 VC = 15 pF
6.5
8.0
9.7
13.2
11.5
15.0
14.5
18.0
PLZ
CC
L
t
R = 1000 W
C = 50 pF
L
PHZ
L
Input OE to Y
(Figures 4. and 5.)
V
= 5.0 0.5 VC = 15 pF
4.8
7.0
6.8
8.8
8.0
10.0
10.0
12.0
CC
L
R = 1000 W
C = 50 pF
L
L
C
Maximum Input
Capacitance
4.0
10
10
10
pF
pF
IN
C
OUT
Maximum 3−State Output
Capacitance (Output in
High Impedance State)
6.0
Typical @ 25°C, V = 5.0 V
CC
8.0
C
PD
Power Dissipation Capacitance (Note 5)
pF
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G126
SWITCHING WAVEFORMS
V
CC
OE
50%
V
GND
CC
50%
t
t
PZL
PLZ
A
Y
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
50% V
Y
CC
V
V
+ 0.3V
OL
50% V
CC
t
t
PZH
PHZ
− 0.3V
OH
50% V
Y
CC
HIGH
IMPEDANCE
Figure 4. Switching Waveforms
Figure 5.
TEST POINT
1 kW
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
DEVICE ORDERING INFORMATION
†
Device Order Number
Package Type
Tape and Reel Size
MC74VHC1G126DFT1
SC−88A/SOT−353/SC−70
178 mm (7”)
3000 Units / Tape & Reel
M74VHC1G126DFT1G
MC74VHC1G126DFT2
M74VHC1G126DFT2G
MC74VHC1G126DTT1
M74VHC1G126DTT1G
SC−88A/SOT−353/SC−70
(Pb−Free)
178 mm (7”)
3000 Units / Tape & Reel
SC−88A/SOT−353/SC−70
178 mm (7”)
3000 Units / Tape & Reel
SC−88A/SOT−353/SC−70
(Pb−Free)
178 mm (7”)
3000 Units / Tape & Reel
TSOP−5/SOT−23/SC−59
178 mm (7”)
3000 Units / Tape & Reel
TSOP−5/SOT−23/SC−59
(Pb−Free)
178 mm (7”)
3000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G126
PACKAGE DIMENSIONS
SC−88A / SOT−353 / SC70
CASE 419A−02
ISSUE H
NOTES:
A
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
N
K
N
S
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
mm
inches
ǒ
Ǔ
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G126
PACKAGE DIMENSIONS
TSOP−5 / SOT23−5 / SC59−5
DT SUFFIX
CASE 483−02
ISSUE D
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
B
C
S
1
2
L
G
A
MILLIMETERS
INCHES
MIN MAX
0.1142 0.1220
DIM
A
B
C
D
G
H
J
K
L
MIN
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
MAX
3.10
J
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
0.05 (0.002)
H
M
K
M
S
10
0
10
_
_
_
_
2.50
3.00 0.0985 0.1181
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G126/D
相关型号：
MC74VHC1G126DFT4
AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
ONSEMI
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