MC74VHC244MELG [ONSEMI]
AHC/VHC SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20;型号: | MC74VHC244MELG |
厂家: | ONSEMI |
描述: | AHC/VHC SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20 驱动 光电二极管 输出元件 逻辑集成电路 |
文件: | 总7页 (文件大小:144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74VHC244
Octal Bus Buffer
The MC74VHC244 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology.
The MC74VHC244 is a noninverting 3−state buffer, and has two
active−low output enables. This device is designed to be used with
3−state memory address drivers, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
http://onsemi.com
MARKING DIAGRAMS
20
SOIC−20
DW SUFFIX
CASE 751D
• High Speed: t = 3.9 ns (Typ) at V = 5 V
PD
CC
VHC244
AWLYYWWG
20
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
1
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
1
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
20
VHC
244
• Designed for 2 V to 5.5 V Operating Range
TSSOP−20
DT SUFFIX
CASE 948E
20
• Low Noise: V
= 0.9 V (Max)
OLP
ALYWG
1
G
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V
Machine Model > 200 V
1
VHC244 = Specific Device Code
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Chip Complexity: 136 FETs
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
(Note: Microdot may be in either location)
• These Devices are Pb−Free and are RoHS Compliant
PIN ASSIGNMENT
2
4
6
8
18
16
14
12
A1
A2
A3
A4
YA1
YA2
YA3
YA4
OEA
A1
1
2
3
4
5
6
7
8
9
20
V
CC
19 OEB
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
YB4
A2
YB3
A3
DATA
NONINVERTING
OUTPUTS
INPUTS
YB2
A4
11
13
15
17
9
7
5
3
B1
B2
B3
B4
YB1
YB2
YB3
YB4
YB1
GND 10
ORDERING INFORMATION
See detailed ordering and shipping information in the
Ordering Information Table on page 2 of this data sheet.
1
OEA
OEB
OUTPUT
19
ENABLES
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
March, 2013 − Rev. 9
MC74VHC244/D
MC74VHC244
FUNCTION TABLE
INPUTS
OUTPUTS
OEA, OEB
A, B
L
YA, YB
L
L
L
H
Z
H
H
X
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC244DWR2G
SOIC−20 WB
(Pb−Free)
1000/Tape & Reel
MC74VHC244DTG
75 Units/Rail
TSSOP−20
(Pb−Free)
MC74VHC244DTR2G
NLV74VHC244DTR2G*
2500/Tape & Reel
2500/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
CC
IN
V
DC Output Voltage
−0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC
TSSOP
500
450
D
T
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
V
Human Body Model (Note 2)
Machine Model (Note 3)
>2000
>200
V
ESD
Charged Device Model (Note 4)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
$300
96
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC
°C/W
JA
TSSOP
128
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. V and V should be constrained to the range GND v (V or V ) v V . Unused inputs must always be tied to an appropriate logic voltage
in
out
in
out
CC
level (e.g., either GND or V ). Unused outputs must be left open.
CC
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
http://onsemi.com
2
MC74VHC244
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
0
V
CC
V
OUT
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
0
125
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V + 0.3 V
= 5.0 V + 0.5 V
100
20
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 2. Failure Rate vs. Time Junction Temperature
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
T
A
≤ 85°C
−55°C ≤ T ≤ 125°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
1.5
Min
Max
Unit
V
V
V
Minimum High−Level
Input Voltage
2.0
1.5
1.5
1.5
V
IH
3.0 to
5.5
V
CCX
V
CCX
V
CCX
V
CCX
0.7
0.7
0.7
0.7
Maximum Low−Level
Input Voltage
2.0
0.5
0.5
0.5
V
V
IL
3.0 to
5.5
V
CCX
V
CCX
V
CCX
0.3
0.3
0.3
V
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
Maximum High−Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
I
= −50 mA
OH
V
IN
= V or V
IH
I
= −4 mA
3.0
4.5
2.58
3.94
2.48
3.8
2.34
3.66
OH
I
= −8 mA
OH
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low−Level
Output Voltage
V
IH
I
OL
= 50 mA
V
IN
= V or V
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OH
I
OH
I
I
Input Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
IN
IN
Maximum 3−State
Leakage Current
V
V
= V or V
IL
5.5
0.25
2.5
2.5
OZ
IN
IH
= V or GND
OUT
CC
I
Maximum Quiescent
Supply Current
(per package)
V
IN
= V or GND
5.5
4.0
40.0
40.0
mA
CC
CC
http://onsemi.com
3
MC74VHC244
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
−55°C 3 T
A
3 125°C
T
A
= 25°C
T 3 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Unit
t
t
t
,
Maximum Propagation
Delay, A to YA or
B to YB
V
V
V
5.8
8.3
8.4
11.9
1.0
1.0
10.0
13.5
1.0
1.0
11.0
14.5
ns
PLH
t
CC
CC
CC
L
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
3.9
5.4
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.5
9.5
L
C = 50 pF
L
,
Output Enable Time
OEA to YA or
OEB to YB
= 3.3 0.3 V C = 15 pF
6.6
9.1
10.6
14.1
1.0
1.0
12.5
16.0
1.0
1.0
13.5
17.0
ns
ns
ns
PZL
t
L
R = 1 kW
C = 50 pF
L
PZH
L
V
CC
= 5.0 0.5 V C = 15 pF
4.7
6.2
7.3
9.3
1.0
1.0
8.5
10.5
1.0
1.0
9.5
11.5
L
R = 1 kW
C = 50 pF
L
L
,
Output Disable Time
OEA to YA or
OEB to YB
V
CC
= 3.3 0.3 V C = 50 pF
10.3
14.0
9.2
1.5
1.0
10
1.0
16.0
10.5
1.5
1.0
17.0
11.5
1.5
PLZ
L
t
R = 1 kW
PHZ
L
V
CC
= 5.0 0.5 V C = 50 pF
L
R = 1 kW
6.7
1.0
1.0
L
t
,
Output to Output Skew
V
= 3.3 0.3 V C = 50 pF
OSLH
CC L
t
(Note 6)
OSHL
V
CC
= 5.0 0.5 V C = 50 pF
1.0
1.5
L
(Note 6)
C
Maximum Input
Capacitance
4
6
10
10
pF
pF
in
C
Maximum Three−State
Output Capacitance
(Output in High−Impedance
State)
out
Typical @ 25°C, V = 5.0V
CC
19
C
Power Dissipation Capacitance (Note 7)
= |t
pF
PD
6. Parameter guaranteed by design. t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
CC
PD CC in CC PD
2
dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.6
0.9
−0.9
3.5
OLP
OL
Quiet Output Minimum Dynamic V
−0.6
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
http://onsemi.com
4
MC74VHC244
SWITCHING WAVEFORMS
V
CC
V
CC
A or B
OEA or OEB
50%
50%
GND
GND
t
t
PLZ
PZL
HIGH
t
t
PHL
PLH
IMPEDANCE
YA or YB
50% V
CC
YA or YB
YA or YB
50% V
CC
V
V
+0.3V
OL
t
t
PHZ
PZH
-0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
OUTPUT
TESTING t AND t
PLZ
.
PZL
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
INPUT
Figure 7. Input Equivalent Circuit
http://onsemi.com
5
MC74VHC244
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
0.25
T A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
C
T
http://onsemi.com
6
MC74VHC244
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006)
T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT
PLANE
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74VHC244/D
相关型号:
©2020 ICPDF网 联系我们和版权申明