MC74VHC259DTR2G [ONSEMI]
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter, TSSOP-16, 2500-REEL;
| 型号： | MC74VHC259DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter, TSSOP-16, 2500-REEL 解码器 驱动器 转换器 电平转换器 逻辑集成电路 光电二极管 双倍数据速率 |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non–addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one–of–eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
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MARKING DIAGRAMS
16
1
9
8
VHC259
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
16
9
VHC259
TSSOP–16
DT SUFFIX
CASE 948F
AWLYWW
1
8
The MC74VHC259 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
16
9
VHC259
ALYW
• High Speed: t = 7.6 ns (Typ) at V = 5 V
PD
CC
SOIC EIAJ–16
M SUFFIX
CASE 966
• Low Power Dissipation: I = 2 µA (Max) at T = 25°C
CC
A
1
8
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• CMOS–Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
A
= Assembly Location
L, WL = Wafer Lot
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
Y, YY = Year
W, WW = Work Week
• ESD Performance: HBM > 2000 V
ORDERING INFORMATION
A0
A1
1
2
16
15
V
CC
Device
Package
SOIC–16
SOIC–16
TSSOP–16
Shipping
48 Units/Rail
RESET
MC74VHC259D
MC74VHC259DR2
MC74VHC259DT
3
4
14
13
A2
Q0
Q1
ENABLE
DATA IN
Q7
2500 Units/Reel
96 Units/Rail
5
6
7
8
12
11
10
9
Q2
Q3
Q6
Q5
Q4
MC74VHC259DTR2 TSSOP–16 2500 Units/Reel
SOIC
MC74VHC259M
50 Units/Rail
EIAJ–16
GND
SOIC
EIAJ–16
MC74VHC259MEL
2000 Units/Reel
Figure 1. Pin Assignment
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
April, 2001 – Rev. 2
MC74VHC259/D
MC74VHC259
4
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
A0
A1
A2
ADDRESS
INPUTS
6
7
NONINVERTING
OUTPUTS
9
10
11
12
13
DATA IN
PIN 16 = V
CC
PIN 8 = GND
15
14
RESET
ENABLE
Figure 2. Logic Diagram
BIN/OCT
DMUX
0
0
1
7
1
2
3
1
2
3
4
5
6
7
8
4
5
6
7
8
A0
A1
A2
A0
A1
A2
1
2
4
0
Q0
Q1
Q2
Q3
Q4
0
2
Q0
Q1
Q2
Q3
Q4
G
1
2
3
4
5
2
3
4
10
11
12
13
14
15
10
11
12
13
14
15
ID
EN
R
ID
Q5
Q6
Q7
5
Q5
Q6
Q7
EN
R
6
7
6
7
Figure 3. IEC Logic Symbol
LATCH SELECTION TABLE
MODE SELECTION TABLE
Address Inputs
Enable Reset
Mode
Latch
A
Addressed
C
B
L
H
Addressable Latch
H
L
H
L
Memory
L
L
L
L
L
Q0
Q1
8–Line Demultiplexer
H
H
L
Reset
L
L
H
H
L
Q2
Q3
H
H
H
H
H
L
L
L
H
L
Q4
Q5
Q6
Q7
H
H
H
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2
MC74VHC259
13
4
5
D
D
ăDATA INPUT
Q0
Q1
6
D
Q2
7
D
D
D
Q3
Q4
Q5
ăA0
ă3 TO 8
ADDRESS
INPUTS
ăA1
ăA2
DECODER
9
10
14
ăENABLE
11
D
Q6
12
D
Q7
15
ăRESET
Figure 4. Expanded Logic Diagram
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3
MC74VHC259
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
–0.5 to +7.0
–0.5 to +7.0
CC
IN
V
DC Output Voltage
–0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
–20
$20
$25
$75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
Storage Temperature Range
ESD Withstand Voltage
–65 to +150
°C
STG
V
Human Body Model (Note 2.)
Machine Model (Note 3.)
>2000
>200
V
ESD
Charged Device Model (Note 4.)
>2000
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 5.)
$300
143
164
mA
LATCH–UP
CC
q
Thermal Resistance, Junction to Ambient
SOIC Package
TSSOP
°C/W
JA
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
0
V
CC
V
OUT
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
–55
0
125
20
°C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3 V + 0.3 V
= 5.0 V + 0.5 V
f
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 5. Failure Rate vs. Time Junction Temperature
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4
MC74VHC259
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
–55°C ≤ T ≤ 125°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
V
V
V
Minimum High–Level
Input Voltage
2.0
3.0to 5.5
1.5
1.5
V
IH
V
0.7
V
0.7
CCX
CCX
Maximum Low–Level
Input Voltage
2.0
3.0to 5.5
0.5
0.5
V
V
IL
V
0.3
V
0.3
CCX
CCX
V
I
= V or V
= –50 µA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
Maximum High–Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
OH
V
IN
= V or V
V
V
V
IH
I
OL
= 4 mA
= 8 mA
3.0
4.5
2.58
3.94
2.48
3.8
I
OL
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low–Level
Output Voltage
IH
I
OL
= 50 µA
V
IN
= V or V
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
I
OL
I
I
Input Leakage Current
V
= 5.5 V or GND
0 to 5.5
5.5
±0.1
±1.0
µA
µA
IN
IN
Maximum Quiescent
Supply Current
V
IN
= V or GND
4.0
40.0
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
–55°C ≤ T
≤
A
125°C
T
A
= 25°C
T ≤ 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Maximum
Propagation Delay,
Data to Output
Test Conditions
Unit
t
t
,
ns
V
V
V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
C = 15pF
C = 50pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
CC
CC
CC
L
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
(Figures 6 and 11)
C = 50pF
L
t
t
,
Maximum
ns
C = 15pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
Propagation Delay,
Address Select to
Output
C = 50pF
L
V
CC
= 5.0 ± 0.5V
C = 15pF
L
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
C = 50pF
L
(Figures 7 and 11)
t
t
,
Maximum
ns
ns
V
CC
V
CC
V
CC
V
CC
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
C = 15pF
C = 50pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
L
Propagation Delay,
Enable to Output
(Figures 8 and 11)
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50pF
L
t
Maximum
C = 15pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PHL
L
Propagation Delay,
Reset to Output
(Figures 9 and 11)
C = 50pF
L
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50pF
L
C
C
Maximum Input
Capacitance
6
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0V
CC
30
Power Dissipation Capacitance (Note 6.)
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no–load dynamic
PD CC in CC PD
CC(OPR
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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5
MC74VHC259
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= ≤ 85°C
T = ≤ 125°C
A
Min Typ Max Min Max
Min
5.5
5.5
4.5
3.0
2.0
2.0
Max
Symbol
Parameter
Test Conditions
Unit
t
Minimum Pulse Width, Reset or Enable
(Figure 10)
ns
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
5.0
5.0
4.5
3.0
2.0
2.0
5.5
5.5
4.5
3.0
2.0
2.0
w
su
h
t
t
Minimum Setup Time, Address or Data to Enable
(Figure 10)
ns
ns
ns
Minimum Hold Time, Enable to Address or Data
(Figure 8 or 9)
t t
Maximum Input, Rise and Fall Times
(Figure 6)
400
200
300
100
300
100
r,
f
V
CC
DATA IN
GND
t
r
t
f
V
CC
ADDRESS
SELECT
V
CC
50%
50%
50%
GND
DATA IN
GND
t
t
PLH
PHL
V
CC
50%
GND
t
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 6. Switching Waveform
Figure 7. Switching Waveform
V
CC
V
CC
GND
DATA IN
ENABLE
DATA IN
RESET
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GND
t
t
PHL
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 8. Switching Waveform
Figure 9. Switching Waveform
DATA IN
OR
TEST POINT
OUTPUT
V
CC
50%
ADDRESS
SELECT
GND
t
h(H)
t
DEVICE
UNDER
TEST
h(H)
t
su
t
su
C *
L
ENABLE
V
CC
50%
GND
*Includes all probe and jig capacitance
Figure 10. Switching Waveform
Figure 11. Test Circuit
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6
MC74VHC259
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
B
0.25 (0.010)
1
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45
K
_
C
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
K
M
P
R
D
16 PL
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
TSSOP–16
DT SUFFIX
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T
U
V
S
U
0.15 (0.006) T
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
2X L/2
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
B
–U–
SECTION N–N
L
J
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
PIN 1
IDENT.
8
1
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
–V–
N
F
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
A
B
4.90
4.30
---
0.193
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
–W–
C
G
H
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
J
0.10 (0.004)
J1
K
H
DETAIL E
SEATING
PLANE
–T–
D
G
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
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7
MC74VHC259
PACKAGE DIMENSIONS
SOIC EIAJ–16
M SUFFIX
CASE 966–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
16
9
L
E
Q
1
H
E
M
_
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
---
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.18
9.90
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.27 0.007
b
c
D
E
10.50 0.390
5.45 0.201
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
0
10
0.90 0.028
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
1
Z
0.78
---
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC74VHC259/D
相关型号：
MC74VHC259_06
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL-Compatible Inputs
ONSEMI
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