MC74VHC540DTR2 [ONSEMI]
AHC/VHC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20;
| 型号： | MC74VHC540DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, TSSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC540
Octal Bus Buffer
Inverting
The MC74VHC540 is an advanced high speed CMOS inverting
octal bus buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The MC74VHC540 features inputs and outputs on opposite sides
of the package and two AND−ed active−low output enables. When
either OE1 or OE2 are high, the terminal outputs are in the high
impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
SOIC−20
DW SUFFIX
CASE 751D
VHC540
AWLYYWWG
20
20
1
1
Features
VHC
540
TSSOP−20
DT SUFFIX
CASE 948E
• High Speed: t = 3.7 ns (Typ) at V = 5.0 V
PD
CC
ALYWG
• Low Power Dissipation: I = 4.0 μA (Max) at T = 25°C
CC
A
G
1
• High Noise Immunity: V
= V
= 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 1.2 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
PIN ASSIGNMENT
OE1
1
20
V
CC
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 124 FETs or 31 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
A1
A2
A3
2
3
4
5
6
7
8
9
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A4
A5
A6
A7
A8
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
13 Y6
12 Y7
11 Y8
GND 10
DATA
INPUTS
INVERTING
OUTPUTS
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
L
H
L
L
X
L
H
X
X
H
L
Z
A8
X
H
Z
1
OE1
OUTPUT
ENABLES
19
OE2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 5
MC74VHC540/D
MC74VHC540
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must be
taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
I
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
range GND v (V or V ) v V
.
out
CC
in
out
CC
Unused inputs must always be tied
75
CC
to an appropriate logic voltage level
(e.g., either GND or V ). Unused
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute−maximum−rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
−55
+ 125
_C
ns/V
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
= 3.3V 0.3V
=5.0V 0.5V
0
0
100
20
f
DC ELECTRICAL CHARACTERISTICS
T = 25°C
A
T = − 55 to 125°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
1.50
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= − 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
OH
V
in
= V or V
IH
IL
OH
OH
I
I
= − 4mA
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
OL
I
OL
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
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2
MC74VHC540
DC ELECTRICAL CHARACTERISTICS
T = 25°C
A
T = − 55 to 125°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 5.5
0.1
1.0
μA
in
in
I
Maximum Three−State
Leakage Current
= V or V
IH
5.5
5.5
0.25
4.0
2.5
μA
μA
OZ
in
IL
V
= V or GND
out CC
I
Maximum Quiescent
Supply Current
V
in
= V or GND
40.0
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T = 25°C
A
T = − 55 to 125°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Maximum Propagation Delay,
A to Y
(Figures 1 and 3)
V
V
V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
C = 15pF
C = 50pF
L
4.8
7.3
7.0
10.5
1.0
1.0
8.5
12.0
ns
PLH
CC
CC
CC
L
PHL
C = 15pF
3.7
5.2
5.0
7.0
1.0
1.0
6.0
8.0
L
C = 50pF
L
t
t
,
Output Enable TIme,
OEn to Y
(Figures 2 and 4)
C = 15pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
ns
PZL
L
R = 1kΩ
C = 50pF
L
PZH
L
V
CC
= 5.0 0.5V
C = 15pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
L
R = 1kΩ
C = 50pF
L
L
t
t
,
Output Disable Time,
OEn to Y
(Figures 2 and 4)
V
CC
= 3.3 0.3V
C = 50pF
L
11.2
15.4
8.8
1.5
1.0
10
1.0
17.5
PLZ
R = 1kΩ
PHZ
L
V
CC
= 5.0 0.5V
C = 50pF
L
6.0
1.0
10.0
R = 1kΩ
L
t
,
Output to Output Skew
V
CC
= 3.3 0.3V
C = 50pF
L
ns
ns
OSLH
t
(Note 1)
OSHL
V
CC
= 5.0 0.5V
C = 50pF
L
(Note 1)
C
in
Maximum Input Capacitance
4
6
10
pF
pF
C
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
out
Typical @ 25°C, V = 5.0V
CC
17
C
PD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. t = |t − t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
PD CC in CC PD
2
dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T = 25°C
A
Typ
Max
1.2
Symbol
Parameter
Unit
V
V
OLP
Quiet Output Maximum Dynamic V
0.9
OL
V
Quiet Output Minimum Dynamic V
− 0.9
− 1.2
3.5
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
1.5
V
ILD
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3
MC74VHC540
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
50%
50%
V
CC
GND
A
50%
t
t
PLZ
PZL
HIGH
IMPEDANCE
GND
t
t
PLH
PHL
50% V
t
Y
Y
CC
V
V
+0.3V
-0.3V
OL
t
50% V
PZH
PHZ
CC
Y
OH
50% V
CC
HIGH
IMPEDANCE
Figure 2.
Figure 3.
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
.
PZL
CC
TESTING t AND t
1kΩ
OUTPUT
OUTPUT
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
INPUT EQUIVALENT CIRCUIT
INPUT
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4
MC74VHC540
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC540DWR2G
SOIC−20
(Pb−Free)
1000 Units / Tape & Reel
2500 Units / Tape & Reel
MC74VHC540DTR2G
TSSOP−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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5
MC74VHC540
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
U
0.15 (0.006) T
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006) T
U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
M
0
8
8
_
_
_
_
−T− SEATING
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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6
MC74VHC540
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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MC74VHC540/D
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