MC74VHC540MEL [ROCHESTER]
AHC/VHC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, PLASTIC, SOIC-20;
| 型号： | MC74VHC540MEL |
| 厂家： | 
Rochester Electronics |
| 描述： | AHC/VHC SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, PLASTIC, SOIC-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：862K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC74VHC540 is an advanced high speed CMOS inverting octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC540 features inputs and outputs on opposite sides of the
package and two AND–ed active–low output enables. When either OE1 or
OE2 are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
•
•
•
•
•
•
•
•
•
•
•
High Speed: t
= 3.7ns (Typ) at V
= 5V
= 4µA (Max) at T = 25°C
PD
Low Power Dissipation: I
CC
CC
A
High Noise Immunity: V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
= V
= 28% V
NIH
NIL CC
Designed for 2V to 5.5V Operating Range
Low Noise: V
= 1.2V (Max)
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 124 FETs or 31 Equivalent Gates
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC WIDE
TSSOP
SOIC EIAJ
LOGIC DIAGRAM
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
PIN ASSIGNMENT
OE1
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
V
CC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
DATA
INPUTS
INVERTING
OUTPUTS
GND 10
A8
1
OE1
FUNCTION TABLE
Inputs
OUTPUT
ENABLES
19
OE2
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
4/98
REV 1
121
Motorola, Inc. 1998
MC74VHC540
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V
CC
+ 0.5
V
out
I
IK
– 20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
± 20
± 25
± 75
OK
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in out
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V
).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 40
+ 85
C
t , t
r f
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
= 3.3V ±0.3V
=5.0V ±0.5V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Unit
Min
1.50
Typ
Max
Min
Max
V
IH
Minimum High–Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low–Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High–Level
Output Voltage
V
= V or V
IH
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IL
IL
I
= – 50µA
OH
V
in
= V or V
IH
I
I
= – 4mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
= – 8mA
V
OL
Maximum Low–Level
Output Voltage
V
= V or V
IH IL
= 50µA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
I
OL
V
in
= V or V
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
MOTOROLA
122
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
MC74VHC540
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = – 40 to 85°C
A
V
CC
V
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 5.5
± 0.1
± 1.0
µA
in
in
I
Maximum Three–State
Leakage Current
= V or V
IL
5.5
± 0.25
± 2.5
µA
µA
OZ
CC
in
IH
or GND
V
out
= V
CC
or GND
CC
I
Maximum Quiescent
Supply Current
V
in
= V
5.5
4.0
40.0
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= – 40 to 85°C
Symbol
Parameter
Test Conditions
Unit
Min
Typ
Max
Min
1.0
Max
t
t
,
Maximum Propagation Delay,
A to Y
(Figures 1 and 3)
V
V
V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
C
C
= 15pF
= 50pF
4.8
7.3
7.0
10.5
8.5
12.0
ns
PLH
CC
CC
CC
L
L
1.0
PHL
C
C
= 15pF
= 50pF
3.7
5.2
5.0
7.0
1.0
1.0
6.0
8.0
L
L
t
t
,
Output Enable TIme,
OEn to Y
(Figures 2 and 4)
C
C
= 15pF
= 50pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
ns
PZL
L
L
R
= 1kΩ
PZH
L
V
R
= 5.0 ± 0.5V
= 1kΩ
C
C
= 15pF
= 50pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
CC
L
L
L
t
t
,
Output Disable Time,
OEn to Y
(Figures 2 and 4)
V
R
= 3.3 ± 0.3V
= 1kΩ
C
C
C
C
= 50pF
= 50pF
= 50pF
= 50pF
11.2
15.4
8.8
1.5
1.0
10
1.0
17.5
10.0
PLZ
CC
L
L
L
L
PHZ
L
V
R
= 5.0 ± 0.5V
= 1kΩ
6.0
1.0
CC
L
t
t
,
Output to Output Skew
V
CC
= 3.3 ± 0.3V
(Note 1.)
ns
ns
OSLH
OSHL
V
= 5.0 ± 0.5V
CC
(Note 1.)
C
Maximum Input Capacitance
4
6
10
pF
pF
in
C
Maximum Three–State Output
Capacitance (Output in High
Impedance State)
out
Typical @ 25°C, V
= 5.0V
CC
C
Power Dissipation Capacitance (Note 2.)
pF
17
PD
1. Parameter guaranteed by design. t = |t – t
|, t
= |t
– t
|.
OSLH PLHm PLHn OSHL
PHLm PHLn
2. C
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Averageoperatingcurrentcanbeobtainedbytheequation:I
=C
V
f
+I
/8(perbit).C isusedtodeterminetheno–load
PD
CC(OPR)
PD CC in CC
2
dynamic power consumption; P = C
V
CC
f
+ I
V
.
D
PD
in CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V
= 5.0V)
r
f
L
CC
T
A
= 25°C
Symbol
Parameter
Unit
V
Typ
Max
V
OLP
Quiet Output Maximum Dynamic V
0.9
1.2
– 1.2
3.5
OL
V
OLV
Quiet Output Minimum Dynamic V
– 0.9
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
123
MOTOROLA
MC74VHC540
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
50%
50%
V
CC
GND
A
50%
t
t
PZL PLZ
HIGH
IMPEDANCE
GND
t
t
PLH
PHL
50% V
CC
Y
Y
V
+0.3V
–0.3V
OL
t
t
50% V
CC
PZH PHZ
Y
V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
TEST
POINT
POINT
CONNECT TO V WHEN
CC
1kΩ
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t AND t
AND t .
PZL
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
INPUT EQUIVALENT CIRCUIT
INPUT
MOTOROLA
124
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
SEMICONDUCTOR TECHNICAL DATA
Device Nomenclature
MC 74 VHCX YYY A ZZ
Motorola
Package Type
Circuit Identifier
• D
= Plastic Narrow JEDEC SOIC
• DW = Plastic Wide JEDEC SOIC
Temperature Range
• M
= Plastic EIAJ SOIC
• 74 = –40 to +85°C
• DT = Plastic TSSOP
Output Type
Family Identifier
• Indicates Full CMOS Output Swing
(Shown on VHCT Only; all VHC parts
have full CMOS output swings)
• VHC
= Very High Speed CMOS
• VHCT = Very High Speed CMOS,
TTL Compatible Inputs
• VHCU = Very High Speed CMOS,
Function Type
Unbuffered
MOTOROLA
202
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–A–
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
P 7 PL
–B–
M
M
0.25 (0.010)
B
MILLIMETERS
INCHES
MIN MAX
G
F
R X 45°
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
C
A
B
C
D
F
G
J
K
M
P
8.55
3.80
1.35
0.35
0.40
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
J
M
SEATING
PLANE
K
D 14 PL
1.27 BSC
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
M
S
S
0.25 (0.010)
T
B
A
0°
7°
5.80
0.25
6.20
0.50
0.228 0.244
0.010 0.019
R
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
–U–
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
–V–
A
B
C
4.90
4.30
–––
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
––– 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N–N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
0.19
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
SEATING
PLANE
–T–
H
G
DETAIL E
D
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
203
MOTOROLA
Case Outlines
(continued)
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
14
8
Q
1
H
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN MAX
––– 0.081
A
e
DIM MIN
MAX
c
A
–––
0.05
0.35
0.18
2.05
A
0.20 0.002 0.008
0.50 0.014 0.020
1
b
c
0.27 0.007
0.011
D
E
e
9.90 10.50 0.390 0.413
b
A
1
5.10
5.45 0.201 0.215
M
1.27 BSC
0.050 BSC
8.20 0.291 0.323
0.85 0.020 0.033
1.50 0.043 0.059
0.13 (0.005)
0.10 (0.004)
H
7.40
0.50
1.10
0
0.70
–––
E
0.50
L
E
M
10
0.90 0.028 0.035
1.42 ––– 0.056
10
0
Q
1
Z
MOTOROLA
204
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
Case Outlines
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B
–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
MIN MAX
DIM MIN
MAX
A
B
C
D
F
G
J
K
M
P
9.80 10.00
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
F
K
R X 45°
3.80
1.35
0.35
0.40
4.00
1.75
0.49
1.25
C
1.27 BSC
–T
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
J
SEAT–ING
M
PLANE
D 16 PL
0°
7°
5.80
0.25
6.20
0.50
0.229 0.244
0.010 0.019
M
S
S
0.25 (0.010)
T
B
A
R
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
S
0.15 (0.006) T U
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
16
9
2X L/2
J1
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
B
–U–
SECTION N–N
L
0.25 (0.010) PER SIDE.
J
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
–V–
MIN
MAX
0.200
0.177
0.047
0.006
0.030
N
A
B
C
4.90
4.30
–––
5.10 0.193
4.50 0.169
1.20
F
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.011
0.008
0.006
0.012
0.010
–W–
C
6.40 BSC
0.252 BSC
0.10 (0.004)
M
0
8
0
8
H
DETAIL E
SEATING
PLANE
–T–
D
G
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
205
MOTOROLA
Case Outlines
(continued)
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 966–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
A
–––
0.05
0.35
0.18
9.90
5.10
2.05
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
MOTOROLA
206
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
Case Outlines
DW SUFFIX
PLASTIC SOIC WIDE PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
DIM MIN MAX
INCHES
20X D
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
A
B
C
D
F
12.65
7.40
2.35
0.35
0.50
12.95 0.499
7.60 0.292
2.65 0.093
0.49 0.014
0.90 0.020
M
S
S
0.010 (0.25) T A
B
F
G
J
K
M
P
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32 0.010
0.25 0.004
0.012
0.009
7
R X 45
7
0
10.05
0.25
10.55 0.395
0.75 0.010
0.415
0.029
C
R
SEATING
PLANE
–T–
M
18X G
K
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
207
MOTOROLA
Case Outlines
(continued)
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN MAX
––– 0.081
e
A
DIM MIN
MAX
c
A
A
–––
0.05
0.35
0.18
2.05
0.20 0.002 0.008
0.50 0.014 0.020
0.27 0.007
1
b
c
0.011
D
E
e
12.35 12.80 0.486 0.504
A
b
1
5.10
5.45 0.201 0.215
1.27 BSC
0.050 BSC
8.20 0.291 0.323
0.85 0.020 0.033
1.50 0.043 0.059
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
0
0.70
–––
E
L
L
E
M
Q
10
0.90 0.028 0.035
0.81 ––– 0.032
10
0
1
Z
MOTOROLA
208
Very High–Speed CMOS Logic
VHC Data – DL203 – Rev 2
相关型号：
MC74VHC540MR2
Bus Driver, AHC/VHC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20
MOTOROLA
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