MC74VHC74MR2 [ONSEMI]
AHC/VHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SOIC-14;
| 型号： | MC74VHC74MR2 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, EIAJ, SOIC-14 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC74
Dual D-Type Flip-Flop
with Set and Reset
The MC74VHC74 is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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MARKING
DIAGRAMS
14
1
SOIC−14
D SUFFIX
CASE 751A
VHC74G
AWLYWW
14
1
14
Features
VHC
74
• High Speed: f
= 170MHz (Typ) at V = 5V
CC
TSSOP−14
DT SUFFIX
CASE 948G
max
• Low Power Dissipation: I = 2mA (Max) at T = 25°C
ALYWG
CC
A
1
G
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
1
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
14
• Designed for 2.0 V to 5.5 V Operating Range
SOEIAJ−14
M SUFFIX
CASE 965
VHC74
ALYWG
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
1
1
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
A
= Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Outputs
13
12
11
10
1
2
3
4
RD1
D1
RD2
D2
SD
RD
CP
D
Q
Q
9
8
5
6
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*
H
L
L
H
H*
L
Q2
Q2
Q1
Q1
CP1
SD1
CP2
SD2
H
L
H
No Change
No Change
No Change
Figure 1. LOGIC DIAGRAM
*Both outputs will remain high as long as Set and Re-
set are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 8
MC74VHC74/D
MC74VHC74
RD1
D1
1
2
14
13 RD2
12
V
CC
3
4
CP1
SD1
D2
11 CP2
10 SD2
Q1
Q1
5
6
7
9
8
Q2
Q2
GND
Figure 2. PIN ASSIGNMENT
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
−20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
50
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
Storage Temperature
–65 to +150
_C
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating
SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
in
DC Input Voltage
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
Operating Temperature, All Package Types
−55
+ 125
_C
ns/V
A
t , t
r
Input Rise and Fall Time
V
CC
= 3.3V 0.3V
=5.0V 0.5V
0
0
100
20
f
V
CC
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2
MC74VHC74
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = −55°C to +125°C
A
V
CC
V
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
CC
1.50
CC
V
V
x 0.7
V
x 0.7
V
Maximum Low−Level
2.0
0.50
CC
0.50
CC
V
V
IL
Input Voltage
3.0 to 5.5
V
x 0.3
V
x 0.3
V
OH
Minimum High−Level
Output Voltage
V
OH
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
= − 50mA
V
in
= V or V
IH
IL
I
I
= − 4mA
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
= 50mA
V
in
= V or V
IH
IL
I
OL
I
OL
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 5.5
0.1
1.0
mA
mA
in
in
I
Maximum Quiescent
Supply Current
= V or GND
5.5
2.0
20.0
CC
in
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = −55°C to +125°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
,
Maximum Propagation Delay,
CP to Q or Q
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
C = 15pF
C = 50pF
L
6.7
9.2
11.9
15.4
1.0
1.0
14.0
17.5
ns
PLH
L
t
PHL
C = 15pF
4.6
6.1
7.3
9.3
1.0
1.0
8.5
10.5
L
C = 50pF
L
t
,
Maximum Propagation Delay,
SD or RD to Q or Q
C = 15pF
7.6
10.1
12.3
15.8
1.0
1.0
14.5
18.0
ns
PLH
L
t
C = 50pF
L
PHL
C = 15pF
4.8
6.3
7.7
9.7
1.0
1.0
9.0
11.0
L
C = 50pF
L
f
Maximum Clock Frequency
(50% Duty Cycle)
C = 15pF
80
50
125
75
70
45
MHz
max
L
C = 50pF
L
C = 15pF
130
90
170
115
110
75
L
C = 50pF
L
C
Maximum Input Capacitance
4
10
10
pF
pF
in
Typical @ 25°C, V = 5.0V
CC
25
C
Power Dissipation Capacitance (Note 1)
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /2 (per flip−flop). C is used to determine the
CC
CC(OPR
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
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3
MC74VHC74
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
Guaranteed Limit
V
CC
V
T
A
= 25_C
6.0
5.0
T = −55°C to +125°C
A
Symbol
Parameter
Minimum Pulse Width, CP
Unit
t
w
3.3 0.3
5.0 0.5
7.0
5.0
ns
t
Minimum Pulse Width, RD or SD
Minimum Setup Time, D to CP
3.3 0.3
5.0 0.5
6.0
5.0
7.0
5.0
ns
ns
ns
ns
w
t
su
3.3 0.3
5.0 0.5
6.0
5.0
7.0
5.0
t
Minimum Hold Time, D to CP
3.3 0.3
5.0 0.5
0.5
0.5
0.5
0.5
h
t
Minimum Recovery Time, SD or RD to CP
3.3 0.3
5.0 0.5
5.0
3.0
5.0
3.0
rec
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC74DR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
MC74VHC74DTG
MC74VHC74DTR2G
MC74VHC74MELG
TSSOP−14
TSSOP−14
96 Units / Rail
2500 Tape & Reel
2000 Tape & Reel
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC74
t
w
V
CC
50%
SD or RD
Q or Q
GND
V
CC
t
CP
PHL
50%
GND
50% V
CC
t
w
1/f
max
t
PLH
t
t
PHL
PLH
50% V
CC
Q or Q
CP
50% V
CC
t
rec
Q or Q
V
CC
50%
GND
Figure 3.
Figure 4.
Switching Waveforms
TEST POINT
OUTPUT
VALID
V
CC
50%
DEVICE
D
UNDER
TEST
GND
C *
L
t
su
t
h
V
CC
50%
CP
GND
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
INPUT
Figure 7. Input Equivalent Circuit
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5
MC74VHC74
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
J
M
K
SEATING
1.27 BSC
D 14 PL
PLANE
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MC74VHC74
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
J1
K
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
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7
MC74VHC74
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
14
8
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
---
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
e
A
---
0.05
0.35
0.10
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
D
E
e
10.50 0.390
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
L
0.10 (0.004)
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
---
1
Z
1.42
---
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC74/D
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