MC74VHCT126AM [ONSEMI]

Quad Bus Buffer; 四路总线缓冲器
MC74VHCT126AM
型号: MC74VHCT126AM
厂家: ONSEMI    ONSEMI
描述:

Quad Bus Buffer
四路总线缓冲器

总线驱动器 总线收发器 逻辑集成电路 光电二极管
文件: 总8页 (文件大小:179K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
with 3–State Control Inputs  
The MC74VHCT126A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves  
noninverting high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
The MC74VHCT126A requires the 3–state control input (OE) to be  
set Low to place the output into high impedance.  
http://onsemi.com  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3V to 5.0V, because it has  
full 5V CMOS level output swings.  
The VHCT126A input structures provide protection when voltages  
between 0V and 5.5V are applied, regardless of the supply voltage.  
14–LEAD SOIC  
D SUFFIX  
CASE 751A  
14–LEAD TSSOP  
DT SUFFIX  
CASE 948G  
The output structures also provide protection when V  
= 0V. These  
CC  
input and output structures help prevent device destruction caused by  
supply voltage – input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
PIN CONNECTION AND  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
MARKING DIAGRAM (Top View)  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
IL IH  
Y1  
3
4
A4  
OE2  
11 Y4  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
A2  
Y2  
5
6
7
10 OE3  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
9
8
A3  
Y3  
GND  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
LOGIC DIAGRAM  
Active–High Output Enables  
ORDERING INFORMATION  
2
1
3
6
A1  
Y1  
Device  
Package  
SOIC  
Shipping  
OE1  
MC74VHCT126AD  
MC74VHCT126ADT  
MC74VHCT126AM  
55 Units/Rail  
96 Units/Rail  
50 Units/Rail  
5
4
TSSOP  
A2  
Y2  
Y3  
FUNCTION TABLE  
SOIC EIAJ  
OE2  
VHCT126A  
9
8
A3  
Inputs Output  
10  
A
OE  
Y
OE3  
H
L
X
H
H
L
H
L
Z
12  
13  
11  
A4  
Y4  
OE4  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 1  
MC74VHCT126A/D  
MC74VHCT126A  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this high–impedance cir-  
V
DC Supply Voltage  
DC Input Voltage  
– 0.5 to + 7.0  
– 0.5 to + 7.0  
CC  
V
V
in  
V
DC Output Voltage  
Input Diode Current  
Output Diode Current  
– 0.5 to V  
CC  
+ 0.5  
V
out  
I
IK  
– 20  
mA  
mA  
mA  
mA  
mW  
cuit. For proper operation, V and  
in  
I
± 20  
± 25  
± 50  
OK  
V
should be constrained to the  
out  
range GND (V or V  
)
V
CC  
.
I
DC Output Current, per Pin  
DC Supply Current, V and GND Pins  
in out  
out  
CC  
Unused inputs must always be  
tied to an appropriate logic voltage  
I
CC  
level (e.g., either GND or V  
).  
P
D
Power Dissipation in Still Air,  
SOIC Packages†  
TSSOP Package†  
500  
450  
CC  
Unused outputs must be left open.  
T
stg  
Storage Temperature  
– 65 to + 150  
C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or  
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not  
implied.  
†Derating — SOIC Packages: – 7 mW/ C from 65 to 125 C  
TSSOP Package: – 6.1 mW/ C from 65 to 125 C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
4.5  
0
Max  
5.5  
Unit  
V
V
CC  
DC Supply Voltage  
DC Input Voltage  
DC Output Voltage  
V
in  
5.5  
V
V
out  
0
V
CC  
V
T
Operating Temperature, All Package Types  
Input Rise and Fall Time =5.0V ±0.5V  
– 40  
0
+ 85  
20  
C
A
t , t  
r f  
V
CC  
ns/V  
DC ELECTRICAL CHARACTERISTICS  
T
A
= 25°C  
T
85°C  
T 125°C  
A
A
V
(V)  
CC  
Symbol  
Parameter  
Test Conditions  
Unit  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
V
IH  
Minimum High–Level Input  
Voltage  
3.0  
4.5  
5.5  
1.2  
2.0  
2.0  
1.2  
2.0  
2.0  
1.2  
2.0  
2.0  
V
V
Maximum Low–Level Input  
Voltage  
3.0  
4.5  
5.5  
0.53  
0.8  
0.8  
0.53  
0.8  
0.8  
0.53  
0.8  
0.8  
V
V
IL  
V
OH  
Minimum High–Level  
Output Voltage  
V
= V or V  
IH  
3.0  
4.5  
2.9  
4.4  
3.0  
4.5  
2.9  
4.4  
2.9  
4.4  
IN  
IL  
IL  
I
= – 50µA  
OH  
V
IN  
= V or V  
IH  
IL  
V
= V or V  
IH  
= – 4mA  
= – 8mA  
IN  
OH  
OH  
I
I
3.0  
4.5  
2.58  
3.94  
2.48  
3.80  
2.34  
3.66  
V
OL  
Maximum Low–Level  
Output Voltage  
V
= V or V  
IH  
3.0  
4.5  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
IN  
IL  
IL  
I
= 50µA  
OL  
V
IN  
= V or V  
IH  
IL  
V
= V or V  
IH  
= 4mA  
= 8mA  
IN  
OL  
OL  
I
I
3.0  
4.5  
0.36  
0.36  
0.44  
0.44  
0.52  
0.52  
I
Maximum Input Leakage  
Current  
V
= 5.5 V or  
0 to 5.5  
± 0.1  
± 1.0  
± 1.0  
µA  
µA  
IN  
IN  
GND  
= V or GND  
CC  
I
Maximum Quiescent Supply  
Current  
V
IN  
5.5  
2.0  
20  
40  
CC  
I
Quiescent Supply Current  
Output Leakage Current  
Input: V = 3.4V  
IN  
5.5  
0.0  
1.35  
0.5  
1.50  
5.0  
1.65  
10  
mA  
CCT  
I
V
OUT  
= 5.5V  
µA  
OPD  
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2
MC74VHCT126A  
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)  
r
f
T
A
= 25°C  
T
A
= 85°C  
T 125°C  
A
Symbol  
Parameter  
Test Conditions  
= 3.3 ± 0.3V C = 15pF  
Unit  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
t
t
,
Maximum Propagation  
Delay, A to Y  
V
V
V
5.6  
8.1  
8.0  
11.5  
1.0  
1.0  
9.5  
13.0  
12.0  
16.0  
ns  
PLH  
CC  
CC  
CC  
L
C
= 50pF  
L
PHL  
= 5.0 ± 0.5V C = 15pF  
3.8  
5.3  
5.5  
7.5  
1.0  
1.0  
6.5  
8.5  
8.5  
10.5  
L
L
C
= 50pF  
t
t
,
Maximum Output Enable  
TIme,OE to Y  
= 3.3 ± 0.3V C = 15pF  
5.4  
7.9  
8.0  
11.5  
1.0  
1.0  
9.5  
13.0  
11.5  
15.0  
ns  
ns  
ns  
PZL  
L
R
= 1kΩ  
C = 50pF  
L
PZH  
L
V
R
= 5.0 ± 0.5V C = 15pF  
3.6  
5.1  
5.1  
7.1  
1.0  
1.0  
6.0  
8.0  
7.5  
9.5  
CC  
L
= 1kΩ  
C = 50pF  
L
L
t
t
,
Maximum Output Disable  
Time,OE to Y  
V
R
= 3.3 ± 0.3V C = 50pF  
9.5  
13.2  
8.8  
1.5  
1.0  
10  
1.0  
15.0  
10.0  
1.5  
18.0  
12.0  
2.0  
PLZ  
CC  
L
= 1kΩ  
PHZ  
L
V
R
= 5.0 ± 0.5V C = 50pF  
L
= 1kΩ  
6.1  
1.0  
CC  
L
t
t
,
Output–to–Output Skew  
V
= 3.3 ± 0.3V C = 50pF  
OSLH  
CC L  
(Note 1.)  
OSHL  
V
= 5.0 ± 0.5V C = 50pF  
1.0  
1.5  
CC  
(Note 1.)  
L
C
Maximum Input  
Capacitance  
4
6
10  
10  
pF  
pF  
in  
C
Maximum Three–State  
Output Capacitance (Output  
in High Impedance State)  
out  
Typical @ 25°C, V  
= 5.0V  
CC  
C
Power Dissipation Capacitance (Note 2.)  
= |t  
pF  
15  
PD  
1. Parameter guaranteed by design. t  
– t  
|, t  
= |t  
– t  
|.  
OSLH  
PLHm PLHn OSHL  
PHLm PHLn  
2. C  
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.  
PD  
Average operating current can be obtained by the equation: I  
= C  
V
V
f
+ I  
/4 (per buffer). C is used to determine the  
PD  
CC(OPR)  
in CC  
PD  
CC  
CC in CC  
2
no–load dynamic power consumption; P = C  
V
CC  
f
+ I  
.
D
PD  
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V  
= 5.0V)  
r
f
L
CC  
T
A
= 25°C  
Symbol  
Characteristic  
Unit  
V
Typ  
Max  
0.8  
V
OLP  
Quiet Output Maximum Dynamic V  
0.3  
OL  
V
Quiet Output Minimum Dynamic V  
– 0.3  
– 0.8  
3.5  
V
OLV  
OL  
V
Minimum High Level Dynamic Input Voltage  
Maximum Low Level Dynamic Input Voltage  
V
IHD  
V
1.5  
V
ILD  
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3
MC74VHCT126A  
SWITCHING WAVEFORMS  
3.0V  
GND  
OE  
1.5V  
3.0V  
A
Y
1.5V  
t
t
PZL PLZ  
GND  
HIGH  
IMPEDANCE  
t
PHL  
t
PLH  
1.5V  
Y
V
OH  
V
+ 0.3V  
OL  
1.5V  
t
t
PZH PHZ  
V
OL  
V
OH  
– 0.3V  
1.5V  
Y
HIGH  
IMPEDANCE  
Figure 1.  
Figure 2.  
TEST POINT  
TEST POINT  
OUTPUT  
CONNECT TO V WHEN  
CC  
AND t  
1 kΩ  
TESTING t  
OUTPUT  
PLZ  
PZL.  
DEVICE  
UNDER  
TEST  
CONNECT TO GND WHEN  
TESTING t AND t  
DEVICE  
UNDER  
TEST  
PHZ PZH.  
C *  
L
C *  
L
*Includes all probe and jig capacitance  
*Includes all probe and jig capacitance  
Figure 3. Test Circuit  
Figure 4. Test Circuit  
MARKING DIAGRAMS  
(Top View)  
14 13 12 11 10  
9
6
8
7
14  
13  
12  
11  
10  
9
6
8
VHCT  
126A  
VHCT126A  
AWLYWW*  
ALYW*  
1
2
3
4
5
7
1
2
3
4
5
14–LEAD SOIC  
D SUFFIX  
14–LEAD TSSOP  
DT SUFFIX  
CASE 751A  
CASE 948G  
14  
13  
12  
11  
10  
9
6
8
VHCT126A  
AWLYWW*  
1
2
3
4
5
7
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
*See Applications Note #AND8004/D for date code and traceability information.  
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4
MC74VHCT126A  
PACKAGE DIMENSIONS  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751A–03  
ISSUE F  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
–A–  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
14  
1
8
7
P 7 PL  
–B–  
M
M
0.25 (0.010)  
B
MILLIMETERS  
INCHES  
MIN MAX  
G
F
R X 45°  
DIM MIN  
MAX  
8.75  
4.00  
1.75  
0.49  
1.25  
C
A
B
C
D
F
G
J
K
M
P
8.55  
3.80  
1.35  
0.35  
0.40  
0.337 0.344  
0.150 0.157  
0.054 0.068  
0.014 0.019  
0.016 0.049  
0.050 BSC  
J
M
SEATING  
PLANE  
K
D 14 PL  
1.27 BSC  
0.19  
0.10  
0°  
0.25  
0.25  
7°  
0.008 0.009  
0.004 0.009  
M
S
S
0.25 (0.010)  
T
B
A
0°  
7°  
5.80  
0.25  
6.20  
0.50  
0.228 0.244  
0.010 0.019  
R
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5
MC74VHCT126A  
PACKAGE DIMENSIONS  
DT SUFFIX  
PLASTIC TSSOP PACKAGE  
CASE 948G–01  
ISSUE O  
NOTES:  
14X K REF  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
M
S
S
0.10 (0.004)  
T U  
V
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,  
PROTRUSIONS OR GATE BURRS. MOLD FLASH  
OR GATE BURRS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSION. INTERLEAD FLASH OR  
PROTRUSION SHALL NOT EXCEED  
0.25 (0.010) PER SIDE.  
S
0.15 (0.006) T U  
N
0.25 (0.010)  
14  
8
2X L/2  
M
B
–U–  
5. DIMENSION K DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN  
EXCESS OF THE K DIMENSION AT MAXIMUM  
MATERIAL CONDITION.  
L
N
PIN 1  
IDENT.  
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
DETAIL E  
7. DIMENSION A AND B ARE TO BE DETERMINED  
AT DATUM PLANE W.  
S
K
0.15 (0.006) T U  
A
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
K1  
–V–  
A
B
C
4.90  
4.30  
–––  
5.10 0.193 0.200  
4.50 0.169 0.177  
J J1  
1.20  
––– 0.047  
D
F
0.05  
0.50  
0.15 0.002 0.006  
0.75 0.020 0.030  
SECTION N–N  
G
H
J
J1  
K
K1  
L
0.65 BSC  
0.026 BSC  
0.60 0.020 0.024  
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
0.50  
0.09  
0.09  
0.19  
0.19  
–W–  
C
6.40 BSC  
0.252 BSC  
0.10 (0.004)  
M
0
8
0
8
SEATING  
PLANE  
–T–  
H
G
DETAIL E  
D
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6
MC74VHCT126A  
PACKAGE DIMENSIONS  
M SUFFIX  
PLASTIC SOIC EIAJ PACKAGE  
CASE 965–01  
ISSUE O  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
L
E
14  
8
Q
1
H
E
4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
L
7
1
DETAIL P  
Z
D
VIEW P  
MILLIMETERS  
INCHES  
A
e
DIM MIN  
MAX  
2.05  
MIN  
–––  
MAX  
0.081  
0.008  
0.020  
0.011  
0.413  
0.215  
c
A
1
b
c
D
E
e
–––  
0.05  
0.35  
0.18  
9.90  
5.10  
A
0.20 0.002  
0.50 0.014  
0.27 0.007  
10.50 0.390  
5.45 0.201  
A
b
1
M
1.27 BSC  
0.050 BSC  
0.13 (0.005)  
0.10 (0.004)  
H
7.40  
0.50  
1.10  
0
8.20 0.291  
0.85 0.020  
1.50 0.043  
10  
0.90 0.028  
1.42 –––  
0.323  
0.033  
0.059  
10  
0.035  
0.056  
E
0.50  
L
E
M
0
Q
Z
0.70  
–––  
1
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7
MC74VHCT126A  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes  
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular  
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,  
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be  
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.  
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