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MC74VHCT132ADR2G [ONSEMI]

Quad 2−Input NAND Schmitt Trigger; 四2输入与非施密特触发器
MC74VHCT132ADR2G
型号： MC74VHCT132ADR2G
厂家： ONSEMI    ONSEMI
描述：

Quad 2−Input NAND Schmitt Trigger
四2输入与非施密特触发器

栅极 触发器 逻辑集成电路 光电二极管
文件： 总6页 (文件大小：101K)
中文：  中文翻译
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MC74VHCT132A  
Quad 2−Input NAND Schmitt  
Trigger  
The MC74VHCT132A is an advanced high speed CMOS Schmitt  
NAND trigger fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
Pin configuration and function are the same as the MC74VHC00,  
but the inputs have hysteresis and, with its Schmitt trigger function,  
the VHCT132A can be used as a line receiver which will receive slow  
input signals.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
The VHCT132A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
1
SOIC−14  
D SUFFIX  
CASE 751A  
VHCT132AG  
AWLYWW  
1
The output structures also provide protection when V = 0 V. These  
CC  
14  
input and output structures help prevent device destruction caused by  
supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
VHCT  
132A  
ALYWG  
G
TSSOP−14  
DT SUFFIX  
CASE 948G  
1
1
14  
Features  
SOEIAJ−14  
M SUFFIX  
CASE 965  
VHCT132  
ALYWG  
• High Speed: t = 4.9 ns (Typ) at V = 5.0 V  
PD  
CC  
1
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
1
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
• Power Down Protection Provided on Inputs  
• Balanced Propagation Delays  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
• Designed for 2.0 V to 5.5 V Operating Range  
• Low Noise: V  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
• ESD Performance:  
WW, W = Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
G or G  
= 0.8 V (Max)  
OLP  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Human Body Model > 2000 V;  
Machine Model > 200 V  
• Chip Complexity: 72 FETs or 18 Equivalent Gates  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 4  
MC74VHCT132A/D  
MC74VHCT132A  
1
2
4
5
9
A1  
B1  
A2  
B2  
A3  
3
6
8
Y1  
Y3  
Y4  
10  
B3  
12  
A4  
11  
Y2  
13  
B4  
Figure 1. Logic Diagram  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
FUNCTION TABLE  
14  
Inputs  
Output  
A
B
Y
L
L
H
H
L
H
L
H
H
H
L
H
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
Figure 2. Pinout: 14−Lead Packages (Top View)  
ORDERING INFORMATION  
†
Device  
MC74VHCT132ADR2  
Package  
Shipping  
SOIC−14  
2500 Tape & Reel  
2500 Tape & Reel  
MC74VHCT132ADR2G  
SOIC−14  
(Pb−Free)  
MC74VHCT132ADTR2  
MC74VHCT132ADTRG  
MC74VHCT132AM  
TSSOP−14*  
TSSOP−14*  
SOEIAJ−14  
2500 Tape & Reel  
2500 Tape & Reel  
50 Units / Rail  
MC74VHCT132AMG  
SOEIAJ−14  
(Pb−Free)  
50 Units / Rail  
MC74VHCT132AMEL  
MC74VHCT132AMELG  
SOEIAJ−14  
2000 Tape & Reel  
2000 Tape & Reel  
SOEIAJ−14  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*This package is inherently Pb−Free.  
http://onsemi.com  
2
MC74VHCT132A  
MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this high−impedance cir-  
V
DC Supply Voltage  
DC Input Voltage  
DC Output Voltage  
Input Diode Current  
– 0.5 to + 7.0  
– 0.5 to + 7.0  
CC  
V
V
in  
V
– 0.5 to V + 0.5  
V
out  
IK  
CC  
I
− 20  
20  
mA  
mA  
mA  
mA  
mW  
cuit. For proper operation, V and  
I
Output Diode Current  
in  
OK  
V
out  
should be constrained to the  
I
I
DC Output Current, per Pin  
25  
out  
range GND v (V or V ) v V  
.
CC  
in  
out  
DC Supply Current, V and GND Pins  
50  
Unused inputs must always be  
tied to an appropriate logic voltage  
CC  
CC  
P
Power Dissipation in Still Air,  
SOIC Packages†  
TSSOP Package†  
500  
450  
D
level (e.g., either GND or V ).  
CC  
Unused outputs must be left open.  
T
stg  
Storage Temperature  
– 65 to + 150  
_C  
Maximum ratings are those values beyond which device damage can occur. Maximum ratings  
applied to the device are individual stress limit values (not normal operating conditions) and are  
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,  
damage may occur and reliability may be affected.  
†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C  
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
4.5  
0
Max  
5.5  
Unit  
V
V
DC Supply Voltage  
DC Input Voltage  
DC Output Voltage  
CC  
V
in  
5.5  
V
V
out  
0
V
V
CC  
T
A
Operating Temperature, All Package Types  
− 40  
+ 85  
_C  
DC ELECTRICAL CHARACTERISTICS  
T
A
= 25°C  
T
A
≤ 85°C  
T ≤ 125°C  
A
V
CC  
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
V
Symbol  
Parameter  
Test Conditions  
Unit  
V
Positive Threshold Voltage  
3.0  
4.5  
5.5  
1.7  
2.0  
2.0  
1.6  
2.0  
2.0  
1.6  
2.0  
2.0  
V
T+  
V
Negative Threshold Voltage  
Hysteresis Voltage  
3.0  
4.5  
6.0  
0.35  
0.5  
0.6  
0.35  
0.5  
0.6  
0.35  
0.5  
0.6  
V
V
V
T−  
V
3.0  
4.5  
5.5  
0.30  
0.40  
0.50  
1.20  
1.40  
1.60  
0.30  
0.40  
0.50  
1.20  
1.40  
1.60  
0.30  
0.40  
0.50  
1.20  
1.40  
1.60  
H
V
Minimum High−Level Output  
Voltage  
V
= V or V  
= − 50mA  
2.0  
3.0  
4.5  
1.9  
2.9  
4.4  
2.0  
3.0  
4.5  
1.9  
2.9  
4.4  
1.9  
2.9  
4.4  
OH  
IN  
IH  
IL  
IL  
I
OH  
I
= −50mA  
OH  
I
I
= − 4mA  
= − 8mA  
4.5  
5.5  
2.58  
3.94  
2.48  
3.80  
2.34  
3.66  
OH  
OH  
V
Maximum Low−Level Output  
Voltage  
V
= V or V  
2.0  
3.0  
4.5  
0.0  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
OL  
IN  
IH  
I
= 50mA  
OL  
I
I
= 4mA  
= 8mA  
4.5  
5.5  
0.36  
0.36  
0.44  
0.44  
0.52  
0.52  
OL  
OL  
I
Maximum Input Leakage  
Current  
V
GND  
= 5.5V or  
IN  
0 to  
5.5  
0.1  
1.0  
1.0  
mA  
mA  
IN  
I
Maximum Quiescent Supply  
Current  
V
GND  
= V or  
5.5  
2.0  
20  
40  
CC  
IN  
CC  
I
Quiescent Supply Current  
Output Leakage Current  
Input: V = 3.4V  
5.5  
0.0  
1.35  
0.5  
1.50  
5.0  
1.65  
10  
mA  
CCT  
IN  
I
V
= 5.5V  
mA  
OPD  
OUT  
http://onsemi.com  
3
MC74VHCT132A  
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)  
r
f
T
A
= − 40 to  
85°C  
T
A
= 25°C  
Typ  
T ≤ 125°C  
A
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Test Conditions  
Unit  
t
t
,
Maximum Propagation Delay,  
A or B to Y  
V
V
= 3.3 0.3 V C = 15pF  
7.6  
10.1 15.4  
11.9  
1.0  
1.0  
14.0  
17.5  
16.5  
20.0  
ns  
PLH  
CC  
CC  
L
C = 50pF  
L
PHL  
= 5.0 0.5 V C = 15pF  
4.9  
6.4  
7.7  
9.7  
1.0  
1.0  
9.0  
11.0  
11.0  
13.0  
L
C = 50pF  
L
C
Maximum Input Capacitance  
4
10  
10  
10  
pF  
pF  
in  
Typical @ 25°C, V = 5.0 V  
CC  
16  
C
PD  
Power Dissipation Capacitance (Note 1)  
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.  
PD  
Average operating current can be obtained by the equation: I  
no−load dynamic power consumption; P = C ꢀ V  
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the  
CC(OPR  
PD CC in CC PD  
2
ꢀ f + I ꢀ V  
.
CC  
D
PD  
CC  
in  
CC  
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0 V)  
r
f
L
CC  
T
A
= 25°C  
Typ  
Max  
0.8  
Symbol  
Characteristic  
Unit  
V
V
V
Quiet Output Maximum Dynamic V  
0.3  
OLP  
OL  
Quiet Output Minimum Dynamic V  
− 0.3  
− 0.8  
3.5  
V
OLV  
OL  
V
Minimum High Level Dynamic Input Voltage  
Maximum Low Level Dynamic Input Voltage  
V
IHD  
V
1.5  
V
ILD  
TEST POINT  
OUTPUT  
3.0V  
1.5V  
A
Y
GND  
DEVICE  
UNDER  
TEST  
t
t
PHL  
PLH  
C *  
L
V
V
OH  
OL  
1.5V  
*Includes all probe and jig capacitance  
Figure 3. Switching Waveforms  
Figure 4. Test Circuit  
(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times  
(b) A Schmitt−Trigger Offers Maximum Noise Immunity  
V
V
CC  
CC  
V
V
H
H
V
V
T+  
T+  
V
in  
V
in  
V
V
T−  
T−  
GND  
GND  
V
V
OH  
OH  
V
out  
V
out  
V
V
OL  
OL  
Figure 5. Typical Schmitt−Trigger Applications  
http://onsemi.com  
4
 
MC74VHCT132A  
PACKAGE DIMENSIONS  
SOIC−14  
D SUFFIX  
CASE 751A−03  
ISSUE G  
NOTES:  
−A−  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
14  
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
−B−  
P 7 PL  
5. DIMENSION D DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.127  
(0.005) TOTAL IN EXCESS OF THE D  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
M
M
B
0.25 (0.010)  
7
1
G
F
R X 45  
_
C
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
A
B
C
D
F
G
J
K
M
P
R
8.55  
3.80  
1.35  
0.35  
0.40  
8.75 0.337 0.344  
4.00 0.150 0.157  
1.75 0.054 0.068  
0.49 0.014 0.019  
1.25 0.016 0.049  
0.050 BSC  
0.25 0.008 0.009  
0.25 0.004 0.009  
−T−  
SEATING  
PLANE  
J
M
K
D 14 PL  
M
S
S
0.25 (0.010)  
T
B
A
1.27 BSC  
0.19  
0.10  
0
7
0
7
_
_
_
_
5.80  
0.25  
6.20 0.228 0.244  
0.50 0.010 0.019  
TSSOP−14  
DT SUFFIX  
CASE 948G−01  
ISSUE A  
NOTES:  
14X K REF  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH, PROTRUSIONS OR GATE BURRS.  
MOLD FLASH OR GATE BURRS SHALL NOT  
EXCEED 0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL  
NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
M
S
S
V
0.10 (0.004)  
T
U
S
0.15 (0.006) T  
U
N
0.25 (0.010)  
14  
8
2X L/2  
M
B
L
N
−U−  
PIN 1  
IDENT.  
F
7
1
DETAIL E  
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE −W−.  
S
K
0.15 (0.006) T  
U
A
K1  
−V−  
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
A
B
C
D
F
4.90  
4.30  
−−−  
0.05  
0.50  
5.10 0.193 0.200  
4.50 0.169 0.177  
J J1  
1.20  
−−− 0.047  
0.15 0.002 0.006  
0.75 0.020 0.030  
SECTION N−N  
G
H
J
J1  
K
0.65 BSC  
0.026 BSC  
0.60 0.020 0.024  
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
0.50  
0.09  
0.09  
0.19  
−W−  
C
0.10 (0.004)  
K1 0.19  
L
M
6.40 BSC  
0.252 BSC  
SEATING  
PLANE  
−T−  
H
G
DETAIL E  
D
0
8
0
8
_
_
_
_
http://onsemi.com  
5
MC74VHCT132A  
PACKAGE DIMENSIONS  
SOEIAJ−14  
M SUFFIX  
CASE 965−01  
ISSUE A  
NOTES:  
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.  
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
L
14  
8
E
Q
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
L
7
1
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
DETAIL P  
Z
D
VIEW P  
A
e
c
MILLIMETERS  
INCHES  
MIN MAX  
−−− 0.081  
DIM MIN  
MAX  
2.05  
0.20  
0.50  
0.20  
10.50  
5.45  
A
−−−  
0.05  
0.35  
0.10  
9.90  
5.10  
A
1
b
A
1
b
c
0.002  
0.008  
0.020  
0.008  
0.413  
0.215  
0.014  
0.004  
0.390  
0.201  
M
0.13 (0.005)  
0.10 (0.004)  
D
E
e
1.27 BSC  
0.050 BSC  
H
7.40  
0.50  
1.10  
8.20  
0.85  
1.50  
0.291  
0.020  
0.043  
0.323  
0.033  
0.059  
E
0.50  
L
E
M
0
0.70  
−−−  
10  
10  
0.035  
−−− 0.056  
0
0.028  
_
_
_
_
Q
1
0.90  
1.42  
Z
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
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For additional information, please contact your  
local Sales Representative.  
MC74VHCT132A/D  

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 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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