MC74VHCT14ADR2 [ONSEMI]
Hex Schmitt Inverter; 六角施密特逆变器
| 型号： | MC74VHCT14ADR2 |
| 厂家： | 
ONSEMI |
| 描述： | Hex Schmitt Inverter |
| 文件： | 总6页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT14A
Hex Schmitt Inverter
The MC74VHCT14A is an advanced high speed CMOS Schmitt
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the
MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt
trigger function, the VHCT14A can be used as a line receiver which
will receive slow input signals.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
VHCT14AG
AWLYWW
The VHCT14A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
1
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
14
VHCT
14A
TSSOP−14
DT SUFFIX
CASE 948G
ALYWG
1
G
1
14
Features
SOEIAJ−14
M SUFFIX
CASE 965
74VHCT14
ALYWG
• High Speed: t = 5.5 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
1
CC
A
1
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
A
= Assembly Location
WL, L = Wafer Lot
Y, YY = Year
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
WW, W = Work Week
G or G = Pb−Free Package
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: 60 FETs or 15 Equivalent Gates
• Pb−Free Packages are Available*
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 4
MC74VHCT14A/D
MC74VHCT14A
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
Y3
V
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
CC
14
Y = A
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
11
13
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
Pinout: 14−Lead Packages (Top View)
Figure 1. Logic Diagram
MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
−0.5 to +7.0
−0.5 to +7.0
V
IN
V
Output in HIGH or LOW State (Note 1)
V
V
−0.5 to V +0.5 V
V
OUT
OUT
CC
V
CC
= 0 V
−0.5 to 7.0
−20
V
DC Input Diode Current
I
mA
mA
mA
mA
mA
°C
IK
DC Output Diode Current
I
$20
OK
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
I
O
$25
I
$50
CC
I
$50
GND
T
STG
−65 to +150
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
T
260
°C
L
T
+150
°C
J
SOIC
TSSOP
q
125
170
°C/W
JA
Power Dissipation in Still Air
ESD Withstand Voltage
SOIC
TSSOP
P
500
450
mW
V
D
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
V
ESD
>2000
>200
2000
Latchup Performance
Above V and Below GND at 85°C (Note 5)
I
$300
mA
CC
Latchup
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHCT14A
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Min
4.5
0
Max
5.5
Unit
V
V
CC
Input Voltage
V
I
5.5
V
Output Voltage (Note 6)
V
0
V
V
O
O
CC
V
CC
= 0 V
V
0
5.5
V
Operating Free−Air Temperature
T
A
−55
+125
°C
6. I absolute maximum rating must be observed.
O
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
V
CC
Symbol
V
Min Typ Max Min Max Min Max
Parameter
Test Conditions
Unit
Positive Threshold Voltage
V
T+
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
Negative Threshold Voltage
Hysteresis Voltage
V
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
V
V
V
T−
V
4.5
5.5
0.40
0.40
1.40 0.40 1.40 0.40 1.40
1.50 0.40 1.50 0.40 1.50
H
Minimum High−Level Output Voltage
V
= V or V
= −50 mA
V
OH
4.5
4.4
4.5
0.0
4.4
4.4
IN
IH
IL
I
= −50 mA
I
OH
OH
I
= −8.0 mA
5.5
4.5
3.94
3.80
3.66
OH
Maximum Low−Level Output Voltage
V
IN
= V or V
V
OL
0.1
0.1
0.1
V
IH
IL
I
OL
= 50 mA
I
= 8.0 mA
5.5
0 to 5.5
5.5
0.36
0.1
0.44
1.0
0.52
1.0
40
OL
Maximum Input Leakage Current
Maximum Quiescent Supply Current
Quiescent Supply Current
V
= 5.5 V or GND
I
mA
mA
IN
IN
IN
V
= V or GND
I
2.0
20
CC
CC
Input: V = 3.4 V
I
5.5
1.35
0.5
1.50
5.0
1.65 mA
IN
CCT
Output Leakage Current
V
OUT
= 5.5 V
I
0.0
10
mA
OFF
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Min Typ Max Min Max Min Max
Parameter
Test Conditions
= 5.0 0.5 V
Symbol
Unit
Maximum Propagation Delay, A to Y
V
ns
CC
C = 15 pF
C = 50 pF
L
t
t
,
5.5
7.0
7.6
9.6
1.0
1.0
9.0
11.0
1.0
1.0 13.5
11.5
L
PLH
PHL
Maximum Input Capacitance
C
2.0
10
10
10
pF
pF
IN
Power Dissipation Capacitance
(Note 7)
Typical @ 25°C, V = 5.0 V
CC
11
C
PD
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /6 (per buffer). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
0.8
Max
1.0
Characteristic
Quiet Output Maximum Dynamic V
Symbol
Unit
V
V
OL
OLP
OLV
Quiet Output Minimum Dynamic V
V
−0.8
−1.0
2.0
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
V
ILD
0.8
V
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3
MC74VHCT14A
TEST POINT
OUTPUT
3.0V
GND
1.5V
A
Y
DEVICE
UNDER
TEST
t
t
PHL
PLH
C *
L
V
V
OH
1.5V
OL
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times
(b) A Schmitt−Trigger Offers Maximum Noise Immunity
V
CC
V
CC
V
H
V
H
V
V
V
V
T+
T+
V
in
V
in
T−
T−
GND
GND
V
V
OH
OL
OH
OL
V
out
V
out
V
V
Figure 4. Typical Schmitt−Trigger Applications
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT14ADR2
MC74VHCT14ADR2G
SOIC−14
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHCT14ADTR2
MC74VHCT14ADTR2G
MC74VHCT14AM
TSSOP−14*
TSSOP−14*
SOEIAJ−14
50 Units / Rail
MC74VHCT14AMG
SOEIAJ−14
(Pb−Free)
MC74VHCT14AMEL
MC74VHCT14AMELG
SOEIAJ−14*
2000 / Tape & Reel
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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4
MC74VHCT14A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
−A−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
M
B
0.25 (0.010)
7
1
G
F
R X 45
_
C
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
1.27 BSC
0.19
0.10
0
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
CASE 948G−01
ISSUE A
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
0
8
0
8
D
_
_
_
_
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5
MC74VHCT14A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
7
1
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
A
e
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
−−−
0.05
0.35
0.10
9.90
5.10
2.05
b
A
1
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
M
0.13 (0.005)
0.10 (0.004)
D
E
e
10.50 0.390
5.45 0.201
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
0.50
L
E
M
0
0.70
−−−
10
0.90 0.028
10
0.035
0.056
0
_
_
_
_
Q
1
Z
1.42
−−−
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
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Order Literature: http://www.onsemi.com/litorder
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Email: orderlit@onsemi.com
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Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
MC74VHC14/D
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