MC74VHCXXXM [ONSEMI]
Octal Bus Transceiver; 八路总线收发器
| 型号： | MC74VHCXXXM |
| 厂家： | 
ONSEMI |
| 描述： | Octal Bus Transceiver |
| 文件： | 总8页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
MC74VHC245
Octal Bus Transceiver
The MC74VHC245 is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
It is intended for two−way asynchronous communication between
data buses. The direction of data transmission is determined by the
level of the DIR input. The output enable pin (OE) can be used to
disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static
discharge.
DW SUFFIX
20−LEAD SOIC WIDE PACKAGE
CASE 751D−05
• High Speed: t = 4.0ns (Typ) at V = 5V
PD
CC
DT SUFFIX
20−LEAD TSSOP PACKAGE
CASE 948E−02
• Low Power Dissipation: I = 4μA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
= 1.2V (Max)
OLP
M SUFFIX
20−LEAD SOIC EIAJ PACKAGE
CASE 967−01
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 308 FETs or 77 Equivalent Gates
w These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC WIDE
TSSOP
SOIC EIAJ
APPLICATION NOTES
• Do not force a signal on an I/O pin when it is an active output,
damage may occur.
• All floating (high impedance) input or I/O pins must be fixed by
means of pull up or pull down resistors or bus terminator ICs.
• A parasitic diode is formed between the bus and V terminals.
CC
Therefore, the VHC245 cannot be used to interface 5V to 3V systems
directly.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 5
MC74VHC245/D
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
20
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
19 OE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
A
DATA
PORT
B
DATA
PORT
1
DIR
OE
19
GND 10
Figure 1. LOGIC
DIAGRAM
Figure 2. PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
OE
L
DIR
L
Operation
Data Transmitted from Bus B to Bus A
Data Transmitted from Bus A to Bus B
Buses Isolated (High−Impedance State)
L
H
H
X
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
± 20
± 25
± 75
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature
Input Rise and Fall Time
− 40
+ 85
_C
ns/V
A
t , t
r
V
CC
= 3.3V ±0.3V
=5.0V ±0.5V
0
0
100
20
f
V
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
1.50
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= − 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
I
OH
V
in
= V or V
IH
IL
I
I
= − 4mA
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
I
in
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
μA
in
(DIR, OE)
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3
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Maximum
Test Conditions
= V or V
Unit
I
V
in
5.5
± 0.25
± 2.5
μA
OZ
IL
IH
Three−State Leakage
V
= V or GND
out CC
Current
I
Maximum Quiescent
Supply Current
V
in
= V or GND
5.5
4.0
40.0
μA
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= − 40 to 85°C
Min
Typ
Max
Min
1.0
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation Delay,
A to B or B to A
V
V
V
= 3.3 ± 0.3V
= 5.0 ± 0.5V
= 3.3 ± 0.3V
C = 15pF
C = 50pF
L
5.8
8.3
8.4
11.9
10.0
13.5
ns
PLH
t
CC
CC
CC
L
1.0
PHL
C = 15pF
4.0
5.5
5.5
7.5
1.0
1.0
6.5
8.5
L
C = 50pF
L
,
Output Enable Time
OE to A or B
C = 15pF
L
8.5
11.0
13.2
16.7
1.0
1.0
15.5
19.0
ns
ns
PZL
t
R = 1 kΩ
C = 50pF
L
PZH
L
V
CC
= 5.0 ± 0.5V
C = 15pF
L
5.8
7.3
8.5
10.6
1.0
1.0
10.0
12.0
R = 1 kΩ
C = 50pF
L
L
,
Output Disable Time
OE to A or B
V
CC
= 3.3 ± 0.3V
C = 50pF
L
11.5
15.8
9.7
1.5
1.0
10
1.0
18.0
11.0
1.5
PLZ
t
R = 1 kΩ
PHZ
L
V
CC
= 5.0 ± 0.5V
C = 50pF
L
7.0
1.0
R = 1 kΩ
L
t
,
Output to Output Skew
V
CC
= 3.3 ± 0.3V
C = 50pF
L
ns
ns
pF
pF
OSLH
t
(Note 1)
OSHL
V
CC
= 5.0 ± 0.5V
C = 50pF
L
1.0
(Note 1)
C
Maximum Input Capacitance
DIR, OE
4
8
10
in
C
Maximum Three−State
I/O
I/O Capacitance
Typical @ 25°C, V = 5.0V
CC
21
C
Power Dissipation Capacitance (Note 2)
pF
PD
1. Parameter guaranteed by design. t = |t − t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I / 8 (per bit). C is used to determine the no−load
CC(OPR
CC
PD CC in CC PD
2
dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.9
1.2
−1.2
3.5
OLP
OL
Quiet Output Minimum Dynamic V
−0.9
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
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4
SWITCHING WAVEFORMS
V
CC
DIR
OE
50%
GND
V
CC
50% V
50% V
CC
CC
GND
V
CC
A or B
B or A
t
t
PLZ
PZL
50%
HIGH
GND
IMPEDANCE
50% V
CC
t
t
PHL
A or B
A or B
PLH
V
+0.3V
−0.3V
OL
t
t
PHZ
PZH
50% V
CC
V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 3.
Figure 4.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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5
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
18
17
16
15
B1
B2
B3
B4
14
13
12
11
B5
B6
B7
B8
1
DIR
OE
19
Figure 7. EXPANDED LOGIC DIAGRAM
DIR, OE
A, B
INPUT
I/O
Figure 9. BUS TERMINAL EQUIVALENT CIRCUIT
Figure 8. INPUT EQUIVALENT CIRCUIT
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6
OUTLINE DIMENSIONS
DW SUFFIX
SOIC
CASE 751D−05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
DT SUFFIX
TSSOP
CASE 948E−02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006)
T U
M
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
−−−
6.60 0.252
4.50 0.169
N
C
1.20
−−−
D
0.05
0.50
0.15 0.002
0.75 0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
−W−
J1
K
C
K1
L
6.40 BSC
0.252 BSC
0
G
D
M
0
8
8
_
_
_
_
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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7
M SUFFIX
SOIC EIAJ
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
A
−−−
0.05
0.35
0.18
12.35
5.10
−−−
0.002
0.014
0.007
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0
10
_
0.035
0.032
_
_
_
0.70
−−−
0.90
0.81
0.028
−−−
1
Z
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC245/D
相关型号：
MC74VHCXXXXDT
Quad Analog Switch/Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS
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