MJE13005G [ONSEMI]
4 AMPERE NPN SILICON POWER TRANSISTOR 400 VOLTS − 75 WATTS; 4安培NPN硅功率晶体管400伏 - 75瓦
| 型号： | MJE13005G |
| 厂家： | 
ONSEMI |
| 描述： | 4 AMPERE NPN SILICON POWER TRANSISTOR 400 VOLTS − 75 WATTS |
| 文件： | 总7页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MJE13005
Preferred Device
SWITCHMODEt Series
NPN Silicon Power
Transistors
These devices are designed for high−voltage, high−speed power
switching inductive circuits where fall time is critical. They are
particularly suited for 115 and 220 V SWITCHMODE applications
such as Switching Regulator’s, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
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4 AMPERE
NPN SILICON
POWER TRANSISTOR
400 VOLTS − 75 WATTS
Features
• V
400 V
CEO(sus)
• Reverse Bias SOA with Inductive Loads @ T = 100_C
C
• Inductive Switching Matrix 2 to 4 A, 25 and 100_C t @ 3A,
c
100_C is 180 ns (Typ)
• 700 V Blocking Capability
• SOA and Switching Applications Information
• Pb−Free Package is Available*
MAXIMUM RATINGS
TO−220AB
CASE 221A−09
Rating
Collector−Emitter Voltage
Collector−Emitter Voltage
Emitter−Base Voltage
Symbol
Value
400
700
9
Unit
Vdc
Vdc
Vdc
Adc
1
STYLE 1
2
V
CEO(sus)
3
V
CEV
V
EBO
MARKING DIAGRAM
Collector Current − Continuous
− Peak (Note 1)
I
4
8
C
I
I
I
CM
Base Current
− Continuous
− Peak (Note 1)
I
2
4
Adc
Adc
B
BM
Emitter Current
− Continuous
− Peak (Note 1)
I
6
12
E
EM
MJE13005G
AY WW
Total Device Dissipation @ T = 25_C
P
P
2
16
W
C
D
D
Derate above 25°C
W/_C
W
W/_C
_C
Total Device Dissipation @ T = 25_C
75
600
C
Derate above 25°C
Operating and Storage Junction
Temperature Range
T , T
−65 to
+150
J
stg
A
= Assembly
THERMAL CHARACTERISTICS
Location
Y
WW
G
Characteristics
Symbol
Max
62.5
1.67
275
Unit
_C/W
_C/W
_C
= Year
= Work Week
= Pb−Free Pack-
Thermal Resistance, Junction−to−Ambient
Thermal Resistance, Junction−to−Case
R
q
JA
JC
L
R
q
age
ORDERING INFORMATION
Maximum Lead Temperature for Soldering
Purposes 1/8″ from Case for 5 Seconds
T
Device
Package
Shipping
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
MJE13005
MJE13005G
TO−220
50 Units / Rail
50 Units / Rail
TO−220
(Pb−Free)
1. Pulse Test: Pulse Width = 5 ms, Duty Cycle ≤ 10%.
Preferred devices are recommended choices for future use
and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
February, 2006 − Rev. 7
MJE13005/D
MJE13005
ELECTRICAL CHARACTERISTICS (T = 25_C unless otherwise noted)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS (Note 2)
Collector−Emitter Sustaining Voltage
V
400
−
−
Vdc
CEO(sus)
(I = 10 mA, I = 0)
C
B
Collector Cutoff Current
I
mAdc
CEV
(V
(V
= Rated Value, V
= Rated Value, V
= 1.5 Vdc)
= 1.5 Vdc, T = 100_C)
CEV
CEV
BE(off)
BE(off)
−
−
−
−
1
5
C
Emitter Cutoff Current
(V = 9 Vdc, I = 0)
I
−
−
1
mAdc
EBO
EB
C
SECOND BREAKDOWN
Second Breakdown Collector Current with base forward biased
Clamped Inductive SOA with Base Reverse Biased
I
−
−
See Figure 11
See Figure 12
S/b
RBSOA
ON CHARACTERISTICS (Note 2)
DC Current Gain
h
FE
−
(I = 1 Adc, V = 5 Vdc)
C
CE
10
8
−
−
60
40
(I = 2 Adc, V = 5 Vdc)
C
CE
Collector−Emitter Saturation Voltage
(I = 1 Adc, I = 0.2 Adc)
V
V
Vdc
CE(sat)
C
B
−
−
−
−
−
−
−
−
0.5
0.6
1
(I = 2 Adc, I = 0.5 Adc)
C
B
(I = 4 Adc, I = 1 Adc)
C
B
(I = 2 Adc, I = 0.5 Adc, T = 100_C)
C
B
C
1
Base−Emitter Saturation Voltage
(I = 1 Adc, I = 0.2 Adc)
Vdc
BE(sat)
C
B
−
−
−
−
−
−
1.2
1.6
1.5
(I = 2 Adc, I = 0.5 Adc)
C
B
(I = 2 Adc, I = 0.5 Adc, T = 100_C)
C
B
C
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product
f
4
−
−
−
−
MHz
pF
T
(I = 500 mAdc, V = 10 Vdc, f = 1 MHz)
C
CE
Output Capacitance
C
65
ob
(V = 10 Vdc, I = 0, f = 0.1 MHz)
CB
E
SWITCHING CHARACTERISTICS
Resistive Load (Table 2)
Delay Time
t
t
−
−
−
−
0.025
0.3
0.1
0.7
4
ms
ms
ms
ms
d
(V = 125 Vdc, I = 2 A,
CC
C
Rise Time
Storage Time
Fall Time
t
r
I
= I = 0.4 A, t = 25 ms,
B2 p
B1
1.7
s
Duty Cycle v 1%)
t
0.4
0.9
f
Inductive Load, Clamped (Table 2, Figure 13)
Voltage Storage Time
t
−
−
−
0.9
4
0.9
−
ms
ms
ms
sv
(I = 2 A, V
= 300 Vdc,
clamp
C
Crossover Time
Fall Time
t
0.32
0.16
c
fi
I
= 0.4 A, V
= 5 Vdc, T = 100_C)
B1
BE(off)
C
t
2. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
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2
.4
−
0
0
.2
0
+ꢂ0.4
+ꢂ0.6
0.3
0.5 1 3
5
10
30
50
100
300
MJE13005
2
100
70
T = 25°C
J
T = 150°C
J
1.6
1.2
0.8
0.4
0
50
I = 1 A
C
25°C
2 A
3 A
4 A
30
20
−ꢂ55°C
10
V
V
= 2 V
= 5 V
CE
CE
7
5
0.1
0.2
0.4 0.6
1
2
4
0.03 0.05
0.1
0.2 0.3
0.5 0.7
1
2
3
0.04 0.06
I , COLLECTOR CURRENT (AMP)
C
I , BASE CURRENT (AMP)
B
Figure 1. DC Current Gain
Figure 2. Collector Saturation Region
0.55
0.45
0.35
0.25
0.15
0.05
1.3
1.1
0.9
0.7
0.5
0.3
I /I = 4
C B
V
V
@ I /I = 4
C B
@ V = 2 V
BE(sat)
BE(on)
CE
T = −ꢂ55°C
J
T = −ꢂ55°C
J
25°C
25°C
25°C
150°C
150°C
0.04 0.06 0.1
0.2
0.4 0.6
1
2
4
0.04 0.06 0.1
0.2
0.4 0.6
1
2
4
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (AMP)
C
Figure 3. Base−Emitter Voltage
Figure 4. Collector−Emitter Saturation Voltage
10 k
1 k
2 k
V
= 250 V
CE
C
ib
1 k
700
500
T = 150°C
J
100
10
1
300
200
125°C
100°C
75°C
100
70
50°C
25°C
50
30
20
C
ob
REVERSE
FORWARD
+ꢂ0.2
, BASE−EMITTER VOLTAGE (VOLTS)
0.1
−
V
V , REVERSE VOLTAGE (VOLTS)
R
BE
Figure 5. Collector Cutoff Region
Figure 6. Capacitance
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3
MJE13005
SWITCHING TIMES NOTE
I
CPK
V
clamp
In resistive switching circuits, rise, fall, and storage times
have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive
loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage
waveforms are not in phase. Therefore, separate
measurements must be made on each waveform to
determine the total switching time. For this reason, the
following new terms have been defined.
90% V
90% I
clamp
C
I
t
sv
t
rv
t
fi
t
ti
C
t
c
V
I
10% V
clamp
CE
10%
I
2% I
C
90% I
CPK
B
B1
t
sv
t
rv
= Voltage Storage Time, 90% I to 10% V
B1 clamp
= Voltage Rise Time, 10−90% V
clamp
TIME
t = Current Fall Time, 90−10% I
fi
C
Figure 7. Inductive Switching Measurements
Table 1. Typical Inductive Switching Performance
t = Current Tail, 10−2% I
ti
C
t = Crossover Time, 10% V
to 10% I
C
c
clamp
An enlarged portion of the inductive switching
waveforms is shown in Figure 7 to aid in the visual identity
of these terms.
For the designer, there is minimal switching loss during
storage time and the predominant switching power losses
occur during the crossover interval and can be obtained
using the standard equation from AN−222:
I
T
t
sv
t
rv
t
fi
t
ti
t
c
C
C
AMP
_C
ns
ns
ns
ns
ns
2
25
600
900
70
110
100
240
80
130
180
320
100
3
4
25
100
650
950
60
100
140
330
60
100
200
350
PSWT = 1/2 VCCIC(tc)f
25
100
550
850
70
110
160
350
100
160
220
390
In general, t + t ] t . However, at lower test currents
rv
fi
c
this relationship may not be valid.
NOTE: All Data recorded in the inductive Switching Circuit In Table 2.
As is common with most switching transistors, resistive
switching is specified at 25°C and has become a benchmark
for designers. However, for designers of high frequency
converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive
switching speeds (t and t ) which are guaranteed at 100_C.
c
sv
RESISTIVE SWITCHING PERFORMANCE
1
10
V
I /I = 5
= 125 V
V
I /I = 5
= 125 V
CC
CC
t
s
0.5
5
C B
C B
T = 25°C
J
T = 25°C
J
t
r
0.2
0.1
2
1
0.5
0.05
t @ V
d
= 5 V
BE(off)
0.3
0.2
t
f
0.02
0.01
0.1
0.04
0.04
0.1
0.2
0.4
1
2
4
0.1
0.2
0.5
1
2
4
I , COLLECTOR CURRENT (AMP)
C
I , COLLECTOR CURRENT (AMP)
C
Figure 8. Turn−On Time
Figure 9. Turn−Off Time
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4
MJE13005
Table 2. Test Conditions for Dynamic Performance
RESISTIVE
SWITCHING
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
+ꢂ5 V
V
CC
33
1N4933
+125 V
R
MJE210
L
MR826*
0.001 mF
1N4933
33
C
5 V
TUT
V
clamp
I
C
P
2N222
2
W
R
SCOPE
R
B
B
1 k
DUTY CYCLE ≤ 10%
t , t ≤ 10 ns
68
*SELECTED FOR ≥ 1 kV
r
f
1 k
+ꢂ5 V
5.1 k
51
I
B
D1
V
CE
1 k
T.U.T.
1N493
−ꢂ4.0
V
2N2905
3
270
MJE200
0.02 mF
47
100
NOTE
1/2 W
PW and V Adjusted for Desired I
CC
C
−V
BE(off)
R
B
Adjusted for Desired I
B1
V
= 125 V
CC
Coil Data:
Ferroxcube Core #6656
Full Bobbin (~16 Turns) #16
GAP for 200 mH/20 A
= 200 mH
V
V
= 20 V
CC
R = 62 W
C
D1 = 1N5820 or Equiv.
= 300 Vdc
L
clamp
coil
R = 22 W
B
OUTPUT WAVEFORMS
+10 V
0
25 ms
t CLAMPED
f
I
C
t UNCLAMPED ≈ t
t ADJUSTED TO
1
OBTAIN I
f
2
I
C
C(pk)
Test Equipment
Scope−Tektronics
475 or Equivalent
L
(I
t
coil C )
pk
t ≈
1
t
1
t
f
−8 V
t , t < 10 ns
V
CC
V
CE
L
(I
coil C )
pk
r
f
V
or
CE
t ≈
2
Duty Cycle = 1.0%
and R adjusted
V
V
clamp
clamp
R
B
t
C
t
2
TIME
for desired I and I
B
C
1
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
P
(pk)
Z
= r(t) R
q
JC
q
JC(t)
0.05
0.02
0.07
0.05
R
= 1.67°C/W MAX
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
0.03
0.02
1
t
1
2
0.01
T
− T = P
C
Z
q
(pk) JC(t)
J(pk)
DUTY CYCLE, D = t /t
1 2
SINGLE PULSE
0.05
0.01
1 k
0.01
0.02
0.1
0.2
0.5
1
2
5
10
20
50
100
200
500
t, TIME (ms)
Figure 10. Typical Thermal Response [ZqJC(t)]
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5
MJE13005
SAFE OPERATING AREA INFORMATION
The Safe Operating Area Figures 11 and 12 are specified ratings for these devices under the test conditions shown.
10
5
4
3
T
≤ 100°C
= 2.0 A
C
I
B1
500 ms
2
1
5 ms
dc
0.5
2
1
0
V
= 9 V
1 ms
BE(off)
0.2
0.1
0.05
MJE13005
300
5 V
0.02
0.01
3 V
1.5 V
MJE13005
5
7
10
V
20 30
50 70 100
200 300 500
400
0
100
200
400
500
600
700
800
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
V
, COLLECTOR−EMITTER CLAMP VOLTAGE (VOLTS)
CE
CE
Figure 11. Forward Bias Safe Operating Area
Figure 12. Reverse Bias Switching Safe Operating Area
FORWARD BIAS
REVERSE BIAS
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be held to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current conditions during
reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 12 gives the complete RBSOA
characteristics.
breakdown. Safe operating area curves indicate I − V
C
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 11 is based on T = 25_C; T
is
C
J(pk)
variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated when T ≥ 25_C. Second breakdown limitations do
C
not derate the same as thermal limitations. Allowable
current at the voltages shown on Figure 11 may be found at
any case temperature by using the appropriate curve on
Figure 13.
T
may be calculated from the data in Figure 10. At
J(pk)
high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations
imposed by second breakdown.
1
SECOND BREAKDOWN
DERATING
0.8
0.6
THERMAL
DERATING
0.4
0.2
0
20
40
60
80
100
120
140
160
T , CASE TEMPERATURE (°C)
C
Figure 13. Forward Bias Power Derating
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6
MJE13005
PACKAGE DIMENSIONS
TO−220AB
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
−−− 0.080
2.04
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
SWITCHMODE is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MJE13005/D
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