MM74HC138M [ONSEMI]
3-8 线路解码器;
| 型号： | MM74HC138M |
| 厂家： | 
ONSEMI |
| 描述： | 3-8 线路解码器 PC 驱动 输入元件 光电二极管 逻辑集成电路 解码器 |
| 文件： | 总7页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
3-to-8 Line Decoder
MM74HC138
1
1
Description
TSSOP−16
CASE 948F
SOIC−16
CASE 751B
The MM74HC138 decoder utilizes advanced silicon−gate CMOS
technology and is well suited to memory address decoding or data
routing applications. The circuit features high noise immunity and low
power consumption usually associated with CMOS circuitry, yet has
speeds comparable to low power Schottky TTL logic. The
MM74HC138 has 3 binary select inputs (A, B, and C). If the device is
enabled, these inputs determine which one of the eight normally HIGH
outputs will go LOW. Two active LOW and one active HIGH enables
(G1, G2A and G2B) are provided to ease the cascading of decoders.
The decoder’s outputs can drive 10 low power Schottky TTL
equivalent loads, and are functionally and pin equivalent to the
74LS138. All inputs are protected from damage due to static discharge
MARKING DIAGRAMS
16
1
16
HC
138A
ALYW
HC138A
AWLYWW
1
HC138A = Specific Device Code
A
L/WL
Y/YY
= Assembly Location
= Wafer Lot
= Year, Last Number
by diodes to V and ground.
CC
W/WW = Work Week
Features
• Typical Propagation Delay: 18 ns
• Wide Power Supply Range: 2 V-6 V
• Low Quiescent Current: 80 mA Maximum (74HC Series)
• Low Input Current: 1 mA maximum
• Fanout of 10 LS-TTL Loads
• These are Pb−Free Devices
CONNECTION DIAGRAM
ORDERING INFORMATION
†
Device
Package
Shipping
SOIC−16
(Pb−Free)
MM74HC138M
48 Units/Tube
SOIC−16
(Pb−Free)
2500/Tape &
Reel
MM74HC138MX
Figure 1. Logic Diagram
MM74HC138MTCX TSSOP−16
(Pb−Free)
2500/Tape &
Reel
MM74HC138MTC TSSOP−16
(Pb−Free)
96 Units/Tube
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
November, 2022 − Rev. 1
MM74HC138/D
MM74HC138
TRUTH TABLE
Enable
Inputs
Outputs
Select
Y4
H
G1
X
G2 (Note 1)
C
X
X
L
B
A
X
X
L
Y1
H
H
H
L
Y2
H
Y3
H
Y5
H
Y6
H
Y7
H
Y0
H
H
L
X
H
X
L
X
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H = high level; L = low level X = don’t care
Note 1: G2 = G2A + G2B
ABSOLUTE MAXIMUM RATINGS (note 1)
Symbol
Parameter
Value
Unit
V
Supply Voltage
–0.5 to + 7.0
−0.5 to V + 0.5
V
CC
V
DC Input Voltage
V
in
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5
V
out
CC
I
I
20
25
mA
mA
mA
_C
mW
IK, OK
I
out
CC
I
DC V or GND Current per Pins
50
CC
T
stg
Storage Temperature. Range
–65 to +150
P
Power Dissipation
(Note 2)
S. O. Package Only
D
600
500
T
Lead Temperature
(Soldering 10 seconds)
260
_C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: −12 mW/_C from 65_C to 85_C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
V
DC Input Voltage or Output Voltage
Operating Temperature
Input Rise or Fall Times
0
V
V
in, out
CC
T
A
−40
+85
_C
ns
t , t
r
f
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
−
−
−
1000
500
400
www.onsemi.com
2
MM74HC138
DC ELECTRICAL CHARACTERISTICS (note 3)
T
A
= 25°C
T –40 to
A
85°C
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
Unit
V
IH
Minimum HIGH−Level Input
Voltage
2.0
4.5
6.0
−
1.5
3.15
4.2
1.5
3.15
4.2
V
V
Maximum LOW−Level Input
Voltage
2.0
4.5
6.0
−
0.5
1.35
1.8
0.5
1.35
1.8
V
V
IL
V
OH
Minimum HIGH−Level Output
V
IN
= V or V
IH IL
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
⎪I ⎪ ≤ 20 mA
OUT
V
⎪I
⎪I
= V or V
IL
V
V
IN
IH
⎪ ≤ 4.0 mA
OUT
⎪ ≤ 5.2 mA
OUT
4.5
6.0
4.2
5.7
3.98
5.48
3.84
5.34
V
OL
Maximum LOW−Level Output
V
IN
= V or V
IH IL
Voltage
2.0
4.5
6.0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
⎪I ⎪ ≤ 20 mA
OUT
V
⎪I
⎪I
= V or V
IL
V
IN
IH
⎪ ≤ 4.0 mA
OUT
⎪ ≤ 5.2 mA
OUT
4.5
6.0
0.2
0.2
0.26
0.26
0.33
0.33
I
Maximum Input Current
V
= V or GND
6.0
6.0
−
−
0.1
8.0
0.1
80
mA
mA
IN
IN
CC
I
Maximum Quiescent Supply
Current
V
IN
= V or GND
CC
= 0 mA
CC
I
OUT
3. For a power supply of 5 V 10% the worst case output voltages (V , and V ) occur for HC at 4.5 V. Thus the 4.5 V values should be used
OH
OL
when designing with this supply. Worst case V and V occur at V = 5.5 V and 4.5 V respectively. (The V value at 5.5 V is 3.85 V.) The
IH
IL
CC
IH
worst case leakage current (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
IN CC
OZ
AC ELECTRICAL CHARACTERISTICS (V = 5 V, T = 25°C, C = 15 pF, t = t = 6 ns)
CC
A
L
r
f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
18
Unit
ns
t
t
Maximum Propagation Delay, Binary Select to any Output
Maximum Propagation Delay, Binary Select to any Output
25
35
25
PLH
PHL
28
ns
t
Maximum Propagation Delay,
G1 to any Output
18
ns
PHL,
t
PLH
PHL
PLH
t
Maximum Propagation Delay, G2A or G2B to Output
Maximum Propagation Delay, G2A or G2B to Output
23
18
30
25
ns
ns
t
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, tr = tf = 6 ns unless otherwise specified)
L
T
A =
–40 to
85°C
T
A
= 25°C
V
CC
Typ
Guaranteed Limit
(V)
Symbol
Parameter
Conditions
Unit
t
Maximum Propagation Delay,
Binary Select to any Output
LOW−to−HIGH
2.0
4.5
6.0
75
15
13
150
30
26
189
38
32
ns
PLH
t
Maximum Propagation Delay,
Binary Select to any Output
HIGH−to−LOW
2.0
4.5
6.0
100
20
17
200
40
34
252
50
43
ns
ns
PHL
t
Maximum Propagation
Delay G1 to any Output
2.0
4.5
6.0
75
15
13
150
30
26
189
38
32
PHL,
t
PLH
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3
MM74HC138
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, tr = tf = 6 ns unless otherwise specified) (continued)
L
T
A =
–40 to
85°C
T
A
= 25°C
V
CC
Typ
Guaranteed Limit
(V)
Symbol
Parameter
Conditions
Unit
t
Maximum Propagation
Delay G2A or G2B to Output
2.0
4.5
6.0
82
28
22
175
35
30
221
44
37
ns
PHL
t
Maximum Propagation
Delay G2A or G2B to Output
2.0
4.5
6.0
75
15
13
150
30
26
189
38
32
ns
ns
PLH
t
,
Output Rise and Fall Time
2.0
4.5
6.0
30
8
7
75
15
13
95
19
16
TLH
t
THL
C
Maximum Input Capacitance
−
−
3
10
10
pF
pF
IN
C
Power Dissipation
Capacitance
(Note 4)
75
−
−
PD
2
4. CPD determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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