MM74HC595MTC [ONSEMI]
8 位移位寄存器，带输出锁存;
| 型号： | MM74HC595MTC |
| 厂家： | 
ONSEMI |
| 描述： | 8 位移位寄存器，带输出锁存 光电二极管 输出元件 逻辑集成电路 触发器 移位寄存器 |
| 文件： | 总12页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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8-Bit Shift Register
with Output Latches
SOIC−16
CASE 751B−05
MM74HC595
General Description
The MM74HC595 high−speed shift register utilizes advanced
silicon−gate CMOS technology. This device possesses the high noise
immunity and low power consumption of standard CMOS integrated
circuits, as well as the ability to drive 15 LS−TTL loads.
TSSOP 16
CASE 948AH−01
This device contains an eight−bit serial−in, parallel−out, shift
register that feeds an eight−bit D−type storage register. The storage
register has eight 3−state outputs. Separate clocks are provided
for both the shift register and the storage register. The shift register has
a direct−overriding clear, serial input, and serial output (standard) pins
for cascading. Both the shift register and storage register use
positive−edge triggered clocks. If both clocks are connected together,
the shift register state is one clock pulse ahead of the storage register.
The 74HC logic family is speed, function, and pin−out compatible
with the standard 74LS logic family. All inputs are protected
16
1
TSSOP−16
CASE 948F−01
MARKING DIAGRAMS
from damage due to static discharge by internal diode clamps to V
and ground.
CC
SOIC−16
Features
• Low Quiescent Current: 160 mA Maximum (74HC Series)
• Low Input Current: 1 mA Maximum
• 8−Bit Serial−In, Parallel−Out Shift Register with Storage
• Wide Operating Voltage Range: 2 V−6 V
• Cascadable
HC595A
AWLYWW
TSSOP−16
• Shift Register has Direct Clear
16
• Guaranteed Shift Frequency: DC to 30 MHz
• This Device is Pb−Free and is RoHS Compliant
HC
595A
ALYW
1
HC595A = Specific Device Code
A
WL, L
Y
= Assembly Location
= Wafer Lot Number
= Year
WW, YW = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 1983
1
Publication Order Number:
May, 2023 − Rev. 3
MM74HC595/D
MM74HC595
Block Diagram
Figure 1. Logic Diagram (Positive Logic)
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2
MM74HC595
Pin Configuration
Figure 2. Pin Configuration
PIN DEFINITIONS
Pin No.
Symbol
Description
1
2
Q
Q
Q
Q
Output Bit B
Output Bit C
Output Bit D
Output Bit E
Output Bit F
Output Bit G
Output Bit H
Ground
B
C
D
E
3
4
5
Q
F
G
H
6
Q
Q
7
8
GND
Q’
9
Serial Data Output
Shift Register Clear
Shift Register Clock Input
Storage Register Clock Input
Output Enable
H
10
11
12
13
14
15
16
SCLR
SCK
RCK
G
SER
QA
Serial Data Input
Output Bit A
V
CC
Supply Voltage
TRUTH TABLE
RCK
X
SCK
X
SCLR
G
H
L
Function
X
L
QA through Q = 3−state
H
X
X
Shift register clocked; Q’ = 0
H
X
↑
H
H
L
Shift register clocked; Q = Q , Q = SER
N n−1 0
↑
X
L
Contents of shift; register transferred to output latches
NOTES: L = Logic Level LOW
H = Logic Level HIGH
X = Don’t Care
↑ = Transition from LOW to HIGH level
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3
MM74HC595
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Rating
Min
−0.5
−0.5
−0.5
Max
Unit
V
V
CC
Supply Voltage
7.0
V
IN
DC Input Voltage
V
V
+ 0.5
V
CC
CC
V
OUT
DC Output Voltage
+ 0.5
20
V
I , I
IK OK
Clamp Diode Current
DC Output Current, per pin
DC VCC or GND Current, per pin
Storage Temperature Range
Power Dissipation
mA
mA
mA
°C
mW
°C
V
I
35
OUT
I
70
CC
T
STG
−65
+150
P
D
SOIC Package only
500
+260
4000
T
L
Lead Temperature
ESD
Electrostatic Discharge Capability
Human Body Model,
JESD22−A114
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
, V
DC Input or Output Voltage
Operating Temperature Range
Input Rise and Fall Times
0
V
CC
V
IN
OUT
T
A
−55
−
+125
1000
500
°C
ns
t , t
R
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
F
−
−
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
MM74HC595
ELECTRICAL CHARACTERISTICS (Note 2)
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
125°C
Symbol
Parameter
Conditions
V
CC
Typ
Guaranteed Limits
Unit
V
IH
Minimum HIGH
Level Input Voltage
2.0 V
4.5 V
6.0 V
1.50
3.15
4.20
1.50
3.15
4.20
1.50
3.15
4.20
V
V
V
V
IL
Minimum LOW
Level Input Voltage
2.0 V
4.5 V
6.0 V
0.50
1.35
1.80
0.50
1.35
1.80
0.50
1.35
1.80
V
V
V
V
OH
Minimum HIGH
Level Output
Voltage
V
IN
= V or V
2.0 V
4.5 V
6.0 V
2.00
4.50
6.00
1.90
4.40
5.90
1.90
4.40
5.90
1.90
4.40
5.90
V
V
V
⎪I ⎪ ≤ 20 mA
OUT
IH
IL
Q’
V
IN
V
IN
V
IN
= V or V
⎪I
⎪I
⎪ ≤ 4.0 mA
⎪ ≤ 5.2 mA
4.5 V
6.0 V
4.20
5.20
3.98
5.48
3.84
5.34
3.70
5.20
V
V
H
IH
IL
IL
IL
OUT
OUT
QA through Q
= V or V
⎪I
⎪I
⎪ ≤ 6.0 mA
⎪ ≤ 7.8 mA
4.5 V
6.0 V
4.20
5.70
3.98
5.48
3.84
5.34
3.70
5.20
V
V
H
IH
OUT
OUT
V
OL
Minimum LOW
Level Output
Voltage
= V or V
2.0 V
4.5 V
6.0 V
0
0
0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
V
V
⎪I
OUT
⎪ ≤ 20 mA
IH
Q’
V
V
V
V
= V or V
⎪I
⎪I
⎪ ≤ 4.0 mA
⎪ ≤ 5.2 mA
4.5 V
6.0 V
0.20
0.20
0.26
0.26
0.33
0.33
0.40
0.40
V
V
H
IN
IH
IL
OUT
OUT
QA through Q
= V or V
⎪I
⎪I
⎪ ≤ 6.0 mA
⎪ ≤ 7.8 mA
4.5 V
6.0 V
0.20
0.20
0.26
0.26
0.33
0.33
0.40
0.40
V
V
H
IN
IH
IL
OUT
OUT
I
IN
Maximum Input
Output Leakage
= V or GND
6.0 V
6.0 V
6.0 V
0.1
0.5
8.0
1.0
5.0
80
1.0
mA
mA
mA
IN
CC
I
Maximum 3−STATE
Output Leakage
= V
G = V
IH
10
OZ
CC
OUT
CC
or GND
I
Maximum Quiescent
Supply Current
V
IN
= V
I = 0 mA
OUT
160
CC
or GND
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. For a power supply of 5 V 10% the worst−case output voltages (V , and V ) occur for HC at 4.5 V. The 4.5 V values should be used
OH
OL
when designing with this supply. Worst−case V and V occur at V = 5.5 V and 4.5 V, respectively; V value at 5.5 V is 3.85 V. The worst
IH
IL
CC
IH
case leakage current (I , I , and I ) occur for CMOS at the higher voltage; so the 6.0 V values should be used.
IN CC
OZ
AC ELECTRICAL CHARACTERISTICS
(V = 5 V, T = 25°C, t = t = 6 ns)
CC
A
r
f
Symbol
Parameter
Conditions
Typ
50
Guaranteed Limit
Unit
MHz
ns
f
Maximum Operating Frequency of SCK
Maximum Propagation Delay, SCK to Q’
30
20
30
MAX
t
, t
C = 45 pF
L
12
PHL PLH
H
Maximum Propagation Delay, RCK to Q thru Q’
18
ns
A
H
t
t
, t
Maximum Output Enable Time from G to Q thru Q’
R = 1 kW
C = 45 pF
L
17
28
ns
PZH PZL
A
H
L
, t
Maximum Output Disable Time from G to Q thru Q’
R = 1 kW
L
15
25
ns
PHZ PLZ
A
H
C = 45 pF
L
t
S
Minimum Setup Time from SER to SCK
Minimum Setup Time from SCLR to SCK
Minimum Setup Time from SER to RCK (Note 3)
20
20
40
ns
ns
ns
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5
MM74HC595
AC ELECTRICAL CHARACTERISTICS (continued)
(V = 5 V, T = 25°C, t = t = 6 ns)
CC
A
r
f
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Unit
ns
t
H
Minimum Hold Time from SER to SCK
Minimum Pulse Width of SCK or RCK
0
t
W
16
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This setup time ensures the register will see stable data from the shift−register outputs. The clocks may be connected together in which case
the storage register state will be one clock pulse behind the shift register.
ELECTRICAL CHARACTERISTICS
(V = 2.0 V−6.0 V, C = 50 pF, t = t = 6 ns, unless otherwise specified)
CC
L
r
f
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
125°C
Symbol
Parameter
Conditions
C = 50 pF
V
Typ
Guaranteed Limits
Unit
CC
f
Maximum Operating
Frequency
2.0 V
4.5 V
6.0 V
10.0
45.0
50.0
6.0
30.0
35.0
4.8
4.0
ns
ns
ns
MAX
L
24.0
28.0
20.0
24.0
t
, t
Maximum Propagation
C = 50 pF
C = 150 pF
L
2.0 V
2.0 V
58.0
83.0
210.0
294.0
235.0
367.0
315.0
441.0
ns
ns
PHL PLH
L
Delay, SCK to Q’
H
C = 50 pF
C = 150 pF
L
4.5 V
4.5 V
14.0
17.0
42.0
58.0
53.0
74.0
63.0
88.0
ns
ns
L
C = 50 pF
C = 150 pF
L
6.0 V
6.0 V
10.0
14.0
36.0
50.0
45.0
63.0
54.0
76.0
ns
ns
L
Maximum Propagation
C = 50 pF
C = 150 pF
L
2.0 V
70.0
175.0
220.0
306.0
265.0
368.0
ns
ns
L
Delay, RCK to Q thru Q’
2.0 V 105.0 245.0
A
H
C = 50 pF
C = 150 pF
L
4.5 V
4.5 V
21.0
28.0
35.0
49.0
44.0
61.0
53.0
74.0
ns
ns
L
C = 50 pF
C = 150 pF
L
6.0 V
6.0 V
18.0
26.0
30.0
42.0
37.0
53.0
45.0
63.0
ns
ns
L
Maximum Propagation
2.0 V
4.5 V
6.0 V
175.0
35.0
30.0
221.0
44.0
37.0
261.0
52.0
44.0
ns
ns
ns
Delay, SCLR to Q’
H
t
t
, t
Maximum Output Enable
R = 1 kW C = 50 pF
2.0 V
75.0
175.0
220.0
306.0
265.0
368.0
ns
ns
PZH PZL
L
L
Time from G to Q thru Q’
C = 150 pF
L
2.0 V 100.0 245.0
A
H
C = 50 pF
4.5 V
4.5 V
15.0
20.0
35.0
49.0
44.0
61.0
53.0
74.0
ns
ns
L
C = 150 pF
L
C = 50 pF
6.0 V
6.0 V
13.0
17.0
30.0
42.0
37.0
53.0
45.0
63.0
ns
ns
L
C = 150 pF
L
, t
Maximum Output Disable
R = 1 kW
2.0 V
4.5 V
6.0 V
75.0
15.0
13.0
175.0
35.0
30.0
220.0
44.0
37.0
265.0
53.0
45.0
ns
ns
ns
PHZ PLZ
L
Time from G to Q thru Q’
C = 50 pF
L
A
H
t
S
Minimum Setup Time
from SER to SCK
R = 1 kW
C = 50 pF
L
2.0 V
4.5 V
6.0 V
100.0
20.0
17.0
125.0
25.0
21.0
150.0
30.0
25.0
ns
ns
ns
L
t
R
Minimum Removal Time
from SCLR to SCK
2.0 V
4.5 V
6.0 V
50.0
10.0
9.0
63.0
13.0
11.0
75.0
15.0
13.0
ns
ns
ns
t
S
Minimum Setup Time
from SCK to RCK
2.0 V
4.5 V
6.0 V
100.0
20.0
17.0
125.0
25.0
21.0
150.0
30.0
26.0
ns
ns
ns
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6
MM74HC595
ELECTRICAL CHARACTERISTICS (continued)
(V = 2.0 V−6.0 V, C = 50 pF, t = t = 6 ns, unless otherwise specified)
CC
L
r
f
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
125°C
Symbol
Parameter
Conditions
V
CC
Typ
Guaranteed Limits
Unit
t
H
Minimum Hold Time
from SER to SCK
2.0 V
4.5 V
6.0 V
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
t
W
Minimum Pulse Width of
SCK or SCLR
2.0 V
4.5 V
6.0 V
30.0
9.0
8.0
80.0
16.0
14.0
100.0
20.0
18.0
120.0
24.0
22.0
ns
ns
ns
t , t
Maximum Input Rise and
Fall Time, Clock
2.0 V
4.5 V
6.0 V
1000.0
500.0
400.0
1000.0
500.0
400.0
1000.0
500.0
400.0
ns
ns
ns
R
F
t
, t
Maximum Output Rise and
2.0 V
4.5 V
6.0 V
25.0
7.0
6.0
60.0
12.0
10.0
75.0
15.0
13.0
90.0
18.0
15.0
ns
ns
ns
THL TLH
Fall Time Q −Q
A
H
Maximum Output Rise and
Fall Time Q’
2.0 V
4.5 V
6.0 V
75.0
15.0
13.0
95.0
19.0
16.0
110.0
22.0
19.0
ns
ns
ns
H
C
Power Dissipation
Capacitance, Outputs
Enabled (Note 4)
G = V
G = GND
90.0
150.0
pF
pF
PD
CC
C
Maximum Input
Capacitance
5.0
10.0
20.0
10.0
20.0
10.0
20.0
pF
pF
IN
C
Maximum Output
Capacitance
15.0
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
4. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
Timing Diagram
NOTE:
5.
Implies that the output is in 3−state mode.
Figure 3. Timing Diagram
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7
MM74HC595
ORDERING INFORMATION
Device
†
Package
Shipping
MM74HC595M
SOIC−16
(Pb−Free)
48 Units / Tube
2500 / Tape & Reel
96 Units / Tube
MM74HC595MX
MM74HC595MTC
TSSOP−16
(Pb−Free and Halide Free)
MM74HC595MTCX
TSSOP 16
(Pb−Free and Halide Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP 16
CASE 948AH−01
ISSUE O
DATE 19 SEP 2008
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34923E
TSSOP 16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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