MMSF5N03HDR2 [ONSEMI]

6.5A, 30V, 0.04ohm, N-CHANNEL, Si, POWER, MOSFET, MINIATURE, CASE 751-07, SOP-8;


型号：	MMSF5N03HDR2
厂家：	ONSEMI
描述：	6.5A, 30V, 0.04ohm, N-CHANNEL, Si, POWER, MOSFET, MINIATURE, CASE 751-07, SOP-8 局域网开关脉冲光电二极管晶体管
文件：	总12页 (文件大小：117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MMSF5N03HD

Preferred Device

Power MOSFET

5 Amps, 30 Volts

N–Channel SO–8

These miniature surface mount MOSFETs feature ultra low R

DS(on)

and true logic level performance. They are capable of withstanding

high energy in the avalanche and commutation modes and the

drain–to–source diode has a very low reverse recovery time.

MiniMOSt devices are designed for use in low voltage, high speed

switching applications where power efficiency is important. Typical

applications are dc–dc converters, and power management in portable

and battery powered products such as computers, printers, cellular and

cordless phones. They can also be used for low voltage motor controls

in mass storage products such as disk drives and tape drives. The

avalanche energy is specified to eliminate the guesswork in designs

where inductive loads are switched and offer additional safety margin

against unexpected voltage transients.

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5 AMPERES

30 VOLTS

= 40 mW

DS(on)

N–Channel

• Ultra Low R

Provides Higher Efficiency and Extends Battery

DS(on)

Life

• Logic Level Gate Drive – Can Be Driven by Logic ICs

• Miniature SO–8 Surface Mount Package – Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

MARKING

DIAGRAM

• I

Specified at Elevated Temperature

DSS

• Avalanche Energy Specified

• Mounting Information for SO–8 Package Provided

SO–8

CASE 751

STYLE 13

S5N03

LYWW

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Drain–to–Source Voltage

Drain–to–Gate Voltage (R

Symbol

Value

Unit

Vdc

Adc

DSS

= Location Code

= Year

= Work Week

= 1.0 MΩ)

DGR

Gate–to–Source Voltage – Continuous

Drain Current – Continuous @ T = 25°C

± 20

6.5

4.4

Drain Current – Continuous @ T = 100°C

PIN ASSIGNMENT

Drain Current – Single Pulse (t ≤ 10 µs)

Apk

Total Power Dissipation @ T = 25°C

(Note 1.)

2.5

Watts

N–C

Drain

Source

Operating and Storage Temperature Range

T , T

J stg

– 55 to

150

°C

Gate

Drain

Single Pulse Drain–to–Source Avalanche

450

Top View

Energy – Starting T = 25°C

= 30 Vdc, V

= 5.0 Vdc, Peak

= 15 Apk, L = 4.0 mH, R = 25 Ω)

ORDERING INFORMATION

Thermal Resistance – Junction to Ambient

(Note 1.)

°C/W

°C

θJA

Device

Package

Shipping

2500 Tape & Reel

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

260

MMSF5N03HDR2

SO–8

1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),

10 sec. max.

Preferred devices are recommended choices for future use

and best overall value.

Semiconductor Components Industries, LLC, 2000

Publication Order Number:

November, 2000 – Rev. 6

MMSF5N03HD/D

MMSF5N03HD

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

Vdc

(BR)DSS

= 0 Vdc, I = 250 µAdc)

Temperature Coefficient (Positive)

–

mV/°C

µAdc

Zero Gate Voltage Drain Current

DSS

= 30 Vdc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

–

1.0

Gate–Body Leakage Current (V

= ± 20 Vdc, V

= 0)

–

100

nAdc

Vdc

GSS

ON CHARACTERISTICS (Note 2.)

Gate Threshold Voltage

GS(th)

= V , I = 250 µAdc)

1.0

–

2.0

5.0

3.0

–

Temperature Coefficient (Negative)

mV/°C

Static Drain–Source On–Resistance

Ohms

DS(on)

= 10 Vdc, I = 5.0 Adc)

–

0.033

0.04

0.040

0.050

= 4.5 Vdc, I = 2.5 Adc)

Forward Transconductance (V

= 3 Vdc, I = 2.5 Adc)

3.0

8.0

–

Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

–

1207

354

1680

490

iss

= 24 Vdc, V

f = 1.0 MHz)

= 0 Vdc,

Output Capacitance

oss

Transfer Capacitance

120

rss

SWITCHING CHARACTERISTICS (Note 3.)

Turn–On Delay Time

–

108

216

136

–

d(on)

= 15 Vdc, I = 5.0 Adc,

Rise Time

= 4.5 Vdc,

Turn–Off Delay Time

Fall Time

d(off)

= 9.1 Ω)

Turn–On Delay Time

Rise Time

d(on)

= 15 Vdc, I = 5.0 Adc,

= 10 Vdc,

= 9.1 Ω)

Turn–Off Delay Time

Fall Time

d(off)

Gate Charge

See Figure 8

15.2

3.4

6.6

5.6

= 24 Vdc, I = 5.0 Adc,

= 10 Vdc)

–

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (Note 2.)

Vdc

(I = 5 Adc, V

= 0 Vdc)

= 0 Vdc, T = 125°C)

–

0.88

0.77

1.3

–

Reverse Recovery Time

See Figure 15

–

(I = 5.0 Adc, V

= 0 Vdc,

dI /dt = 100 A/µs)

Reverse Recovery Stored Charge

0.037

µC

2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

3. Switching characteristics are independent of operating junction temperature.

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MMSF5N03HD

TYPICAL ELECTRICAL CHARACTERISTICS

= 10 V

T = 25°C

≥ 10 V

4.5 V

3.8 V

3.1 V

2.4 V

T = 100°C

25°C

-55°C

0.2 0.4

0.6 0.8

1.2 1.4

1.6 1.8

2.2

2.4

2.6

2.8

3.2

3.4

3.6

3.8

V , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

V , GATE-TO-SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

Figure 2. Transfer Characteristics

0.2

0.16

0.12

0.0425

0.04

= 2.5 A

T = 25°C

= 4.5 V

0.0375

0.035

0.0325

0.03

0.08

0.04

10 V

V , GATE-TO-SOURCE VOLTAGE (VOLTS)

I , DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus

Gate–To–Source Voltage

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

1000

100

1.6

1.4

1.2

= 0 V

= 10 V

= 5 A

T = 125°C

100°C

25°C

0.8

0.6

-ā50

-ā25

100

125

150

, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

T , JUNCTION TEMPERATURE (°C)

Figure 5. On–Resistance Variation with

Temperature

Figure 6. Drain–To–Source Leakage

Current versus Voltage

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MMSF5N03HD

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (∆t)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain–gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

The capacitance (C ) is read from the capacitance curve at

a voltage corresponding to the off–state condition when

iss

calculating t

and is read at a voltage corresponding to the

on–state when calculating t

d(on)

d(off)

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that

t = Q/I

G(AV)

During the rise and fall time interval when switching a

resistive load, V remains virtually constant at a level

known as the plateau voltage, V

. Therefore, rise and fall

SGP

times may be approximated by the following:

t = Q x R /(V

– V )

GSP

t = Q x R /V

GSP

where

= the gate drive voltage, which varies from zero to V

= the gate drive resistance

and Q and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

= R

In [V /(V

In (V /V

iss GG GSP

– V )]

GSP

)

d(on)

d(off)

iss

GG GG

3500

3000

2500

2000

1500

1000

= 0 V

T = 25°C

iss

rss

oss

500

rss

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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MMSF5N03HD

1000

= 15 V

= 5 A

= 4.5 V

T = 25°C

100

= 5 A

T = 25°C

d(off)

d(on)

R , GATE RESISTANCE (OHMS)

100

Q , TOTAL CHARGE (nC)

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or

commutating diode. Of particular interest are the reverse

recovery characteristics which play a major role in

determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of

the body diode itself. The body diode is a minority carrier

high di/dts. The diode’s negative di/dt during t is directly

controlled by the device clearing the stored charge.

However, the positive di/dt during t is an uncontrollable

diode characteristic and is usually the culprit that induces

current ringing. Therefore, when comparing diodes, the

ratio of t /t serves as a good indicator of recovery

b a

abruptness and thus gives a comparative estimate of

probable noise generated. A ratio of 1 is considered ideal and

values less than 0.5 are considered snappy.

device, therefore it has a finite reverse recovery time, t , due

to the storage of minority carrier charge, Q , as shown in

the typical reverse recovery wave form of Figure 15. It is this

stored charge that, when cleared from the diode, passes

through a potential and defines an energy loss. Obviously,

repeatedly forcing the diode through reverse recovery

further increases switching losses. Therefore, one would

Compared to ON Semiconductor standard cell density

low voltage MOSFETs, high cell density MOSFET diodes

are faster (shorter t ), have less stored charge and a softer

reverse recovery characteristic. The softness advantage of

the high cell density diode means they can be forced through

reverse recovery at a higher di/dt than a standard cell

MOSFET diode without increasing the current ringing or the

noise generated. In addition, power dissipation incurred

from switching the diode will be less due to the shorter

recovery time and lower switching losses.

like a diode with short t and low Q

minimize these losses.

specifications to

The abruptness of diode reverse recovery effects the

amount of radiated noise, voltage spikes, and current

ringing. The mechanisms at work are finite irremovable

circuit parasitic inductances and capacitances acted upon by

= 0 V

T = 25°C

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

V , SOURCE-TO-DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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MMSF5N03HD

di/dt = 300 A/µs

Standard Cell Density

High Cell Density

t, TIME

Figure 11. Reverse Recovery Time (t )

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and must be adjusted for operating

conditions differing from those specified. Although industry

practice is to rate in terms of energy, avalanche energy

capability is not a constant. The energy rating decreases

non–linearly with an increase of peak current in avalanche

and peak junction temperature.

the maximum simultaneous drain–to–source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (T ) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal Resistance –

General Data and Its Use.”

Although many E–FETs can withstand the stress of

drain–to–source avalanche at currents up to rated pulsed

Switching between the off–state and the on–state may

traverse any load line provided neither rated peak current

current (I

), the energy rating is specified at rated

) nor rated voltage (V

) is exceeded, and that the

continuous current (I ), in accordance with industry

DSS

transition time (t , t ) does not exceed 10 µs. In addition the

custom. The energy rating must be derated for temperature

as shown in the accompanying graph (Figure 13). Maximum

r f

total power averaged over a complete switching cycle must

not exceed (T

– T )/(R

energy at currents below rated continuous I can safely be

assumed to equal the values indicated.

J(MAX)

θJC

A power MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For

100

450

= 10 V

SINGLE PULSE

= 25°C

= 15 A

100 µs

1 ms

10 ms

300

150

LIMIT

DS(on)

THERMAL LIMIT

PACKAGE LIMIT

0.1

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″

thick single sided), 10s max.

0.01

100

125

150

0.1

100

T , STARTING JUNCTION TEMPERATURE (°C)

V , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

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MMSF5N03HD

TYPICAL ELECTRICAL CHARACTERISTICS

D = 0.5

0.2

0.1

Normalized to θja at 10s.

0.05

0.02

0.01

0.0163 Ω

0.0652 Ω

0.1988 Ω

0.6411 Ω

0.9502 Ω

Chip

0.01

0.0307 F

0.1668 F

1.0E+00

0.5541 F

1.9437 F

72.416 F

Ambient

1.0E+03

SINGLE PULSE

1.0E-04

0.001

1.0E-05

1.0E-03

1.0E-02

1.0E-01

t, TIME (s)

1.0E+01

1.0E+02

Figure 14. Thermal Response

di/dt

TIME

0.25 I

Figure 15. Diode Reverse Recovery Waveform

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MMSF5N03HD

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must

be the correct size to ensure proper solder connection

interface between the board and the package. With the

correct pad geometry, the packages will self–align when

subjected to a solder reflow process.

0.060

1.52

0.275

7.0

0.155

4.0

0.024

0.6

0.050

1.270

inches

SO–8 POWER DISSIPATION

The power dissipation of the SO–8 is a function of the

input pad size. This can vary from the minimum pad size

for soldering to the pad size given for maximum power

dissipation. Power dissipation for a surface mount device is

into the equation for an ambient temperature T of 25°C,

one can calculate the power dissipation of the device which

in this case is 2.5 Watts.

150°C – 25°C

P =

= 2.5 Watts

determined by T

, the maximum rated junction

, the thermal resistance from

J(max)

50°C/W

temperature of the die, R

θJA

The 50°C/W for the SO–8 package assumes the

recommended footprint on a glass epoxy printed circuit

board to achieve a power dissipation of 2.5 Watts using the

footprint shown. Another alternative would be to use a

ceramic substrate or an aluminum core board such as

Thermal Cladt. Using board material such as Thermal

Clad, the power dissipation can be doubled using the same

footprint.

the device junction to ambient; and the operating

temperature, T . Using the values provided on the data

sheet for the SO–8 package, P can be calculated as

follows:

– T

J(max)

θJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated

to a high temperature, failure to complete soldering within

a short time could result in device failure. Therefore, the

following items should always be observed in order to

minimize the thermal stress to which the devices are

subjected.

• Always preheat the device.

• The delta temperature between the preheat and

soldering should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum

temperature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering

method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the

maximum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied

during cooling.

* Soldering a device without preheating can cause

excessive thermal shock and stress which can result in

damage to the device.

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MMSF5N03HD

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of

temperature versus time. The line on the graph shows the

actual temperature that might be experienced on the surface

of a test board at or near a central solder joint. The two

profiles are based on a high density and a low density

board. The Vitronics SMD310 convection/infrared reflow

soldering system was used to generate this profile. The type

of solder used was 62/36/2 Tin Lead Silver with a melting

point between 177–189°C. When this type of furnace is

used for solder reflow work, the circuit boards and solder

joints tend to heat first. The components on the board are

then heated by conduction. The circuit board, because it has

a large surface area, absorbs the thermal energy more

efficiently, then distributes this energy to the components.

Because of this effect, the main body of a component may

be up to 30 degrees cooler than the adjacent solder joints.

control settings that will give the desired heat pattern. The

operator must set temperatures for several heating zones

and a figure for belt speed. Taken together, these control

settings make up a heating “profile” for that particular

circuit board. On machines controlled by a computer, the

computer remembers these profiles from one operating

session to the next. Figure 16 shows a typical heating

profile for use when soldering a surface mount device to a

printed circuit board. This profile will vary among

soldering systems, but it is a good starting point. Factors

that can affect the profile include the type of soldering

system in use, density and types of components on the

board, type of solder used, and the type of board or

substrate material being used. This profile shows

STEP 1

PREHEAT

ZONE 1

“RAMP”

STEP 2

VENT

“SOAK” ZONES 2 & 5

“RAMP”

STEP 3

HEATING

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

205° TO 219°C

PEAK AT

SOLDER

JOINT

170°C

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

200°C

150°C

100°C

5°C

160°C

150°C

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

100°C

140°C

MASS OF ASSEMBLY)

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

TIME (3 TO 7 MINUTES TOTAL)

MAX

Figure 16. Typical Solder Heating Profile

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MMSF5N03HD

PACKAGE DIMENSIONS

SO–8

CASE 751–07

ISSUE V

–X–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

0.25 (0.010)

–Y–

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.197

0.157

0.069

0.020

4.80

3.80

1.35

0.33

5.00 0.189

4.00 0.150

1.75 0.053

0.51 0.013

N X 45

SEATING

PLANE

–Z–

1.27 BSC

0.050 BSC

0.10 (0.004)

0.10

0.19

0.40

0.25 0.004

0.25 0.007

1.27 0.016

0.010

0.050

0.020

0.244

0.25

5.80

0.50 0.010

6.20 0.228

0.25 (0.010)

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

XXXXXX

ALYW

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MMSF5N03HD

Notes

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MMSF5N03HD

MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

Thermal Clad is a registered trademark of the Bergquist Company.

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

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