MT9M031I12STC-DPBR [ONSEMI]
CMOS Digital Image Sensor;
| 型号： | MT9M031I12STC-DPBR |
| 厂家： | 
ONSEMI |
| 描述： | CMOS Digital Image Sensor 时钟 传感器 换能器 |
| 文件： | 总34页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features
1/3-Inch CMOS Digital Image Sensor
MT9M021/MT9M031 Datasheet, Rev. G
For the latest datasheet revision, please visit www.onsemi.com
Features
• Superior low-light performance
• HD video (720p60)
Table 1:
Key Parameters
Parameter
Typical Value
1/3-inch (6 mm)
1280 x 960 = 1.2 Mp
3.75m
RGB Bayer or
Monochrome
• Global shutter
Optical format
Active pixels
Pixel size
• Video/Single Frame mode
• Flexible row-skip modes
• On-chip AE and statistics engine
• Parallel and serial output
• Support for external LED or flash
• Auto black level calibration
• Context switching
Color filter array
Shutter type
Global shutter
6 – 50 MHz
Input clock range
Output pixel clock (maximum)
74.25 MHz
Serial
HiSPi (iBGA package only)
12-bit
Output
Applications
• Scene processing
• Scanning and machine vision
• 720p60 video applications
Parallel
Full resolution 45 fps
Frame rate
720p
60 fps
Responsivity (Monochrome)
Responsivity (Color)
SNRMAX
6.1 V/lux-sec
5.3 V/lux-sec
38 dB
General Description
Dynamic range
I/O
64 dB
The ON Semiconductor MT9M021/MT9M031 is a 1/3-
inch CMOS digital image sensor with an active-pixel
array of 1280H x 960V. It includes sophisticated camera
functions such as auto exposure control, windowing,
scaling, row skip mode, and both video and single
frame modes. It is designed for low light performance
and features a global shutter for accurate capture of
moving scenes. It is programmable through a simple
two-wire serial interface. The MT9M021/MT9M031
produces extraordinarily clear, sharp digital pictures,
and its ability to capture both continuous video and
single frames makes it the perfect choice for a wide
range of applications, including scanning and HD
video.
1.8 or 2.8 V
1.8 V
Digital
Analog
HiSPi
Supply
voltage
2.8 V
0.4 V
Power consumption
<400 mW
Operating temperature (ambient) –30°C to +70°C
9 x 9 mm 64-pin iBGA
Package options
10x10mm 48-pin iLCC
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Product Description
Part Number
Orderable Product Attribute Description
MT9M021IA3XTC-DPBR
MT9M021IA3XTC-DRBR
MT9M021IA3XTM-DPBR
MT9M021IA3XTM-DRBR
MT9M021IA3XTMZ-DPBR
MT9M021IA3XTMZ-DRBR
MT9M021IA3XTMZ-TPBR
MT9M031D00STMC24BC1-200
MT9M031I12STC-DPBR
MT9M031I12STC-DRBR
MT9M031I12STM-DPBR
MT9M031I12STM-DRBR
MT9M031I12STMZ-DRBR
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1 MP 1/6" SOC
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Tape & Reel with Protective Film, Double Side BBAR Glass
Die Sales, 200 m Thickness
1 MP 1/6" SOC
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
1.2 MP 1/3" GS CIS
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Ordering Information
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Ordering Information
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Features Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9x9mm 64-Ball iBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
48 iLCC Package, Parallel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Quantum Efficiency – Monochrome Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Quantum Efficiency – Color Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
64-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
48-pin iLCC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Descriptions - 64-Ball iBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Descriptions - 48 iLCC Package, Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
I/O Timing Characteristics
I/O Rise Slew Rate (2.8V VDD_IO)
I/O Fall Slew Rate (2.8V VDD_IO)
I/O Rise Slew Rate (1.8V VDD_IO)
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
I/O Fall Slew Rate (1.8V VDD_IO)
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Operating Current Consumption for Parallel Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Standby Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Input Voltage and Current (HiSPi Power Supply 0.4 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
General Description
General Description
The ON Semiconductor MT9M021/MT9M031 can be operated in its default mode or
programmed for frame size, exposure, gain, and other parameters. The default mode
output is a full-resolution image at 45 frames per second (fps). It outputs 12-bit raw data,
using either the parallel or serial (HiSPi) output ports. The device may be operated in
video (master) mode or in frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a
synchronized pixel clock. A dedicated FLASH pin can be programmed to control
external LED or flash exposure illumination.
The MT9M021/MT9M031 includes additional features to allow application-specific
tuning: windowing, adjustable auto-exposure control, auto black level correction,
on-board temperature sensor, and row skip and digital binning modes.
The sensor is designed to operate in a wide temperature range (–30°C to +70°C).
Functional Overview
The MT9M021/MT9M031 is a progressive-scan sensor that generates a stream of pixel
data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be
optionally enabled to generate all internal clocks from a single master input clock
running between 6 and 50 MHz. The maximum output pixel rate is 74.25 Mp/s, corre-
sponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1:
Block Diagram
External
Clock
Temperature
sensor
OTPM
Memory
PLL
Active Pixel Sensor
(APS)
Array
Timing and Control
(Sequencer)
Auto Exposure
and Stats Engine
Power
Serial
Output
Parallel
Output
Pixel Data Path
(Signal Processing)
Analog Processing and
A/D Conversion
Flash
Trigger
Two-Wire
Serial
Control Registers
Interface
User interaction with the sensor is through the two-wire serial bus, which communi-
cates with the array control, analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active- Pixel Sensor array. The MT9M021/MT9M031 features global
shutter technology for accurate capture of moving images. The exposure of the entire
array is controlled by programming the integration time by register setting. All rows
simultaneously integrate light prior to readout. Once a row has been read, the data from
the columns is sequenced through an analog signal chain (providing offset correction
and gain), and then through an analog-to- digital converter (ADC). The output from the
ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
processing signal chain (which provides further data path corrections and applies digital
gain). The pixel data are output at a rate of up to 74.25 Mp/s, in parallel to frame and line
synchronization signals.
Features Overview
The MT9M021/MT9M031 Global Sensor shutter has a wide array of features to enhance
functionality and to increase versatility. A summary of features follows. Please refer to
the MT9M021/MT9M031 Developer Guide for detailed feature descriptions, register
settings, and tuning guidelines and recommendations.
•
Operating Modes
The MT9M021/MT9M031 works in master (video), trigger (single frame), or Auto Trig-
ger modes. In master mode, the sensor generates the integration and readout timing.
In trigger mode, it accepts an external trigger to start exposure, then generates the
exposure and readout timing. The exposure time is programmed through the two-
wire serial interface for both modes.
Note:
Trigger mode is not compatible with the HiSPi interface.
•
•
Window Control
Configurable window size and blanking times allow a wide range of resolutions and
frame rates. Digital binning and skipping modes are supported, as are vertical and
horizontal mirror operations.
Context Switching
Context switching may be used to rapidly switch between two sets of register values.
Refer to the MT9M021/MT9M031 Developer Guide for a complete set of context
switchable registers.
•
•
Gain
The MT9M021/MT9M031 Global Shutter sensor can be configured for analog gain of
up to 8x, and digital gain of up to 8x.
Automatic Exposure Control
The integrated automatic exposure control may be used to ensure optimal settings of
exposure and gain are computed and updated every other frame. Refer to the
MT9M021/MT9M031 Developer Guide for more details.
•
•
HiSPi
The MT9M021/MT9M031 Global Shutter image sensor supports two or three lanes of
Streaming-SP or Packetized-SP protocols of ON Semiconductor's High-Speed Serial
Pixel Interface.
PLL
An on chip PLL provides reference clock flexibility and supports spread spectrum
sources for improved EMI performance.
•
•
Reset
The MT9M021/MT9M031 may be reset by a register write, or by a dedicated input pin.
Output Enable
The MT9M021/MT9M031 output pins may be tri-stated using a dedicated output
enable pin.
•
•
•
•
•
Temperature Sensor
Black Level Correction
Row Noise Correction
Column Correction
Test Patterns
Several test patterns may be enabled for debug purposes. These include a solid color,
color bar, fade to grey, and a walking 1s test pattern.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Figure 2:
Typical Configuration: Serial Four-Lane HiSPi Interface
Digital Digital
I/O Core
power power
HiSPi
power
PLL
Analog Analog
1
1
1
1
1
1
power power power
VDD_IO VDD
VDD_PLL VAA VAA_PIX
SLVS0_P
SLVS0_N
SLVS1_P
Master clock
(6–50 MHz)
EXTCLK
SLVS1_N
SLVS2_P
SLVS2_N
To
controller
SDATA
SCLK
SLVS3_P
From
controller
SLVS3_N
SLVSC_P
OE_BAR
STANDBY
RESET_BAR
SLVSC_N
TEST
FLASH
AGND
DGND
VDD_IO
VDD
VDD_SLVS
VDD_PLL
VAA
VAA_PIX
Digital
ground
Analog
ground
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire
speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Refer to the MT9M021/MT9M031 demo headboard schematics for
circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that cou-
pling with the digital power planes is minimized.
7. Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2 or 3 lane HiSPi.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Figure 3:
Typical Configuration: Parallel Pixel Data Interface
Digital Digital
I/O core
power power
PLL Analog Analog
power power power
1
1
1
1
1
VDD_IO VDD
VDD_PLL VAA VAA_PIX
Master clock
(6–50 MHz)
EXTCLK
DOUT [11:0]
PIXCLK
LINE_VALID
To
controller
SDATA
SCLK
TRIGGER
OE_BAR
FRAME_VALID
From
Controller
FLASH
STANDBY
RESET_BAR
TEST
AGND
DGND
VAA
VDD_IO
VDD
VDD_PLL
VAA_PIX
Digital
ground
Analog
ground
Notes: 1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5k, but it may be greater for slower two-wire
speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.
4. The serial interface output pads can be left unconnected if the parallel output interface is used.
5. ON Semiconductor recommends that 0.1μF and 10μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on lay-
out and design considerations. Refer to the MT9M021/MT9M031 demo headboard schematics for
circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that cou-
pling with the digital power planes is minimized.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Figure 4:
9x9mm 64-Ball iBGA Package
1
2
3
4
5
6
7
8
SLVS1P
VDD
STANDBY
SLVS0N
SLVS0P
SLVS1N
VDD
A
B
C
D
E
VDD
SLVSCP
SLVS3N
SLVS2N
SLVS3P
SLVS2P
DGND
VAA
VAA
VDD_PLL
EXTCLK
SADDR
SLVSCN
VDD
AGND
AGND
VDD_
SLVS
SCLK
DGND
VDD
VAA_PIX
RESERVED
TEST
SDATA
DGND
VAA_PIX
RESERVED
RESERVED
OE_BAR
LINE_
VALID
FRAME_
VALID
VDD_IO
PIXCLK
FLASH
DGND
DOUT8
DOUT4
DOUT0
DOUT9
DOUT5
DOUT1
DOUT10
DOUT6
DOUT2
DOUT11
DOUT7
DOUT3
DGND
VDD_IO
VDD_IO
VDD_IO
F
DGND
TRIGGER
G
H
DGND
VDD_IO
RESET
_BAR
Top View
(Ball Down)
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Table 3:
Name
Pin Descriptions - 64-Ball iBGA Package
iBGA Pin
A2
Type
Description
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
VDD_PLL
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
VAA
Output
Output
Output
Output
Input
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 1, differential P.
Standby-mode enable pin (active HIGH).
PLL power.
A3
A4
A5
A8
B1
Power
Output
Output
Output
Output
Power
Input
B2
HiSPi serial DDR clock differential N.
HiSPi serial DDR clock differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 2, differential P.
Analog power.
B3
B4
B5
B7, B8
C1
EXTCLK
External input clock.
VDD_SLVS
SLVS3_N
SLVS3_P
DGND
C2
Power
Output
Output
HiSPi power.
C3
HiSPi serial data, lane 3, differential N.
HiSPi serial data, lane 3, differential P.
C4
C5, D4, D5, E5, F5, G5,
H5
Power
Digital GND.
VDD
AGND
A6, A7, B6, C6, D6
Power
Power
Input
Digital power.
C7, C8
Analog GND.
SADDR
D1
Two-Wire Serial address select.
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
SCLK
D2
Input
SDATA
D3
I/O
VAA_PIX
LINE_VALID
FRAME_VALID
PIXCLK
FLASH
D7, D8
Power
Output
Output
Output
Output
Power
Output
Output
Output
Output
Input
Pixel power.
E1
Asserted when DOUT line data is valid.
Asserted when DOUT frame data is valid.
Pixel clock out. DOUT is valid on rising edge of this clock.
Control signal to drive external light sources.
I/O supply power.
E2
E3
E4
VDD_IO
DOUT8
E6, F6, G6, H6, H7
F1
F2
Parallel pixel data output.
DOUT9
Parallel pixel data output.
DOUT10
DOUT11
TEST
F3
Parallel pixel data output.
F4
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND).
Parallel pixel data output.
F7
DOUT4
G1
G2
G3
G4
G7
G8
H1
H2
H3
H4
Output
Output
Output
Output
Input
DOUT5
Parallel pixel data output.
DOUT6
Parallel pixel data output.
DOUT7
Parallel pixel data output.
TRIGGER
OE_BAR
DOUT0
Exposure synchronization input.
Output enable (active LOW).
Parallel pixel data output (LSB)
Parallel pixel data output.
Input
Output
Output
Output
Output
DOUT1
DOUT2
Parallel pixel data output.
DOUT3
Parallel pixel data output.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Table 3:
Name
Pin Descriptions (continued)- 64-Ball iBGA Package
iBGA Pin
Type
Input
n/a
Description
RESET_BAR
H8
Asynchronous reset (active LOW). All settings are restored to factory
default.
Reserved
E7, E8, F8
Reserved (do not connect).
Figure 5:
48 iLCC Package, Parallel Output
6
5
4
3
2
1
48 47 46 45 44 43
NC
NC
VAA
DOUT7
DOUT8
7
8
42
41
40
39
38
37
36
35
34
33
32
31
DOUT9
9
DOUT10
DOUT11
AGND
10
11
12
13
14
15
16
17
18
VAA_PIX
VAA_PIX
VAA
VDD_IO
PIXCLK
AGND
VDD
SCLK
VAA
SDATA
Reserved
RESET_BAR
VDD_IO
Reserved
Reserved
19 20 21 22 23 24 25 26 27 28 29 30
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Features Overview
Table 4:
Pin Descriptions - 48 iLCC Package, Parallel
Pin Number
Name
DOUT4
DOUT5
DOUT6
VDD_PLL
EXTCLK
DGND
Type
Output
Output
Output
Power
Input
Description
1
2
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
PLL power.
3
4
5
External input clock.
6
Power
Output
Output
Output
Output
Output
Power
Output
Power
Input
Digital ground.
7
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
VDD_IO
PIXCLK
VDD
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output (MSB).
I/O supply power.
8
9
10
11
12
13
14
15
16
17
Pixel clock out. DOUT is valid on rising edge of this clock.
Digital power.
SCLK
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
SDATA
I/O
RESET_BAR
Input
Asynchronous reset (active LOW). All settings are restored to factory
default.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VDD_IO
VDD
Power
Power
I/O supply power.
Digital power.
NC
No connection.
NC
No connection.
STANDBY
OE_BAR
SADDR
Input
Input
Input
Input
Output
Input
Output
Output
Power
n/a
Standby-mode enable pin (active HIGH).
Output enable (active LOW).
Two-Wire Serial address select.
Manufacturing test enable pin (connect to DGND).
Flash output control.
Exposure synchronization input.
Asserted when DOUT frame data is valid.
Asserted when DOUT line data is valid.
Digital ground
TEST
FLASH
TRIGGER
FRAME_VALID
LINE_VALID
DGND
Reserved
Reserved
Reserved
VAA
Reserved (do not connect).
Reserved (do not connect).
Reserved (do not connect).
Analog power.
n/a
n/a
Power
Power
Power
Power
Power
Power
Power
AGND
Analog ground.
VAA
Analog power.
VAA_PIX
VAA_PIX
AGND
Pixel power.
Pixel power.
Analog ground.
VAA
Analog power.
NC
No connection.
NC
No connection.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Table 4:
Pin Descriptions (continued)- 48 iLCC Package, Parallel
Pin Number
Name
NC
Type
Description
43
44
45
46
47
48
No connection.
DGND
DOUT0
DOUT1
DOUT2
DOUT3
Power
Output
Output
Output
Output
Digital ground.
Parallel pixel data output (LSB)
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Electrical Specifications
Unless otherwise stated, the following specifications apply to the following conditions:
VDD = 1.8V – 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V ± 0.3V;
VDD_SLVS = 0.4V – 0.1/+0.2; T = -30°C to +70°C; output load = 10pF;
A
PIXCLK frequency = 74.25 MHz; HiSPi off.
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 6 and Table 5.
Figure 6:
Two-Wire Serial Bus Timing Parameters
SDATA
t
t
f
t
t
t
t
t
t
SU;DAT
LOW
HD;STA
f
r
r
BUF
SCLK
t
t
t
HD;STA
SU;STA
SU;STO
t
t
HIGH
HD;DAT
P
S
S
Sr
Note:
Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register
address are issued.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Table 5:
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; TA = 25°C
Standard-Mode
Fast-Mode
Parameter
Symbol
Min
Max
Min
Max
Unit
SCLK Clock Frequency
fSCL
0
100
0
400
KHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
tHD;STA
4.0
-
0.6
-
S
LOW period of the SCLK clock
HIGH period of the SCLK clock
tLOW
tHIGH
tSU;STA
4.7
4.0
4.7
-
-
-
1.3
0.6
0.6
-
-
-
S
S
S
Set-up time for a repeated START
condition
Data hold time:
tHD;DAT
tSU;DAT
tr
04
250
-
3.455
06
1006
20 + 0.1Cb7
20 + 0.1Cb7
0.6
0.95
S
nS
nS
nS
S
S
Data set-up time
-
1000
300
-
-
300
300
-
Rise time of both SDATA and SCLK signals
Fall time of both SDATA and SCLK signals
Set-up time for STOP condition
tf
-
tSU;STO
tBUF
4.0
4.7
Bus free time between a STOP and START
condition
-
1.3
-
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Cb
CIN_SI
CLOAD_SD
RSD
-
-
400
3.3
30
-
-
400
3.3
30
pF
pF
-
-
pF
1.5
4.7
1.5
4.7
K
Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
I/O Timing
Figure 7:
By default, the MT9M021/MT9M031 launches pixel data, FV and LV with the falling edge
of PIXCLK. The expectation is that the user captures DOUT[11:0], FV and LV using the
rising edge of PIXCLK. The launch edge of PIXCLK can be configured in register R0x3028.
See Figure 7 below and Table 6 on page 18 for I/O timing (AC) characteristics.
I/O Timing Diagram
t
t
t
RP
FP
t
R
F
90%
10%
90%
10%
t
EXTCLK
EXTCLK
PIXCLK
t
PD
Pxl_0
Pxl_1
Pxl_2
Pxl_n
Data[11:0]
t
t
t
PLH
PFL
PLL
t
PFH
LINE_VALID/
FRAME_VALID
FRAME_VALID trails
LINE_VALID by 6 PIXCLKs.
FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
1
Table 6:
I/O Timing Characteristics
Parallel Output
VDD_IO=2.8V
VDD_IO=1.8V
Symbol Definition
Condition
Min
6
Typ
Max
Min
Typ
Max
50
166
4
Unit
MHz
ns
fEXTCLK
Input clock frequency
50
166
4
6
tEXTCLK Input clock period
20
20
tR
tF
Input clock rise time
Input clock fall time
3
3
3
3
ns
PLL enabled
PLL enabled
4
4
ns
tRP
2.3
3
4.6
2.3
3
4.6
ns
Slew setting = 4
(default)
PIXCLK rise time
tFP
4.4
60
4.4
ns
Slew setting = 4
(default)
PIXCLK fall time
PIXCLK duty cycle
40
6
50
40
6
50
60
%
fPIXCLK
74.25
74.25
MHz
Nominal
voltages, PLL
Enabled
PIXCLK frequency2
tPD
-3
2.3
4
-3
2.3
4.5
ns
Nominal
PIXCLK to data valid
voltages, PLL
Enabled
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
1
Table 6:
I/O Timing Characteristics (continued)
Parallel Output
VDD_IO=2.8V
VDD_IO=1.8V
Symbol Definition
Condition
Nominal
voltages, PLL
Enabled
Min
Typ
Max
Min
Typ
Max
Unit
tPFH
-3
1.5
4
4
4
4
-3
1.5
4.5
ns
PIXCLK to FV HIGH
tPLH
tPFL
tPLL
-3
-3
-3
2.3
1.5
2
-3
-3
-3
2.3
1.5
2
4.5
4.5
4.5
ns
ns
ns
Nominal
voltages, PLL
Enabled
PIXCLK to LV HIGH
PIXCLK to FV LOW
PIXCLK to LV LOW
Nominal
voltages, PLL
Enabled
Nominal
voltages, PLL
Enabled
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
ambient at 90% of VDD_IO, and -30°C at 110% of VDD_IO. All values are taken at the 50% transition
point. The loading used is 20pF.
2. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
1
Table 7:
I/O Rise Slew Rate (2.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
1.08
0.77
0.58
0.44
0.32
0.23
0.16
0.10
1.77
1.26
0.95
0.70
0.51
0.37
0.25
0.15
2.72
1.94
1.46
1.08
0.78
0.56
0.38
0.22
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
ambient at 90% of VDD_IO, and -30°C at 110% of VDD_IO. All values are taken at the 50% transition
point. The loading used is 20pF.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
19
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
1
Table 8:
I/O Fall Slew Rate (2.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
1.00
0.76
0.60
0.46
0.35
0.25
0.17
0.11
1.62
1.24
0.98
0.75
0.56
0.40
0.27
0.16
2.41
1.88
1.50
1.16
0.86
0.61
0.41
0.24
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
ambient at 90% of VDD_IO, and -30°C at 110% of VDD_IO. All values are taken at the 50% transition
point. The loading used is 20pF.
1
Table 9:
I/O Rise Slew Rate (1.8V VDD_IO)
Min
Typ
Max
Units
Parallel Slew Rate
(R0x306E[15:13])
Conditions
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.41
0.30
0.24
0.19
0.14
0.10
0.07
0.04
0.65
0.47
0.37
0.28
0.21
0.15
0.10
0.06
1.10
0.79
0.61
0.46
0.34
0.24
0.16
0.10
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Note: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
ambient at 90% of VDD_IO, and -30°C at 110% of VDD_IO. All values are taken at the 50% transition
point. The loading used is 20pF.
1
Table 10:
I/O Fall Slew Rate (1.8V VDD_IO)
Parallel Slew Rate
(R0x306E[15:13])
Conditions
Min
Typ
Max
Units
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
0.42
0.32
0.26
0.20
0.16
0.12
0.08
0.05
0.68
0.51
0.41
0.32
0.24
0.18
0.12
0.07
1.11
0.84
0.67
0.52
0.39
0.28
0.19
0.11
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
Notes: 1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C
ambient at 90% of VDD_IO, and -30°C at 110% of VDD_IO. All values are taken at the 50% transition
point. The loading used is 20pF.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
20
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
DC Electrical Characteristics
The DC electrical characteristics are shown in Table 11, Table 12, Table 13, and Table 14.
Table 11:
DC Electrical Characteristics
Definition
Symbol
VDD
Condition
Min
Typ
1.8
1.8/2.8
2.8
Max
1.95
1.9/3.1
3.1
Unit
V
Core digital voltage
I/O digital voltage
Analog voltage
1.7
VDD_IO
VAA
1.7/2.5
V
2.5
V
VAA_PIX
VDD_PLL
Pixel supply voltage
PLL supply voltage
2.5
2.8
3.1
V
2.5
2.8
3.1
V
VDD_SLVS HiSPi supply voltage
0.3
VDD_IO * 0.7
–
0.4
–
0.6
V
VIH
Input HIGH voltage
–
V
–
VDD_IO *
0.3
V
VIL
Input LOW voltage
No pull-up resistor; VIN = VDD_IO or
DGND
20
–
–
A
IIN
Input leakage current
VOH
VOL
IOH
IOL
Output HIGH voltage
Output LOW voltage
Output HIGH current
Output LOW current
VDD_IO – 0.3
–
–
–
–
–
0.4
–
V
VDD_IO = 2.8V
At specified VOH
At specified VOL
–
–22
–
V
mA
mA
22
Caution Stresses greater than those listed in Table 12 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other con-
ditions above those indicated in the operational sections of this specification is not implied.
Table 12:
Absolute Maximum Ratings
Symbol
VSUPPLY
ISUPPLY
IGND
Parameter
Minimum
–0.3
–
Maximum
4.5
Unit
V
Symbol
VSUPPLY
ISUPPLY
IGND
Power supply voltage (all supplies)
Total power supply current
Total ground current
DC input voltage
200
mA
mA
V
–
200
VIN
–0.3
–0.3
–40
VDD_IO + 0.3
VDD_IO + 0.3
+85
VIN
VOUT
DC output voltage
V
VOUT
1
1
TSTG
Storage temperature
°C
TSTG
Note: 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 13:
Operating Current Consumption for Parallel Output
VAA = VAA_PIX = VDD_IO = VDD_PLL = 2.8V; VDD= 1.8V; PLL Enabled and PIXCLK = 74.25 MHz; TA = 25°C; CLOAD = 10pF
Condition
Symbol
IDD1
Min
Typ
45
501
45
6
Max
55
–
Unit
mA
mA
mA
mA
mA
Digital operating current
I/O digital operating current
Analog operating current
Pixel supply current
Parallel, Streaming, Full resolution 45 fps
Parallel, Streaming, Full resolution 45 fps
Parallel, Streaming, Full resolution 45 fps
Parallel, Streaming, Full resolution 45 fps
Parallel, Streaming, Full resolution 45 fps
IDD_IO
IAA
50
10
8
IAA_PIX
IDD_PLL
PLL supply current
6
Note: 1. IDD_IO operating current is specified with image at 1/2 saturation level.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
21
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Table 14:
Standby Current Consumption
Analog - VAA + VAA_PIX + VDD_PLL; Digital - VDD + VDD_IO; TA = 25°C
Definition
Condition
Min
Typ
Max
Unit
Analog, 2.8V
Digital, 1.8V
Analog, 2.8V
Digital, 1.8V
Analog, 2.8V
Digital, 1.8V
Analog, 2.8V
Digital, 1.8V
–
–
–
–
–
–
–
–
3
8
10
75
20
1.3
10
75
20
1.3
A
A
A
mA
A
A
A
mA
Hard standby (clock off, driven low)
12
0.87
3
Hard standby (clock on, EXTCLK = 20 MHz)
Soft standby (clock off, driven low)
8
12
0.87
Soft standby (clock on, EXTCLK = 20 MHz)
HiSPi Electrical Specifications
The ON Semiconductor MT9M021/MT9M031 sensor supports SLVS mode only, and
does not have a DLL for timing adjustments. Refer to the High-Speed Serial Pixel (HiSPi)
Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications,
and timing information. The VDD_SLVS supply in this datasheet corresponds to VDD_TX
in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as
referenced in the specification. The HiSPi transmitter electrical specifications are listed
at 700 MHz.
Table 15:
Parameter
Input Voltage and Current (HiSPi Power Supply 0.4 V)
Measurement Conditions: Max Freq 700 MHz
Symbol
Min
Typ
Max
Unit
Supply current (PWRHiSPi)
IDD_SLVS
–
10
15
mA
(driving 100 load)
HiSPi common mode voltage
(driving 100 load)
VCMD
VDD_SLVS x 0.45
VDD_SLVS x 0.36
VDD_SLVS/2
VDD_SLVS/2
VDD_SLVS x 0.55
VDD_SLVS x 0.64
V
V
HiSPi differential output voltage
|VOD|
(driving 100 load)
Change in VCM between logic 1 and 0
VCM
25
25
mV
mV
Change in |VOD| between logic 1 and
0
|VOD|
Vod noise margin
NM
–
30
50
%
Difference in VCM between any two
channels
|VCM|
mV
Difference in VOD between any two
channels
|VOD|
100
50
mV
mV
mV
Common-mode AC voltage (pk)
without VCM cap termination
VCM_ac
VCM_ac
Common-mode AC voltage (pk) with
VCM cap termination
30
Max overshoot peak |VOD|
Max overshoot Vdiff pk-pk
Eye Height
VOD_ac
Vdiff_pkpk
Veye
1.3 x |VOD|
2.6 x |VOD|
V
V
1.4 x VOD
35
Single-ended output impedance
Output impedance mismatch
Ro
50
70
20
Ro
%
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
22
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Figure 8:
Differential Output Voltage for Clock or Data Pairs
VDIFFmax
VDIFFmin
0V Diff)
Output Signal is 'Cp - Cn' or 'Dp - Dn'
Table 16:
Rise and Fall Times
Measurement Conditions: HiSPi Power Supply 0.4V, Max Freq 700 MHz
Parameter
Symbol
1/UI
Min
280
0.3
Typ
Max
700
–
Unit
Mb/s
UI1
Data Rate
–
–
Max setup time from transmitter
Max hold time from transmitter
Rise time (20% - 80%)
Fall time (20% - 80%)
Clock duty
TxPRE
TxPost
RISE
0.3
–
–
UI
–
0.25UI
0.25 UI
50
–
FALL
150ps
45
–
PLL_DUTY
tpw
55
3.57
%
ns1
UI1, 2
UI1, 2
ps2
Bitrate Period
1.43
0.3
Eye Width
teye
Data Total jitter (pk pk)@1e-9
Clock Period Jitter(RMS)
Clock cycle to cycle jitter (RMS)
Clock to Data Skew
PHY-to-PHY Skew
ttotaljit
tckjit
0.2
50
tcyjit
100
0.1
2.1
100
ps2
tchskew
t|PHYskew|
tDIFFSKEW
-0.1
UI1, 2
UI1, 5
ps6
Mean diferential skew
–100
Notes: 1. One UI is defined as the normalized mean time between one edge and the following edge of the
clock.
2. Taken from 0V crossing point w/ DLL off.
3. Also defined with a maximum loading capacitance of 10pF on any pin. The loading capacitance
may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum
0.3UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any
edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY
between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the
absolute time between the two complementary edges at mean VCM point.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
23
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Electrical Specifications
Figure 9:
Eye Diagram for Clock and Data Signals
R I SE
8 0 %
2 0 %
D A T A MA SK
T x Pr e
T x Po s t
FA L L
UI / 2
UI / 2
C L O CK MA SK
T r i g ger/ R eference
C L K JITT ER
Figure 10: Skew Within the PHY and Output Channels
V C MD
tC MPSK EW
tC HSKEW1PHY
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
24
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Power-On Reset and Standby Timing
Power-Up Sequence
The recommended power-up sequence for the MT9M021/MT9M031 is shown in
Figure 11. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,
VAA_PIX) must have the separation specified below.
1. Turn on VDD_PLL power supply.
2. After 0–10s, turn on VAA and VAA_PIX power supply.
3. After 0–10s, turn on VDD_IO power supply.
4. After the last power supply is stable, enable EXTCLK.
5. Assert RESET_BAR for at least 1ms.
6. Wait 150000 EXTCLKs (for internal initialization into software standby.
7. Configure PLL, output, and image settings to desired values.
8. Wait 1ms for the PLL to lock.
9. Set streaming mode (R0x301a[2] = 1).
Figure 11: Power Up
t0
V
DD_PLL (2.8)
AA_PIX
V
t1
V
AA (2.8)
DD_IO (1.8/2.8)
DD (1.8)
t2
V
V
t3
VDD_SLVS (0.4)
EXTCLK
t4
RESET_B
tx
t5
t6
Internal
Initialization
Software
Standby
PLL Lock
Streaming
Hard Reset
Table 17:
Definition
Power-Up Sequence
Symbol
Minimum
Typical
10
10
10
10
301
–
Maximum
Unit
s
VDD_PLL to VAA/VAA_PIX
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
t0
t1
t2
t3
tx
t4
t5
t6
0
–
–
–
–
–
–
–
–
0
s
0
s
VDD to VDD_SLVS
Xtal settle time
0
s
–
12
ms
Hard Reset
ms
Internal Initialization
PLL Lock Time
150000
1
–
EXTCLKs
ms
–
Notes: 1. Xtal settling time is component-dependent, usually taking about 10 – 100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard
reset is held down by RC circuit, then the RC time must include the all power rail settle time and
Xtal settle time.
3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered
before or at least at the same time as the others. If the case happens that VDD_PLL is powered after
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
25
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
other supplies then the sensor may have functionality issues and will experience high current draw
on this supply.
Power-Down Sequence
The recommended power-down sequence for the MT9M021/MT9M031 is shown in
Figure 12. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,
VAA_PIX) must have the separation specified below.
1. Disable streaming if output is active by setting standby R0x301a[2] = 0
2. The soft standby state is reached after the current row or frame, depending on config-
uration, has ended.
3. Turn off VDD_SLVS.
4. Turn off VDD.
5. Turn off VDD_IO
6. Turn off VAA/VAA_PIX.
7. Turn off VDD_PLL.
Figure 12: Power Down
VDD_SLVS (0.4)
t 0
VDD (1.8)
t1
V
DD_IO (1.8/2.8)
t2
VAA_PIX
VAA (2.8)
t3
VDD_PLL (2.8)
EXTCLK
t4
Power Down until next Power up cycle
Table 18:
Power-Down Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_SLVS to VDD
VDD to VDD_IO
t0
t1
t2
t3
0
0
0
0
–
–
–
–
–
–
–
–
S
S
S
S
VDD_IO to VAA/VAA_PIX
VAA/VAA_PIX to VDD_PLL
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
26
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Table 18:
Power-Down Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
PwrDn until Next PwrUp Time
t4
100
–
–
mS
Note:
t4 is required between power down and next power up time; all decoupling caps from regulators
must be completely discharged.
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
27
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Figure 13: Quantum Efficiency – Monochrome Sensor
80
70
60
50
40
30
20
10
0
350
450
550
650
750
850
950
1050
1150
Wavelength (nm)
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
28
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Power-On Reset and Standby Timing
Figure 14: Quantum Efficiency – Color Sensor
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
29
©Semiconductor Components Industries, LLC,2015.
Package Dimensions
Figure 15: 64-Ball iBGA Package Outline Drawing
Note:
All dimensions in millimeters.
Figure 16: 48-pin iLCC Package Drawing
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Revision History
Revision History
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15
Updated “Ordering Information” on page 2
•
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12
•
•
Converted to ON Semiconductor template
Removed Confidential marking
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12
•
•
•
•
•
Updated to Production
Updated Table 1, “Key Parameters,” on page 1
Updated Table 2, “Available Part Numbers,” on page 2
Updated “General Description” on page 8
Updated Figure 2: “Typical Configuration: Serial Four-Lane HiSPi Interface,” on
page 10
•
•
•
•
•
Updated Figure 3: “Typical Configuration: Parallel Pixel Data Interface,” on page 11
Updated Table 5, “Two-Wire Serial Bus Characteristics,” on page 17
Updated Figure 7: “I/O Timing Diagram,” on page 18
Updated Table 6, “I/O Timing Characteristics1,” on page 18
Added Table 7, I/O Rise Slew Rate (2.8V Vdd_IO)1 and
Table 8, “I/O Fall Slew Rate (2.8V Vdd_IO)1,” on page 20
•
Added Table 9, I/O Rise Slew Rate (1.8V Vdd_IO)1 and
Table 10, “I/O Fall Slew Rate (1.8V Vdd_IO)1,” on page 20
•
•
Updated Table 13, “Operating Current Consumption for Parallel Output,” on page 21
Updated Table 14, “Standby Current Consumption,” on page 22
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/17/12
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added MT9M031
Updated Table 1, “Key Parameters,” on page 1
Updated Table 2, “Available Part Numbers,” on page 2
Updated “LV Format Options” on page 14
Updated “HiSPi Physical Layer” on page 15
Added Figure 5: “48 iLCC Package, Parallel Output,” on page 14
Added Table 4, “Pin Descriptions - 48 iLCC Package, Parallel,” on page 15
Updated Figure 7: “I/O Timing Diagram,” on page 18
Updated Table 6, “I/O Timing Characteristics1,” on page 18
Updated “HiSPi Electrical Specifications” on page 22
Added Table 15, “Input Voltage and Current (HiSPi Power Supply 0.4 V),” on page 22
Added Figure 8: “Differential Output Voltage for Clock or Data Pairs,” on page 23
Added Table 16, “Rise and Fall Times,” on page 23
Added Figure 9: “Eye Diagram for Clock and Data Signals,” on page 24
Added Figure 10: “Skew Within the PHY and Output Channels,” on page 24
Added Figure 16: “48-pin iLCC Package Drawing,” on page 31
Deleted the following major sections and their sub-sections. Refer to the Developer
Guide:
– Pixel Data Format
– Output Data Format
– Two-Wire Serial Register Interface
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
32
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Revision History
– Real-Time Context Switching
•
Replaced “Feature Description” with “Functional Overview” on page 8 and “Features
Overview” on page 9
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/14/11
•
•
Updated to Preliminary
Updated operating temperature in Table 1, “Key Parameters,” on page 1 and in
“General Description” on page 8
•
•
•
•
•
•
Updated Figure 6: “Two-Wire Serial Bus Timing Parameters,” on page 16
Updated Table 5, “Two-Wire Serial Bus Characteristics,” on page 17
Updated Figure 7: “I/O Timing Diagram,” on page 18
Added Table 6, “I/O Timing Characteristics1,” on page 18
Updated Table 6, “DC Electrical Characteristics,” on page 14
Replaced Table 10, Power Consumption with Table 13, “Operating Current Consump-
tion for Parallel Output,” on page 21
•
•
•
•
•
•
•
Added Table 14, “Standby Current Consumption,” on page 22
Updated Table 14, Power Supply and Operating Temperatures
Deleted Table 14, “Input Voltage and Current,” on page 39
Added Table 15, “SLVS Electrical DC Specification,” on page 40
Updated Table 16, “SLVS Electrical Timing Specification,” on page 40
Updated Table 17, “Power-Up Sequence,” on page 25
Updated Figure 13: “Quantum Efficiency – Monochrome Sensor,” on page 28
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/16/09
•
Updated the following parameters in Table 1, “Key Parameters,” on page 1
– input clock range
– responsivity
– dynamic range
•
•
Updated Table 2, “Available Part Numbers,” on page 2
Replaced “scaling” with “digital binning” in third paragraph of “General Description”
on page 8
•
•
Updated master clock range in Figure 2 on page 10 and Figure 3 on page 11
Updated number of rows in first sentence of first paragraph in “Pixel Array Structure”
on page 10
•
•
•
•
•
Updated array pixel coordinates in Figure 6 on page 12
Added “Default Readout Order” on page 12
Updated “Output Data Format” on page 13
Added “Readout Sequence” on page 13
Replaced “Parallel Data Timing” section with “Parallel Output Data Timing” on
page 14
•
Moved Figure 13, Line Timing and FRAME_VALID/LINE_VALID Signals and Table 5,
Frame Time: Long Integration Time to new section “Frame Time” on page 17; added
Table 4, “Frame Time (Example Based on 1280 x 960, 45 Frames Per Second),” on
page 17
•
•
•
Updated first paragraph of “Real-Time Context Switching” on page 19
Updated Table 6, “Real-Time Context-Switchable Registers,” on page 19
Updated “Features” section as follows:
– Updated “Trigger Mode” on page 20
– Moved “Hard Reset of Logic” and Soft Reset of Logic” to “Reset” on page 21
MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
33
©Semiconductor Components Industries, LLC,2015.
MT9M021/MT9M031: 1/3-Inch CMOS Digital Image Sensor
Revision History
– Added “Readout Modes” on page 25; “Mirror” on page 27, “Maintaining a Constant
Frame Rate” on page 28, “Synchronizing Register Writes to Frame Boundaries” on
page 28; “Restart” on page 29, “Automatic Exposure Control” on page 29,and “Test
Patterns” on page 32
– Deleted “Pixel Integration Control,” “Pixel Clock Speed,” “Statistics and Settings
Readout,” “Read Mode Options,” and “Line_Valid”
•
•
Updated “Electrical Specifications” on page 16
Moved “Power-On Reset and Standby Timing” on page 25 from appendix to main
body of document
•
•
Replaced Figure 13: “Quantum Efficiency – Monochrome Sensor,” on page 28 with
placeholder
Updated Figure 15: “64-Ball iBGA Package Outline Drawing,” on page 30
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/18/09
Initial release
•
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without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
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MT9M021-MT9M031_DS Rev. G Pub. 4/15 EN
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