MT9V032C12STCH-GEVB_技术文档

MT9V032

MT9V032 1/3‐Inch Wide

VGA CMOS Digital Image

Sensor

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Table 1. KEY PERFORMANCE PARAMETERS

Parameter

Optical Format

Value

1/3-inch

Active Imager Size

4.51 mm (H) × 2.88 mm (V)

5.35 mm diagonal

Active Pixels

Pixel Size

752H × 480 V

6.0 mm × 6.0 mm

CLCC48 11.43 × 11.43

Color Filter Array

Monochrome or color RGB Bayer

Pattern

CASE 848AQ

Shutter Type

Global Shutter

Maximum Data Rate Master Clock

Full Resolution

26.6 MPS/26.6 MHz

752 x 480

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

Frame Rate

60 fps (at full resolution)

10−bit column−parallel

4.8 V/lux−sec (550 nm)

ADC Resolution

Responsivity

Dynamic Range

>55 dB;

• Support For Four Unique Serial Control

Register IDs To Control Multiple Imagers

On The Same Bus

>80 dB−100dB in HDR mode

Supply Voltage

3.3 V 0.3 V (all supplies)

Power Consumption

<320 mW at maximum data rate;

100 mW standby Power

• Data Output Formats:

• Single Sensor Mode:

Operating Temperature

Packaging

−30°C to + 70°C

48−Pin CLCC

10−bit Parallel/Stand−Alone

8−bit Or 10−bit Serial LVDS

• Stereo Sensor Mode:

Features

Interspersed 8−bit Serial LVDS

• Array Format: Wide−VGA, Active 752H x 480V (360,960 Pixels)

Applications

• Security

• Global Shutter Photodiode Pixels; Simultaneous Integration And

Readout

• High Dynamic Range Imaging

• Unattended Surveillance

• Stereo Vision

• Video As Input

• Machine Vision

• Automation

• Monochrome Or Color: Near_IR Enhanced Performance For Use

With Non−Visible NIR Illumination

• Readout Modes: Progressive Or Interlaced

• Shutter Efficiency: >99%

• Simple Two−Wire Serial Interface

• Register Lock Capability

• Window Size: User Programmable To Any Smaller Format (QVGA,

CIF, QCIF, etc.). Data Rate Can Be Maintained Independent Of

Window Size

• Binning: 2 x 2 And 4 x 4 Of The Full Resolution

• ADC: On−Chip, 10−bit Column−Parallel (Option To Operate In

12−bit To 10−bit Companding Mode)

• Automatic Controls: Auto Exposure Control (AEC) And Auto Gain

Control (AGC); Variable Regional And Variable Weight AEC/AGC

1

Publication Order Number:

May, 2017 − Rev. 7

MT9V032/D

MT9V032

Table of Contents

Ordering Information

General Description

Pixel Data Format

3

4

8

Color Device Limitations

Output Data Format

Serial Bus Description

Two−Wire Serial Interface Sample Read and Write Sequences

Registers

Feature Description

On−Chip Biases

Window Control

Blanking Control

Pixel Integration Control

Gain settings

Read Mode Options

Electrical Specifications

Temperature Reference

Appendix A − Serial Configurations

Appendix B − Power−On Reset and Standby Timing

9

10

12

14

16

31

34

35

36

37

40

45

50

55

57

60

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MT9V032

ORDERING INFORMATION

Table 2. AVAILABLE PART NUMBERS

Part Number

Product Description

Orderable Product Attribute Description †

MT9V032C12STCD3−GEVK

MT9V032C12STCD−GEVK

MT9V032C12STC−DP

48−pin CLCC demo3 kit (color)

48−pin CLCC demo kit (color)

48−pin CLCC (color)

Dry Pack with Protective Film

MT9V032C12STC−DR

MT9V032C12STCH−GEVB

MT9V032C12STC−TP

48−pin CLCC (color)

Dry Pack without Protective Film

48−pin CLCC headboard only (color)

48−pin CLCC (color)

Tape & Reel with Protective Film

MT9V032C12STMD−GEVK

MT9V032C12STM−DP

MT9V032C12STM−DR

MT9V032C12STMH−GEVB

MT9V032C12STM−TP

48−pin CLCC demo kit (mono)

48−pin CLCC (mono)

Dry Pack with Protective Film

48−pin CLCC (mono)

Dry Pack without Protective Film

48−pin CLCC headboard only (mono)

48−pin CLCC (mono)

Tape & Reel with Protective Film

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

See the ON Semiconductor Device Nomenclature

document (TND310/D) for a full description of the naming

convention used for image sensors. For reference

documentation, including information on evaluation kits,

please visit our web site at www.onsemi.com.

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3

MT9V032

GENERAL DESCRIPTION

The ON Semiconductor MT9V032 is a 1/3−inch

wide−VGA format CMOS active−pixel digital image sensor

with global shutter and high dynamic range (HDR)

operation. The sensor has specifically been designed to

support the demanding interior and exterior surveillance

imaging needs, which makes this part ideal for a wide

variety of imaging applications in real−world environments.

This wide−VGA CMOS image sensor features ON

Semiconductor’s breakthrough low−noise CMOS imaging

technology that achieves CCD image quality (based on

signal−to−noise ratio and low−light sensitivity) while

maintaining the inherent size, cost, and integration

advantages of CMOS.

column and row mirroring. It is programmable through a

simple two−wire serial interface.

The MT9V032 can be operated in its default mode or be

programmed for frame size, exposure, gain setting, and

other parameters. The default mode outputs

a

wide−VGA−size image at 60 frames per second (fps).

An on−chip analog−to−digital converter (ADC) provides

10 bits per pixel. A 12−bit resolution companded for 10 bits

for small signals can be alternatively enabled, allowing more

accurate digitization for darker areas in the image.

In addition to a traditional, parallel logic output the

MT9V032 also features a serial low−voltage differential

signaling (LVDS) output. The sensor can be operated in a

The active imaging pixel array is 752H x 480V. It

incorporates sophisticated camera functions on−chip—such

as binning 2 x 2 and 4 x 4, to improve sensitivity when

operating in smaller resolutions—as well as windowing,

stereo−camera, and the sensor, designated as

stereo−master, is able to merge the data from itself and the

stereo−slave sensor into one serial LVDS stream.

a

Serial

Register

I/O

Control Register

Active−Pixel

Sensor (APS)

Array

Timing and Control

Digital Processing

752H x 480 V

Analog Processing

ADCs

Parallel

Video

Data Out

Serial Video

LVDS Out

Slave Video LVDS in

(for stereo applications only)

Figure 1. Block Diagram

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4

MT9V032

6

5

4

3

2

1

48

47

46

45

44

43

42

LVDSGND

BYPASS_CLKIN_N

BYPASS_CLKIN_P

SER_DATAIN_N

SER_DATAIN_P

LVDSGND

7

8

D

3

4

OUT

41

40

39

38

OUT

VAAPIX

9

10

11

V

AA

A

GND

37

36

35

34

33

12

13

14

NC

D

GND

V

DD

V

AA

A

GND

D

5

6

15

16

17

18

OUT

STANDBY

OUT

32

31

D

7

8

RESET#

OUT

S_CTRL_ADR1

OUT

19

20

21

22

23

24

25

26

27

28

29

30

Figure 2. 48-Pin CLCC Pinout Diagram

Table 3. PIN DESCRIPTIONS (Only pins DOUT0 through DOUT9 may be tri−stated)

48−Pin LLCC

Numbers

Symbol

Type

Input

Descriptions

Note

29

10

RSVD

Connect to DGND.

1

SER_DATAIN_N

SER_DATAIN_P

BYPASS_CLKIN_N

BYPASS_CLKIN_P

Serial data in for stereoscopy (differential negative). Tie to 1kW pull−

up (to 3.3V) in non−stereoscopy mode.

11

8

Input

Serial data in for stereoscopy (differential positive). Tie to DGND in

non−stereoscopy mode.

Input bypass shift−CLK (differential negative). Tie to 1KW pull−up (to

3.3V) in non−stereoscopy mode.

9

Input bypass shift−CLK (differential positive). Tie to DGND in non−

stereoscopy mode.

23

25

EXPOSURE

SCLK

Input

Rising edge starts exposure in slave mode.

Two−wire serial interface clock. Connect to VDD with 1.5K resistor

even when no other two−wire serial interface peripheral is attached.

28

30

31

32

33

OE

Input

DOUT enable pad, active HIGH.

2

S_CTRL_ADR0

S_CTRL_ADR1

RESET#

Two−wire serial interface slave address bit 3.

Two−wire serial interface slave address bit 5.

Asynchronous reset. All registers assume defaults.

Shut down sensor operation for power saving.

STANDBY

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MT9V032

Table 3. PIN DESCRIPTIONS (Only pins DOUT0 through DOUT9 may be tri−stated)

48−Pin LLCC

Numbers

Symbol

Type

Input

I/O

Descriptions

Note

47

24

SYSCLK

Master clock (26.6 MHz).

SDATA

Two−wire serial interface data. Connect to VDD with 1.5K resistor

even when no other two−wire serial interface peripheral is attached.

22

26

STLN_OUT

I/O

Output in master mode—start line sync to drive slave chip in−

phase; input in slave mode.

STFRM_OUT

Output in master mode—start frame sync to drive a slave chip in−

phase; input in slave mode.

20

21

LINE_VALID

FRAME_VALID

DOUT5

Output

Supply

Ground

NC

Asserted when DOUT data is valid.

Parallel pixel data output 5.

Parallel pixel data output 6.

Parallel pixel data output 7.

Parallel pixel data output 8

Parallel pixel data output 9.

LED strobe output.

15

16

DOUT6

17

DOUT7

18

DOUT8

19

DOUT9

27

LED_OUT

DOUT4

41

Parallel pixel data output 4.

Parallel pixel data output 3.

Parallel pixel data output 2.

Parallel pixel data output 1.

Parallel pixel data output 0.

Pixel clock out. DOUT is valid on rising edge of this clock.

Output shift CLK (differential negative).

Output shift CLK (differential positive).

Serial data out (differential negative).

Serial data out (differential positive).

Digital power 3.3V.

42

DOUT3

43

DOUT2

44

DOUT1

45

DOUT0

46

PIXCLK

2

SHFT_CLKOUT_N

SHFT_CLKOUT_P

SER_DATAOUT_N

SER_DATAOUT_P

VDD

3

4

5

1, 14

35, 39

40

VAA

Analog power 3.3V.

VAAPIX

Pixel power 3.3V.

6

VDDLVDS

LVDSGND

DGND

Dedicated power for LVDS pads.

Dedicated GND for LVDS pads.

Digital GND.

7, 12

13, 48

34, 38

36, 37

AGND

Analog GND.

NC

No connect.

3

1. Pin 29 (RSVD) must be tied to GND

2. Output Enable (OE) tri−states signals DOUT0–DOUT9. No other signals are tri−stated with OE.

3. No connect. These pins must be left floating for proper operation.

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MT9V032

V

VAAPIX

DD

AA

V

AA

V

DD

LVDS V

DD

D

(9:0

OUT

(9:0)

OUT

Master Clock

D

SYSCLK

OE

)

LINE_VALID

To Controller

RESET#

EXPOSURE

STANDBY

S_CTRL_ADR0

S_CTRL_ADR1

FRAME_VALID

PIXCLK

STANDBY from

Controller or

Digital GND

LED_OUT

ERROR

To LED Output

Two−Wire

Serial Interface

SCLK

SDATA

RSVD

D

LVDSGND

A

GND

0.1mF

NOTE: LVDS signals are to be left floating.

Figure 3. Typical Configuration (Connection)−Parallel Output Mode

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MT9V032

PIXEL DATA FORMAT

Pixel Array Structure

The MT9V032 pixel array is configured as 782 columns

by 492 rows, shown in Figure 4. The left 26 columns and the

top eight rows of pixels are optically black and can be used

to monitor the black level. The black row data is used

internally for the automatic black level adjustment.

However, the middle four black rows can also be read out by

setting the sensor to raw data output mode. There are 753

columns by 481 rows of optically active pixels. The active

area is surrounded with optically transparent dummy

columns and rows to improve image uniformity within the

active area. One additional active column and active row are

used to allow horizontally and vertically mirrored readout to

also start on the same color pixel.

8 dark, 1 light dummy rows

(0.0)

26 dark, 1 light

dummy columns

2 dummy

columns

(782,492)

2 dummy rows

Figure 4. Pixel Array Description

Column Readout Direction

.

Pixel

(2,9)

G

R

G

R

G

R

B

G

B

G

B

G

R

G

R

G

R

B

G

B

G

B

G

R

G

R

G

R

B

G

B

G

B

G

R

G

R

G

R

B

G

B

G

B

G

Row

Readout

Direction

.

Figure 5. Pixel Color Pattern Detail (Top Right Corner)

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MT9V032

COLOR DEVICE LIMITATIONS

Automatic Black Level Calibration

The color version of the MT9V032 does not support or

offers reduced performance for the following

functionalities.

When the color bit is set (R0x0F[2]=1), the sensor uses

GREEN1 pixels black level correction value, which is

applied to all colors. To use calibration value based on all

dark pixels offset values, the color bit should be cleared.

Pixel Binning

Pixel binning is done on immediate neighbor pixels only;

no facility is provided to skip pixels according to a Bayer

pattern. Therefore, the result of binning combines pixels of

different colors. For more information, see “Pixel Binning”.

Other Limiting Factors

Black level correction and row−wise noise correction are

applied uniformly to each color. Automatic exposure and

gain control calculations are made based on all three colors,

not just the green luma channel. High dynamic range does

operate; however, ON Semiconductor strongly recommends

limiting use to linear operation if good color fidelity is

required.

Interlaced Readout

Interlaced readout yields one field consisting only of red

and green pixels and another consisting only of blue and

green pixels. This is due to the Bayer pattern of the CFA.

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MT9V032

OUTPUT DATA FORMAT

The MT9V032 image data can be read out in a progressive

scan or interlaced scan mode. Valid image data is surrounded

by horizontal and vertical blanking, as shown in Figure 6.

The amount of horizontal and vertical blanking is

programmable through R0x05 and R0x06, respectively.

LINE_VALID is HIGH during the shaded region of the

figure. See “Output Data Timing” for the description of

FRAME_VALID timing.

P

…………P

P

0,n−1 0,n

00 00 00 ………… 00 00 00

0,0 0,1 0,2

P

…………P P

1,n−1 1,n

1,0 1,1 1,2

HORIZONTAL

BLANKING

VALID iMAGE

P

…………P

P

00 00 00 ………… 00 00 00

m−1,0 m−1,1

m−1,n−1 m−1,n

P

…………P

P

m,0 m,1

m,n−1 m,n

00 00 00 ………… 00 00 00

VERTICAL/HORIZONTAL

BLANKING

VERTICAL BLANKING

00 00 00 ………… 00 00 00

Figure 6. Spatial Illustration of Image Readout

Output Data Timing

The data output of the MT9V032 is synchronized with the

PIXCLK output. When LINE_VALID is HIGH, one 10−bit

pixel datum is output every PIXCLK period.

…

LINE_VALID

…

PIXCLK

Blanking

Valide Image Data

Blanking

P

n

(9:0)

P

4

…

D

(9:0)

OUT

n−1

0

1

2

3

(9:0)

Figure 7. Timing Example of Pixel Data

The PIXCLK is a nominally inverted version of the master

clock (SYSCLK). This allows PIXCLK to be used as a clock

to latch the data. However, when column bin 2 is enabled, the

PIXCLK is HIGH for one complete master clock master

period and then LOW for one complete master clock period;

when column bin 4 is enabled, the PIXCLK is HIGH for two

complete master clock periods and then LOW for two

complete master clock periods. It is continuously enabled,

even during the blanking period. Setting R0x74 bit[4] = 1

causes the MT9V032 to invert the polarity of the PIXCLK.

The parameters P1, A, Q, and P2 in Figure 8 are defined

in Table 4.

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MT9V032

...

FRAME_VALID

LINE_VALID

...

P1

A

Q

A

Q

A

P2

Number of master clocks

Figure 8. Row Timing and FRAME_VALID/LINE_VALID Signals

Table 4. FRAME TIME − LARGER THAN ONE FRAME

Parameter

Name

Equation

Default Timing at 26.66 MHz

752 pixel clocks

= 752 master = 28.20ms

A

Active data time

R0x04

71 pixel clocks

P1

Frame start blanking

Frame end blanking

Horizontal blanking

Row time

R0x05 − 23

23 (fixed)

= 71master = 2.66ms

23 pixel clocks

= 23 master = 0.86ms

P2

94 pixel clocks

= 94 master = 3.52ms

Q

R0x05

846 pixel clocks

= 846 master = 31.72ms

A+Q

R0x04 + R0x05

(R0x06) x (A + Q) + 4

(R0x03) × (A + Q)

V + (Nrows x (A + Q))

38,074 pixel clocks

= 38,074 master = 1.43ms

V

Vertical blanking

Frame valid time

Total frame time

406,080 pixel clocks

= 406,080 master = 15.23ms

Nrows x (A + Q)

F

444,154 pixel clocks

= 444,154 master = 16.66ms

Sensor timing is shown above in terms of pixel clock and

master clock cycles (refer to Figure 7). The recommended

master clock frequency is 26.66 MHz. The vertical blanking

and total frame time equations assume that the number of

integration rows (bits 11 through 0 of R0x0B) is less than the

number of active rows plus blanking rows minus overhead

rows (R0x03 + R0x06 − 2). If this is not the case, the number

of integration rows must be used instead to determine the

frame time, as shown in Table 5. In this example it is

assumed that R0x0B is programmed with 523 rows. For

Simultaneous Mode, if the exposure time register (0x0B)

exceeds the total readout time, then vertical blanking is

internally extended automatically to adjust for the additional

integration exposure time required. This extended value is

not written back to R0x06 (vertical blanking). R0x06 can be

used to adjust frame to frame readout time. This register

does not affect the exposure time but it may extend the

readout time.

Table 5. FRAME TIME − LONG INTEGRATION TIME

Equation

(Number of Master Clock Cycles)

Parameter

Name

Default Timing at 26.66 MHz

Vertical blanking (long integration

time)

38,074 pixel clocks

= 38,074 master = 1.43ms

V’

(R0x0B + 2 − R0x03) × (A + Q) + 4

Total frame time (long integration

exposure time)

444,154 pixel clocks

= 444,154 master = 16.66ms

F”

(R0x0B + 2) × (A + Q) + 4

4. The MT9V032 uses column parallel analog−to−digital converters, thus short row timing is not possible. The minimum total row time is 660

columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 43. When the window width is set below 617, horizontal

blanking must be increased. The frame rate will not increase for row times less than 660 columns.

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MT9V032

SERIAL BUS DESCRIPTION

Registers are written to and read from the MT9V032

through the two−wire serial interface bus. The MT9V032 is

a serial interface slave with four possible IDs (0x90, 0x98,

0xB0,and 0xB8) determined by the S_CTRL_ADR0 and

S_CTRL_ADR1 input pins. Data is transferred into the

MT9V032 and out through the serial data (SDATA) line. The

SDATA line is pulled up to VDD off−chip by a 1.5KW resistor.

Either the slave or master device can pull the SDATA line

down—the serial interface protocol determines which

device is allowed to pull the SDATA line down at any given

time. The registers are 16−bit wide, and can be accessed

through 16− or 8−bit two−wire serial interface sequences.

Protocol

The two−wire serial interface defines several different

transmission codes, as follows:

• a start bit

• the slave device 8−bit address

• a(n) (no) acknowledge bit

• an 8−bit message

• a stop bit

Sequence

A typical read or write sequence begins by the master

sending a start bit. After the start bit, the master sends the

slave device’s 8−bit address. The last bit of the address

determines if the request is a read or a write, where a “0”

indicates a write and a “1” indicates a read. The slave device

acknowledges its address by sending an acknowledge bit

back to the master.

If the request was a write, the master then transfers the

8−bit register address to which a write should take place. The

slave sends an acknowledge bit to indicate that the register

address has been received. The master then transfers the data

8 bits at a time, with the slave sending an acknowledge bit

after each 8 bits. The MT9V032 uses 16−bit data for its

internal registers, thus requiring two 8−bit transfers to write

to one register. After 16 bits are transferred, the register

address is automatically incremented, so that the next 16 bits

are written to the next register address. The master stops

writing by sending a start or stop bit.

sends a no−acknowledge bit. The MT9V032 allows for 8−bit

data transfers through the two−wire serial interface by

writing (or reading) the most significant 8 bits to the register

and then writing (or reading) the least significant 8 bits to

R0xF0 (240).

Bus Idle State

The bus is idle when both the data and clock lines are

HIGH. Control of the bus is initiated with a start bit, and the

bus is released with a stop bit. Only the master can generate

the start and stop bits.

Start Bit

The start bit is defined as a HIGH−to−LOW transition of

the data line while the clock line is HIGH.

Stop Bit

The stop bit is defined as a LOW−to−HIGH transition of

the data line while the clock line is HIGH.

A typical read sequence is executed as follows. First the

master sends the write mode slave address and 8−bit register

address, just as in the write request. The master then sends

a start bit and the read mode slave address. The master then

clocks out the register data 8 bits at a time. The master sends

an acknowledge bit after each 8−bit transfer. The register

address is auto−incremented after every 16 bits is

transferred. The data transfer is stopped when the master

Slave Address

The 8−bit address of a two−wire serial interface device

consists of 7 bits of address and 1 bit of direction. A “0” in

the LSB of the address indicates write mode, and a “1”

indicates read mode. As indicated above, the MT9V032

allows four possible slave addresses determined by the two

input pins, S_CTRL_ADR0 and S_CTRL_ADR1.

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12

MT9V032

Table 6. SLAVE ADDRESS MODES

{S_CTRL_ADR1, S_CTRL_ADR0}

Slave Address

Write/Read Mode

00

0x90

0x91

0x98

0x99

0xB0

0xB1

0xB8

0xB9

Write

Read

Write

Read

Write

Read

Write

Read

01

10

11

Data Bit Transfer

when reading) releases the data line, and the receiver

indicates an acknowledge bit by pulling the data line LOW

during the acknowledge clock pulse.

One data bit is transferred during each clock pulse. The

two−wire serial interface clock pulse is provided by the

master. The data must be stable during the HIGH period of

the serial clock—it can only change when the two−wire

serial interface clock is LOW. Data is transferred 8 bits at a

time, followed by an acknowledge bit.

No−Acknowledge Bit

The no−acknowledge bit is generated when the data line

is not pulled down by the receiver during the acknowledge

clock pulse. A no−acknowledge bit is used to terminate a

read sequence.

Acknowledge Bit

The master generates the acknowledge clock pulse. The

transmitter (which is the master when writing, or the slave

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13

MT9V032

TWO−WIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES

16−Bit Write Sequence

A typical write sequence for writing 16 bits to a register

is shown in Figure 9. A start bit given by the master, followed

by the write address, starts the sequence. The image sensor

then gives an acknowledge bit and expects the register

address to come first, followed by the 16−bit data. After each

8−bit word is sent, the image sensor gives an acknowledge

bit. All 16 bits must be written before the register is updated.

After 16 bits are transferred, the register address is

automatically incremented, so that the next 16 bits are

written to the next register. The master stops writing by

sending a start or stop bit.

SCLK

S

DATA

0xB8 ADDR

START

R0x09

0000 0010

1000 0100

STOP

ACK

Figure 9. Timing Diagram Showing a Write to R0x09 with Value 0x0284

16−Bit Read Sequence

clocks out the register data 8 bits at a time. The master sends

an acknowledge bit after each 8−bit transfer. The register

address is auto−incremented after every 16 bits is

transferred. The data transfer is stopped when the master

sends a no−acknowledge bit.

A typical read sequence is shown in Figure 10. First the

master has to write the register address, as in a write

sequence. Then a start bit and the read address specify that

a read is about to happen from the register. The master then

SCLK

S

DATA

0xB8 ADDR

START

R0x09

0xB9 ADDR

0000 0010

1000 0100

STOP

NACK

ACK

Figure 10. Timing Diagram Showing a Read from R0x09; Returned Value 0x0284

8−Bit Write Sequence

To be able to write 1 byte at a time to the register, a special

register address is added. The 8−bit write is done by first

writing the upper 8 bits to the desired register and then

writing the lower 8 bits to the special register address

(R0xF0). The register is not updated until all 16 bits have

been written. It is not possible to just update half of a register.

In Figure 11, a typical sequence for 8−bit writing is shown.

The second byte is written to the special register (R0xF0).

SCLK

0000 0010

ACK

1000 0100

0xB8 ADDR

R0x09

0xB8 ADDR

START

R0xF0

S

DATA

STOP

START

ACK

Figure 11. Timing Diagram Showing a Bytewise Write to R0x09 with Value 0x0284

8−Bit Read Sequence

To read one byte at a time the same special register address

is used for the lower byte. The upper 8 bits are read from the

desired register. By following this with a read from the

special register (R0xF1) the lower 8 bits are accessed

(Figure 12). The master sets the no−acknowledge bits

shown.

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14

MT9V032

SCLK

S

DATA

0xB8 ADDR

0xB9 ADDR

0000 0010

R0x09

START

ACK

START

ACK

NACK

SCLK

S

DATA

0xB8 ADDR

0xB9 ADDR

1000 0100

R0xF0

STOP

START

ACK

START

ACK

NACK

Figure 12. Timing Diagram Showing a Bytewise Read from R0x09; Returned Value 0x0284

Register Lock

Included in the MT9V032 is a register lock (R0xFE)

feature that can be used as a solution to reduce the

probability of an inadvertent noise−triggered two−wire

serial interface write to the sensor. All registers (or read

mode register—register 13 only) can be locked.

At power−up, the register lock defaults to a value of

0xBEEF, which implies that all registers are unlocked and

any two−wire serial interface writes to the register get

committed.

(except R0xFE) are NOT committed. Alternatively, if the

user writes a 0xBEEF to the register lock register, all

registers are unlocked and any subsequent two−wire serial

interface writes to the register are committed.

Lock Read More Register Only (R0x0D)

If a unique pattern (0xDEAF) to R0xFE is programmed,

any subsequent two−wire serial interface writes to register

13 are NOT committed. Alternatively, if the user writes a

0xBEEF to register lock register, register 13 is unlocked and

any subsequent two−wire serial interface writes to this

register are committed.

Lock All Registers

If a unique pattern (0xDEAD) to R0xFE is programmed,

any subsequent two−wire serial interface writes to registers

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15

MT9V032

REGISTERS

CAUTION: Writing and changing the value of a

reserved register (word or bit) puts the

device in an unknown state and may

damage the device.

Table 7 provides default register descriptions of the

registers.

Table 8 provides detailed descriptions of the registers.

Table 7. DEFAULT REGISTER DESCRIPTIONS (1 = always 1;0 = always; d = programmable; ? = read only)

Register # (Hex)

0x00

Description

Data Format (Binary)

Default Value (Hex)

Chip Version

0001 0011 0001 00001 (LSB)

Iter. 1: 0x1311

Iter. 2: 0x1311

Iter. 3: 0x1313

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

Column Start

Row Start

0000 00dd dddd dddd

0x0001

0x0004

0x01E0

0x02F0

0x005E

0x002D

0x0388

0x01BB

0x01D9

0x0164

0x01E0

0x0000

0x0300

0x0000

0x0011

0x0040

0x8042

0x0022

0x2D32

0x0E02

0x7F32

0x2802

0x3E38

0x2802

0x0428

0x0000

0x0002

0x0000

0x01D1

0x0020

0x0010

0000 000d dddd dddd

Window Height

Window Width

0000 000d dddd dddd

0000 00dd dddd dddd

Horizontal Blanking

Vertical Blanking

Chip Control

Shutter Width 1

Shutter Width 2

Shutter Width Ctrl

Total Shutter Width

Reset

0000 00dd dddd dddd

0ddd dddd dddd dddd

0000 dddd dddd dddd

0ddd dddd dddd dddd

0000 00dd dddd dddd

0ddd dddd dddd dddd

0000 0000 0000 00dd

Read Mode

Monitor Mode

Pixel Operation Mode

Reserved

0000 0011 dddd dddd

0000 0000 0000 000d

0000 0000 dddd dddd

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

LED_OUT Ctrl

ADC Mode Control

Reserved

0000 0000 0000 00dd

–

Reserved

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16

MT9V032

Table 7. DEFAULT REGISTER DESCRIPTIONS (continued)(1 = always 1;0 = always; d = programmable; ? = read only)

Register # (Hex)

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x42

0x46

0x47

0x48

0x4C

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x70

0x71

0x72

Description

Data Format (Binary)

Default Value (Hex)

0x0010

Reserved

–

0x0020

0x0010

0x0020

0x0004

0x0840

0x0004

0x0007

0x0004

0x0003

0x001D

0x0018

0x0015

0x0004

0x0010

0x0040

0x0000

RO

–

VREF_ADC Control

Reserved

0000 0000 0000 0ddd

–

Reserved

–

Reserved

–

Reserved

–

V1

0000 0000 000d dddd

V2

0000 0000 000d dddd

V3

0000 0000 000d dddd

V4

0000 0000 000d dddd

Analog Gain

Max Analog Gain

Reserved

0000 0000 0ddd dddd

–

Reserved

–

Frame Dark Average

Dark Avg Thresholds

BL Calib Control

BL Calibration Value

BL Calib Step Size

Reserved

0000 0000 ???? ????

dddd dddd dddd dddd

0x231D

0x8080

0x0000

0x0002

0x0000

RO

1000 0000 ddd0 000d

0000 0000 dddd dddd

0000 0000 000d dddd

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

RO

Reserved

–

RO

Reserved

–

RO

Reserved

–

0x0000

0x0034

0x0000

0x002A

Row Noise Corr Ctrl 1

Reserved

0000 d000 00d1 dddd

–

Row Noise Constant

0000 0000 dddd dddd

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17

MT9V032

Table 7. DEFAULT REGISTER DESCRIPTIONS (continued)(1 = always 1;0 = always; d = programmable; ? = read only)

Register # (Hex)

0x73

0x74

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0XA5

0xA6

Description

Row Noise Corr Ctrl 2

Data Format (Binary)

0000 00dd dddd dddd

0000 0000 000d dddd

0ddd ddd dddd dddd

0000 0000 dddd dddd

0000 00dd dddd dddd

0000 000d dddd dddd

0000 0000 00dd dddd

0000 0000 0000 dddd

Default Value (Hex)

0x02F7

Pixclk, FV, LV

0x0000

0x00F4

0x0000

0x0096

0x012C

0x01C2

0x0258

0x02F0

0x0000

0x0060

0x00C0

0x0120

0x0180

0x01E0

0x003A

0x0002

Digital Test Pattern

Tile Weight/Gain X0_Y0

Tile Weight/Gain X1_Y0

Tile Weight/Gain X2_Y0

Tile Weight/Gain X3_Y0

Tile Weight/Gain X4_Y0

Tile Weight/Gain X0_Y1

Tile Weight/Gain X1_Y1

Tile Weight/Gain X2_Y1

Tile Weight/Gain X3_Y1

Tile Weight/Gain X4_Y1

Tile Weight/Gain X0_Y2

Tile Weight/Gain X1_Y2

Tile Weight/Gain X2_Y2

Tile Weight/Gain X3_Y2

Tile Weight/Gain X4_Y2

Tile Weight/Gain X0_Y3

Tile Weight/Gain X1_Y3

Tile Weight/Gain X2_Y3

Tile Weight/Gain X3_Y3

Tile Weight/Gain X4_Y3

Tile Weight/Gain X0_Y4

Tile Weight/Gain X1_Y4

Tile Weight/Gain X2_Y4

Tile Weight/Gain X3_Y4

Tile Weight/Gain X4_Y4

Tile Coord. X 0/5

Tile Coord. X 1/5

Tile Coord. X 2/5

Tile Coord. X 3/5

Tile Coord. X 4/5

Tile Coord. X 5/5

Tile Coord. Y 0/5

Tile Coord. Y 1/5

Tile Coord. Y 2/5

Tile Coord. Y 3/5

Tile Coord. Y 4/5

Tile Coord. Y 5/5

AEC/AGC Desired Bin

AEC Update Frequency

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18

MT9V032

Table 7. DEFAULT REGISTER DESCRIPTIONS (continued)(1 = always 1;0 = always; d = programmable; ? = read only)

Register # (Hex)

0xA7

0xA8

0xA9

0xAA

0xAB

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0XBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xF0

Description

Data Format (Binary)

–

Default Value (Hex)

0x0000

Reserved

AEC LPF

0000 0000 0000 00dd

0000 0000 0000 dddd

–

0x0000

0x0002

0x0000

0x0002

0x0003

0xABE0

0x0002

0x0010

0x0000

RO

AGC Update Frequency

Reserved

AGC LPF

0000 0000 0000 00dd

dddd dddd dddd dddd

0000 0000 0000 dddd

0000 0000 000d 0ddd

0000 0000 0000 00dd

0000 0000 0000 000d

0000 0000 0000 0ddd

0000 0000 0000 000?

???? ???? ???? ????

0000 0000 0??? ????

???? ???? ???? ????

0000 0000 00?? ????

dddd dddd dddd dddd

0000 0000 dddd dddd

0000 000d dddd dddd

0000 0000 dddd dddd

0000 00?? ???? ????

dddd dddd dddd dddd

0000 0000 0000 00dd

dddd dddd dddd dddd

–

AEC/AGC Enable

AEC/AGC Pix Count

LVDS Master Ctrl

LVDS Shift Clk Ctrl

LVDS Data Ctrl

Data Stream Latency

LVDS Internal Sync

LVDS Payload Control

Stereoscop. Error Ctrl

Stereoscop. Error Flag

LVDS Data Output

AGC Gain Output

AEC Gain Output

AGC/AEC Current Bin

Maximum Shutter Width

AGC/AEC Bin Difference Threshold

Field Blank

RO

0x01E0

0x0014

0x0016

0x000A

RO

Mon Mode Capture Ctrl

Temperature

Analog Controls

0x0840

0x03840

0x4416

0x4421

0x0000

Reserved

0xBEEF

NTSC FV & LV Ctrl

NTSC Horiz Blank Ctrl

NTSC Vert Blank Ctrl

Bytewise Addr

0xF1

Reserved

–

0xFE

0xFF

Register Lock

dddd dddd dddd dddd

0001 0011 0000 0000

Chip Version

Iter. 1: 0x1311

Iter. 2 : 0x1311

Iter. 3: 0x1313

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19

MT9V032

Shadowed Registers

Some sensor settings cannot be changed during frame

readout. For example, changing the register Window Width

(R0x04) part way through frame readout results in

inconsistent LINE_VALID behavior. To avoid this, the

MT9V032 double buffers many registers by implementing

a “pending” and a “live” version. Two−wire serial interface

reads and writes access the pending register. The live

register controls the sensor operation. The value in the

pending register is transferred to a live register at a fixed

point in the frame timing, called “frame−start.” Frame−start

is defined as the point at which the first dark row is read out.

By default, this occurs four row times before

FRAME_VALID goes HIGH. To determine which registers

or register fields are double−buffered in this way, see the

“Shadowed” column in Table 8.

• Shadowed

N = No. The register value is updated and used

immediately.

Y = Yes. The register value is updated at next frame

start. Frame start is defined as when the first dark row

is read out. By default this is four rows before

FRAME_VALID goes HIGH.

• Read/Write

R = Read−only register/bit.

W = Read/Write register/bit.

Table 8 provides a detailed description of the registers. Bit

fields that are not identified in the table are read only.

Table 8. REGISTER DESCRIPTIONS

Default

in Hex

(Dec)

Legal

Values

(Dec)

Shad-

owed

Read/

Write

Bit

0X00/0XFF (0/255) CHIP VERSION

15:0 Chip Version

Bit Name

Bit Description

Chip version—read−only

Iter. 1:

0x1311

(4881)

R

Iter. 2:

0x1311

(4881)

Iter. 3:

0x1313

(4883)

0X01 (1) COLUMN START

9:0 Column Start

The first column to be read out (not counting dark

columns that may be read). To window the image down, set

this register to the starting X value. Readable/active col-

umns are 1–752.

1

Y

1–752

4–482

W

0X02 (2) ROW START

8:0 Row Start

4

The first row to be read out (not counting any dark rows that

may be read). To window the image down, set this register

to the starting Y value. Setting a value less than four is not

recommended since the dark rows should be read using

R0x0D.

0X03 (3) WINDOW HEIGHT

8:0 Window Height

Number of rows in the image to be read out (not counting

any dark rows or border rows that may be read).

1E0

Y

1–480

1–752

W

(480)

0X04 (4) WINDOW WIDTH

9:0 Window Width

Number of columns in image to be read out (not counting

any dark columns or border columns that may be read).

2F0

(752)

0X05 (5) HORIZONTAL BLANKING

9:0 Horizontal Blanking

Number of blank columns in a row. Minimum horizontal

blanking is 43 columns.

05E

(94)

43–1023

4–3000

0X06 (6) VERTICAL BLANKING

14:0 Vertical Blanking

Number of blank rows in a frame. This number must be

equal to or larger than four.

002D

(45)

0X07 (7) CHIP CONTROL

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20

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X06 (6) VERTICAL BLANKING

2:0

Scan Mode

0 = Progressive scan.

1 = Not valid.

0

Y

0, 2, 3

W

2 = Two−field Interlaced scan. Even−numbered rows are

read first, and followed by odd−numbered rows.

3 = Single−field Interlaced scan. If start address is even

number, only even−numbered rows are read out; if start

address is odd number, only odd−numbered rows are

read out. Effective image size is decreased by half.

3

4

5

6

Sensor Master/Slave

Mode

0 = Slave mode. Initiating exposure and readout is allowed.

1

0

Y

0,1

W

1 = Master mode. Sensor generates its own exp

sure and readout timing according to simultaneous/se-

quential mode control bit.

Sensor Snapshot Mode 0 = Snapshot disabled.

1 = Snapshot mode enabled. The start of frame is triggered

by providing a pulse at EXPOSURE pin. Sensor master/

slave mode should be set to logic 1 to turn on this mode.

Stereoscopy Mode

0 = Stereoscopy disabled. Sensor is stand−alone and the

PLL generates a 320 MHz (x12) clock.

1 = Stereoscopy enabled. The PLL generates a 480 MHz

(x18) clock.

Stereoscopic

Master/Slave mode

0 = Stereoscopic master.

1 = Stereoscopic slave. Stereoscopy mode should be en-

abled when using this bit.

7

8

Parallel Output Enable

0 = Disable parallel output. DOUT(9:0) are in High−Z.

1 = Enable parallel output.

1

Y

0,1

W

Simultaneous/

Sequential Mode

0 = Sequential mode. Pixel and column readout takes place

only after exposure is complete.

1 = Simultaneous mode. Pixel and column readout takes

place in conjunction with exposure.

0X08 (8) SHUTTER WIDTH 1

14:0 Shutter Width 1

The row number in which the first knee occurs. This may be

used only when high dynamic range option (bit 6 of R0x0F)

is enabled and exposure knee point auto adjust control bit is

disabled. This register is not shadowed, but any change

made does not take effect until the following new frame.

1BB

N

1–32767

W

(443)

0X09 (9) SHUTTER WIDTH 2

14:0 Shutter Width 2

The row number in which the second knee occurs. This may

be used only when high dynamic range option (bit 6 of

R0x0F) is enabled and exposure knee point auto adjust

control bit is disabled. This register is not shadowed, but

any change made does not take effect until the following

new frame.

1D9

(473)

Shutter width 2 = (bits 14:0)

Note:

t

= Shutter width 1;

= Shutter width 2 – Shutter 1;

= Total integration – Shutter width 2.

1

2

3

0X0A (10) SHUTTER WIDTH CONTROL

3:0 T2 Ratio One−half to the power of this value indicates the ratio of

4

N

0–15

W

duration time t , when saturation control gate is adjusted to

2

level V2 to total integration when exposure knee point auto

adjust control bit is enabled. This register is not shadowed,

but any change made does not take effect until the following

new frame.

t2_ratio

t

= Total integration × (½)

.

2

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21

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X09 (9) SHUTTER WIDTH 2

7:4

T3 Ratio

One−half to the power of this value indicates the ratio of

6

N

0–15

W

duration time t , when saturation control gate is adjusted to

3

level V3 to total integration when exposure knee point auto

adjust control bit is enabled. This register is not shadowed,

but any change made does not take effect until the following

new frame.

t3_ratio

t

= Total integration × (½)

.

3

Note: t ^{= Total integration − t}− t .

1

2

3

8

9

Exposure Knee Point

Auto Adjust Enable

0 = Auto adjust disabled.

1 = Auto adjust enabled.

1

0

N

0,1

W

Single Knee Enable

0 = Single knee disabled.

1 = Single knee enabled.

0X0B (11) TOTAL SHUTTER WIDTH

14:0 Total Shutter Width

Total integration time in number of rows. This value is used

only when AEC is disabled only (bit 0 of Register 175). This

register is not shadowed, but any change made does not

take effect until the following new frame.

1E0

(480)

N

1–32767

W

0X0C (12) RESET

0

Soft Reset

Setting this bit causes the sensor to abandon the current

frame by resetting all digital logic except two−wire serial

interface configuration. This is a self−resetting register bit

and should always read “0.” (This bit de−asserts internal

active LOW reset signal for 15 clock cycles.)

0

N

Y

0, 1

W

1

Auto Block Soft Reset

Setting this bit causes the sensor to reset the automatic

gain and exposure control logic. This is a self−resetting

register bit and should always read “0.” (This bit de−asserts

internal active LOW reset signal for 15 clock cycles.)

0X0D (13) READ MODE

1:0

3:2

4

Row Bin

0 = Normal operation.

0

Y

0, 1, 2

0, 1

W

1 = Row bin 2. Two pixel rows are read per row output.

Image size is effectively reduced by a factor of 2 vertically

while data rate and pixel clock are not affected. Resulting

frame rate is increased by 2.

2 = Row bin 4. Four pixel rows are read per row output.

Image size is effectively reduced by a factor of 4 vertically

while data rate and pixel clock are not affected. Resulting

frame rate is increased by 4.

3 = Not valid.

Column Bin

0 = Normal operation.

1 = Column bin 2. When set, image size is reduced by a

factor of 2 horizontally. Frame rate is not affected but data

rate and pixel clock are reduced by one−half that of

master clock.

2 = Column bin 4. When set, image size is reduced by a

factor of 4 horizontally. Frame rate is not affected but data

rate and pixel clock are reduced by one−fourth that of

master clock.

3 = Not valid.

Row Flip

Read out rows from bottom to top (upside down). When set,

row readout starts from row (Row Start + Window Height)

and continues down to (Row Start + 1). When clear, readout

starts at Row Start and continues to (Row Start + Window

Height − 1). This ensures that the starting color is main-

tained.

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22

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X09 (9) SHUTTER WIDTH 2

5

Column Flip

Read out columns from right to left (mirrored). When set,

column readout starts from column (Col Start + Window

Width) and continues down to (Col Start + 1). When clear,

readout starts at Col Start and continues to (Col Start +

Window Width − 1). This ensures that the starting color is

maintained.

0

Y

0, 1

W

6

Show Dark Rows

When set, the programmed dark rows is output before the

active window. Frame valid is thus asserted earlier than

normal. This has no effect on integration time or frame rate.

Whether the dark rows are shown in the image or not the

definition frame start is before the dark rows are read out.

0

Y

0, 1

W

7

Show Dark Columns

Reserved

When set, the programmed dark columns are output before

the active pixels in a line. Line valid is thus asserted earlier

than normal, and the horizontal blank time gets shorter by

18 pixel clocks.

9:8

Reserved.

3

0

0X0E (14) MONITOR MODE

Monitor Mode Enable

0

Setting this bit puts the sensor into a cycle of sleeping for

five minutes, and waking up to capture a programmable

number of frames (R0xC0). Clearing this bit resumes nor-

mal operation.

Y

0, 1

W

0X0F (15) PIXEL OPERATION MODE

2

Color/Mono

Should be set according to sensor type:

0 = Monochrome.

1 = Color.

0

Y

0, 1

W

6

High Dynamic Range

0 = Linear operation.

1 = High Dynamic Range. Voltage and shutter width must

be correctly set for saturation control to operate.

0X1B (27) LED_OUT CONTROL

0

Disable LED_OUT

Disable LED_OUT output. When cleared, the output pin

LED_OUT is pulsed high when the sensor is undergoing

exposure.

0

Y

0, 1

W

1

Invert LED_OUT

Invert polarity of LED_OUT output. When set, the output pin

LED_OUT is pulsed low when the sensor is undergoing

exposure.

0X1C (28) ADC RESOLUTION CONTROL

1:0

ADC Mode

0 = Invalid.

2

4

Y

N

2, 3

0–7

W

1 = Invalid.

2 = 10−bit linear.

3 = 12−to10−bit companding.

0X2C (44) VREF_ADC CONTROL

2:0

VREF_ADC Voltage

Level

0 = VREF_ADC = 1.0V.

1 = VREF_ADC = 1.1V.

2 = VREF_ADC = 1.2V.

3 = VREF_ADC = 1.3V.

4 = VREF_ADC = 1.4V.

5 = VREF_ADC = 1.5V.

6 = VREF_ADC = 1.6V.

7 = VREF_ADC = 2.1V.

Range: 1.0–2.1V; Default: 1.4V

VREF_ADC for ADC.

0X31 (49) V1 CONTROL

4:0 V1 voltage level

V_Step = bits (4:0) x 62.5mV + 0.5625V.

Range: 0.5625 − 2.5V; Default: 2.375V.

Usage: V_Step1 HiDy voltage.

1D

(29)

N

0–31

W

0X32 (50) V2 CONTROL

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23

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X32 (50) V2 CONTROL

4:0

V2 voltage level

V_Step = bits (4:0) x 62.5mV + 0.5625V.

Range: 0.5625 − 2.5V; Default: 2.0625V.

Usage: V_Step2 HiDy voltage.

18

N

0–31

W

(24)

0X33 (51) V3 CONTROL

4:0 V3 voltage level

V_Step = bits (4:0) x 62.5mV + 0.5625V.

Range: 0.5625 − 2.5V; Default: 1.875V.

Usage: V_Step3 HiDy voltage.

15

(21)

0X34 (52) V4 CONTROL

4:0 V4 voltage level

V_Step = bits (4:0) x 62.5mV + 0.5625V.

Range: 0.5625 − 2.5V; Default: 0.8125V.

Usage: V_Step HiDy parking voltage, also provides anti−

blooming when V_Step is disabled.

4

0X35 (53) ANALOG GAIN

6:0 Analog Gain

Analog gain = bits (6:0) x 0.0625 for values 16–31

Analog gain = bits (6:0)/2 x 0.125 for values 32–64

For values 16–31: each LSB increases analog gain

0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X

For values 32–64: each 2 LSB increases analog gain

0.125v/v. Range: 2X to 4X. An LSB increase of 1 will not

increase the gain; the value must be incremented by 2

No exception detection is installed and caution

should be taken when programming

10

(16)

Y

16–64

W

0X36 (54) MAXIMUM ANALOG GAIN

6:0 Maximum Analog Gain

This register is used by the automatic gain control (AGC) as

the upper threshold of gain. This ensures the new calibrated

gain value does not exceed that which the MT9V032 sup-

ports.

40

(64)

Y

16–64

W

Range: 16 –64

for 1X–4X respectively. Note: No ex-

dec

ception detection is installed; caution should be taken when

programming.

0X42 (66) FRAME DARK AVERAGE

7:0 Frame Dark Average

The value read is the frame averaged black level, that is,

used in the black level algorithm calculations.

0

R

0X46 (70) DARK AVERAGE THRESHOLDS

7:0

Lower threshold

Lower threshold for targeted black level in ADC LSBs.

1D

N

0–255

W

(29)

15:8

Upper threshold

Upper threshold for targeted black level in ADC LSBs.

23

(35)

0X47 (71) BLACK LEVEL CALIBRATION CONTROL

0

Manual Override

Manual override of black level correction.

1 = Override automatic black level correction with pro-

grammed values. (R0x48).

0

4

N

0, 1

0–7

W

0 = Normal operation (default).

7:5

Frames to average over Two to the power of this value decide how many frames to

average over when the black level algorithm is in the aver-

aging mode. In this mode the running frame average is

calculated from the following formula:

Running frame ave = Old running frame ave − (old running

frame ave)/2n + (new frame ave)/ 2n.

15:8

Reserved

Reserved.

80

(128)

0X48 (72) BLACK LEVEL CALIBRATION VALUE

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24

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X48 (72) BLACK LEVEL CALIBRATION VALUE

7:0

Black Level Calibration

Value

Analog calibration offset: Negative numbers are represented

with two’s complement, which is shown in the following

formula: Sign = bit 7 (0 is positive, 1 is negative).

0

N

–127 to

127

W

If positive offset value: Magnitude = bit 6:0.

If negative offset value: Magnitude = not (bit 6:0) + 1.

During two−wire serial interface read, this register returns

the user−programmed value when manual override is en-

abled (R0x47 bit 0); otherwise, this register returns the re-

sult

obtained from the calibration algorithm.

0X4C (76) BLACK LEVEL CALIBRATION VALUE STEP SIZE

4:0

Step Size of Calibration This is the size calibration value may change (positively or

2

4

N

Y

0–31

W

Value

negatively) from frame to frame.

1 calib LSB = ½ ADC LSB, assuming analog gain = 1.

0X70 (112) ROW NOISE CORRECTION CONTROL 1

3:0

Number of Dark Pixels

The number of pixels used in the row−wise noise calcula-

tion.

0, 1, 2,

4, 8

0 = 2 pixels.

1 = 4 pixels.

2 = 6 pixels.

4 = 10 pixels.

8 = 18 pixels.

See “Row−wise Noise Correction” for additional information.

4

5

Reserved

Reserved.

1

Enable noise correction 0 = Normal operation.

1 = Enable row noise cancellation algorithm. When this bit is

Y

0, 1

W

set, on a per row basis, the dark average is subtracted

from each pixel in the row, and then a constant (R0x72) is

added.

11

Use black level average 1 = Use black level frame average from the dark rows in the

row noise correction algorithm for low gains. This frame

0

average was taken before the last adjustment of the offset

DAC for that frame, so it might be slightly off.

0 = Use the average value of the dark columns read out in

each row as dark average.

0X72 (114) ROW NOISE CONSTANT

7:0 Row noise constant

Constant used in the row noise cancellation algorithm. It

should be set to the dark level targeted by the black level

algorithm plus the noise expected between the averaged

values of dark columns. At default the constant is set to 42

LSB.

2A

Y

0–255

W

(42)

0X73 (115) ROW NOISE CORRECTION CONTROL 2

9:0

Dark start column ad-

dress

The starting column address for the dark columns to be

used in the row−wise noise correction algorithm.

2F7

(759)

759–775

0X74 (116) PIXEL CLOCK, FRAME AND LINE VALID CONTROL

0

1

2

Invert Line Valid

Invert Frame Valid

XOR Line Valid

Invert line valid. When set, LINE_VALID is reset to logic “0”

when DOUT is valid.

0

Y

0, 1

W

Invert frame valid. When set, FRAME_VALID is reset to

logic “0” when frame is valid.

1 = Line valid = ”Continuous” Line Valid XOR Frame Valid

0 = Line Valid determined by bit 3. Ineffective if Continuous

Line Valid is set.

3

Continuous Line Valid

1 = ”Continuous” Line Valid (continue producing line valid

during vertical blank).

0

Y

0, 1

W

0 = Normal Line Valid (default, no line valid during vertical

blank).

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25

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X74 (116) PIXEL CLOCK, FRAME AND LINE VALID CONTROL

4

Invert Pixel Clock

Invert pixel clock. When set, LINE_VALID, FRAME_VALID,

and DOUT is set up to the rising edge of pixel clock, PIXCLK.

When clear, they are set up to the falling edge of PIXCLK.

0

Y

N

0, 1

W

0X7F (127) DIGITAL TEST PATTERN

9:0

Two−wire Serial Inter-

face Test Data

The 10−bit test data in this register is used in place of the

data from the sensor. The data is inserted at the beginning

of the digital signal processing. Both test enable (bit 13) and

use two−wire serial interface (bit 10) must be set.

0–1023

10

Use Two−wire Serial In- 0 = Use Gray Shade Test Pattern as test data.

0

N

0, 1

0–3

W

terface Test Data

1 = Use Two−wire Serial Interface Test Data (bits 9:0) as

test data.

12:11

Gray Shade Test Pat-

tern

0 = None.

1 = Vertical Shades.

2 = Horizontal Shades.

3 = Diagonal Shade.

^{When bits (12:11)}! 0, the MT9V032 generates a gray

shaded test pattern to be used as digital test data. Ineffec-

tive when Use Two−wire Serial Interface Test Data (bit 10)

is set.

13

14

Test Enable

Enable the use of test data/gray shaded test pattern in the

signal chain. The data is inserted instead of data from the

ADCs.

Set R0x70 bit 5 = 0 when using this mode. If R0x70 bit 5 =

1, the row−wise correction algorithm processes the test data

values and the result is not accurate.

0

Y

N

0, 1

W

Flip Two−Wire Serial In- Use only when two−wire serial interface test data (bit 10) is

terface Test Data

set. When set, the two−wire serial interface test data (bits

9:0) is used in place of the data from ADC/memory on odd

columns, while complement of the two−wire serial interface

test data is used on even columns.

0X80 (128) − 0X98 (152) TILED DIGITAL GAIN

3:0

Tile Gain

Tile Digital Gain = Bits (3:0) x 0.25. See “Gain Settings” for

additional information on digital gain.

4

Y

1–15

0–15

W

7:4

Sample Weight

To indicate the weight of individual tile used in the automatic

gain/exposure control algorithm.

F

(15)

Refer to Figure 25 for R0x99 (153) − R0xA4 (164).

0X99 (153) DIGITAL TILE COORDINATE 1 − X−DIRECTION

9:0

0X9A (154) DIGITAL TILE COORDINATE 2 − X−DIRECTION

9:0 The starting x−coordinate of digital tiles X1_*.

X

The starting x−coordinate of digital tiles X0_*.

0

Y

0–752

W

0/5

X

096

(150)

1/5

0X9B (155) DIGITAL TILE COORDINATE 3 − X−DIRECTION

9:0 The starting x−coordinate of digital tiles X2_*.

X

12C

Y

0–752

W

2/5

(300)

0X9C (156) DIGITAL TILE COORDINATE 4 − X−DIRECTION

9:0 The starting x−coordinate of digital tiles X3_*.

X

1C2

(450)

3/5

0X9D (157) DIGITAL TILE COORDINATE 5 − X−DIRECTION

9:0 The starting x−coordinate of digital tiles X4_*.

X

258

(600)

4/5

0X9E (158) DIGITAL TILE COORDINATE 6 − X−DIRECTION

9:0

X

The ending x−coordinate of digital tiles X4_*.

2F0

(752)

5/5

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26

MT9V032

Table 8. REGISTER DESCRIPTIONS

0X9F (159) DIGITAL TILE COORDINATE 1 − Y−DIRECTION

8:0

0XA0 (160) DIGITAL TILE COORDINATE 2 − Y−DIRECTION

8:0 The starting y−coordinate of digital tiles *_Y1.

Y

The starting y−coordinate of digital tiles *_Y0.

0

Y

0–480

W

0/5

Y

60

(96)

1/5

0XA1 (161) DIGITAL TILE COORDINATE 3 − Y−DIRECTION

8:0 The starting y−coordinate of digital tiles *_Y2.

Y

0C0

Y

0–480

1–64

W

2/5

(192)

0XA2 (162) DIGITAL TILE COORDINATE 4 − Y−DIRECTION

8:0 The starting y−coordinate of digital tiles *_Y3.

Y

120

(288)

3/5

0XA3 (163) DIGITAL TILE COORDINATE 5 − Y−DIRECTION

8:0 The starting y−coordinate of digital tiles *_Y4.

Y

180

(384)

W

4/5

0XA4 (164) DIGITAL TILE COORDINATE 6 − Y−DIRECTION

8:0

Y

The ending y−coordinate of digital tiles *_Y4.

1E0

(480)

W

5/5

0XA5 (165) AEC/AGC DESIRED BIN

5:0 Desired Bin

User−defined “desired bin” that gives a measure of how

bright the image is intended

3A

(58)

W

0XA6 (166) AEC UPDATE FREQUENCY

3:0 Exp Skip Frame

The number of frames that the AEC must skip before updat-

ing the exposure register (R0xBB).

2

0–15

W

0XA8 (168) AEC LOW PASS FILTER

1:0 Exp LPF

This value plays a role in determining the increment/decre-

ment size of exposure value from frame to frame. If current

bin ! 0 (R0xBC),

0–2

WX

When Exp LPF = 0:

Actual new exposure = Calculated new exposure

When Exp LPF = 1:

If |(Calculated new exp − current exp) | > (current exp/4),

Actual new exposure = Calculated new exposure, otherwise

Actual new exposure = Current exp + (calculated new

exp/2)

When Exp LPF = 2:

If |(Calculated new exp − current exp) |> (current exp/4),

Actual new exposure = Calculated new exposure, otherwise

Actual new exposure = Current exp + (calculated new

exp/4)

0XA9 (169) AGC OUTPUT UPDATE FREQUENCY

3:0

Gain Skip Frame

The number of frames that the AGC must skip before updat-

ing the gain register (R0xBA).

2

Y

0–15

W

0XAB (171) AGC LOW PASS FILTER

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MT9V032

Table 8. REGISTER DESCRIPTIONS

0XAB (171) AGC LOW PASS FILTER

1:0

Gain LPF

This value plays a role in determining the increment/decre-

ment size of gain value from frame to frame. If current bin !

0 (R0xBC)

2

Y

0–2

W

When Gain LPF = 0

Actual new gain = Calculated new gain

When Exp LPF = 1

if |(Calculated new gain − current gain) | > (current gain/4),

Actual new gain = Calculated new gain, otherwise

Actual new gain = Current exp+ (calculated new gain/2)

When Exp LPF = 2:

if |(Calculated new gain − current gain) | > (current gain /4),

Actual new gain = Calculated new gain, otherwise

Actual new gain = Current gain+ (calculated new gain/4).

0XAF (175) AGC/AEC ENABLE

0

AEC Enable

0 = Disable Automatic Exposure Control

1 = Enable Automatic Exposure Control

Y

0, 1

W

1

AGC Enable

0 = Disable Automatic Gain Control.

1 = Enable Automatic Gain Control.

0XB0 (176) AGC/AEC PIXEL COUNT

15−0 Pixel Count

The number of pixel used for the AEC/AGC histogram.

ABE0

Y

0–65535

0, 1

W

(44,00)

0XB1 (177) LVDS MASTER CONTROL

0

PLL Bypass

0 = Internal shift−CLK is driven by PLL.

0

1 = Internal shift−CLK is sourced from the LVDS_BY-

PASS_CLK.

1

2

LVDS Power−down

0 = Normal operation.

1 = Power−down LVDS block.

1

0

Y

0, 1

W

PLL Test Mode

0 = Normal operation.

1 = The PLL output frequency is equal to the system clock

frequency (26.6 MHz).

3

LVDS Test Mode

0 = Normal operation.

0

Y

0, 1

W

1 = The SER_DATAOUT_P drives a square wave in both

stereo and stand−alone modes). In stereo mode, ensure

that SER_DATAIN_P is logic “0.”

0XB2 (178) LVDS SHIFT CLOCK CONTROL

2:0

Shift−clk Delay Element The amount of shift−CLK delay that minimizes inter−sensor

Select skew.

0

1

Y

0–7

0, 1

W

4

LVDS Receiver Power− When set, LVDS receiver is disabled.

down

0XB3 (179) LVDS DATA CONTROL

2:0

Data Delay Element

Select

The amount of data delay that minimizes inter−sensor skew.

0

1

Y

0–7

0, 1

W

4

LVDS Driver Power−

down

When set, data LVDS driver is disabled.

0XB4 (180) LVDS LATENCY

1:0 Stream Latency Select

0XB5 (181) LVDS INTERNAL SYNC

LVDS Internal Sync En- When set, the MT9V032 generates sync pattern (data with

The amount of delay so that the two streams are in sync.

0

Y

0–3

0, 1

W

0

able all zeros except start bit) on LVDS_SER_DATA_OUT.

0XB6 (182) LVDS PAYLOAD CONTROL

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MT9V032

Table 8. REGISTER DESCRIPTIONS

0XB6 (182) LVDS PAYLOAD CONTROL

0

Use 10−bit Pixel Enable When set, all 10 pixel data bits are output in stand−alone

mode. Control signals are embedded. If clear, 8 bits of pixel

data are output with 2 control bits. See “LVDS Output For-

mat” for additional information.

0

Y

0, 1

W

0XB7 (183) STEREOSCOPY ERROR CONTROL

0

1

2

Enable Stereo Error

Detect

Set this bit to enable stereo error detect mechanism.

0

Y

0, 1

W

Enable Stick Stereo Er- When set, the stereo error flag remains asserted once an

ror Flag

error is detected unless clear stereo error flag (bit 2) is set.

Clear Stereo Error Flag

Set this bit to clear the stereoscopy error flag (R0xB8

returns to logic 0).

0XB8 (184) STEREOSCOPY ERROR FLAG

0

Stereoscopy Error Flag

Stereoscopy error status flag. It is also directly connected to

the ERROR output pin.

R

0XB9 (185) LVDS DATA OUTPUT

15:0 Combo Reg

This 16−bit value contains both 8−bit pixel values from both

stereoscopic master and slave sensors. It can be used in

diagnosis to determine how well in sync the two sensors

are. Captures the state when master sensor has issued

a reserved byte and slave has not.

Note: This register should be read from the stereoscopic

master sensor only.

0XBA (186) AGC GAIN OUTPUT

6:0 AGC Gain

Status register to report the current gain value obtained

from the AGC algorithm.

10

R

(16)

0XBB (187) AEC EXPOSURE OUTPUT

15:0 AEC Exposure

Status register to report the current exposure value obtained

from the AEC Algorithm.

00C8

(200)

0XBC (188) AGC/AEC CURRENT BIN

5:0 Current Bin Status register to report the current bin of the histogram.

0XBD (189) MAXIMUM TOTAL SHUTTER WIDTH

R

15:0

Maximum Total Shutter

Width

This register is used by the automatic exposure control

(AEC) as the upper threshold of exposure. This ensures the

new calibrated integration value does not exceed that which

the MT9V032 supports.

01E0

(480)

Y

1–2047

0–63

W

0XBE (190) AGC/AEC BIN DIFFERENCE THRESHOLD

7:0

Bin Difference Thresh-

old

This register is used by the AEC only when exposure reach-

es its minimum value of 1. If the difference between desired

bin (R0xA5) and current bin (R0xBC) is larger than the

threshold, the exposure is increased.

14

(20)

W

0XBF (191) FIELD VERTICAL BLANK

8:0 Field Vertical Blank

The number of blank rows between odd and even fields.

Note: For interlaced (both field) mode only. See R0x07[2:0].

16

(22)

Y

0–255

0XC0 (192) MONITOR MODE CAPTURE CONTROL

7:0

Image Capture Numb

The number of frames to be captured during the wake−up

period when monitor mode is enabled.

0A

(10)

W

R

0XC1 (193) THERMAL INFORMATION

9:0 Temperature Output

Status register to report the temperature of sensor. Updated

once per frame.

0XC2 (194) ANALOG CONTROLS

Reserved

6

Reserved.

1

N

0, 1

W

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29

MT9V032

Table 8. REGISTER DESCRIPTIONS

0XC2 (194) ANALOG CONTROLS

7

Anti−Eclipse Enable

Setting this bit turns on anti−eclipse circuitry.

0

1

N

0, 1

0–7

W

11:13

V_rst_lim voltage Level

V_rst_lim = bits (2:0) × 50mV + 1.95V

Range: 1.95–2.30V; Default: 2.00V

Usage: For anti−eclipse reference voltage control

0XC3 (195) NTSC FRAME VALID CONTROL

0

Extend Frame Valid

When set, frame valid is extended for half−line in length at

0

Y

0, 1

W

the odd field.

1

Replace FV/LV with

Ped/Snyc

When set, frame valid and line valid is replaced by ped and

sync signals respectively.

0XC4 (196) NTSC HORIZONTAL BLANKING CONTROL

7:0

Front porch width

The front porch width in number of master clock cycle.

16

Y

0–255

W

NTSC standard is 1.5msec 0.1msec

(22)

15:8

Sync Width

The sync pulse width in number of master clock cycle.

NTSC standard is 4.7msec 0.1msec.

044

(68)

0XC5 (197) NTSC VERTICAL BLANKING CONTROL

7:0

Equalizing Pulse Width

The pulse width in number of master clock cycle. NTSC

21

Y

0–255

W

standard is 2.3msec 0.1msec.

(33)

15:8

Vertical Serration Width The pulse width in number of master clock cycle. NTSC

44

(68)

standard is 4.7msec 0.1msec.

0XF0 (240) BYTEWISE ADDRESS

Bytewise Address

Special address to perform 8−bit READs and WRITEs to

the sensor. See the “Two−Wire Serial Interface Sam-

ple Read and Write Sequences” for further details on how to

use this functionality.

0XFE (254) REGISTER LOCK

15:0

Register Lock Code

To lock all registers except R0xFE, program data with

0xDEAD; to unlock two−wire serial interface, program data

with 0xBEEF. When two−wire serial interface is locked, any

subsequent two−wire serial interface write to register other

than to two−wire serial interface Protect Enable Register is

ignored until two−wire serial interface is unlocked.

BEEF

(48879)

N

48879,

57005,

57007

W

To lock Register 13 only, program data with 0xDEAF; to

unlock, program data with 0xBEEF. When Register 13 is

locked, any subsequent two−wire serial interface write to

this register only is ignored until register is unlocked.

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30

MT9V032

FEATURE DESCRIPTION

Operational Modes

Master Mode

The MT9V032 works in master, snapshot, or slave mode.

In master mode the sensor generates the readout timing. In

snapshot mode it accepts an external trigger to start

integration, then generates the readout timing. In slave mode

the sensor accepts both external integration and readout

controls. The integration time is programmed through the

two−wire serial interface during master or snapshot modes,

or controlled through externally generated control signal

during slave mode.

There are two possible operation methods for master

mode: simultaneous and sequential. One of these operation

modes must be selected through the two−wire serial

interface.

Simultaneous Master Mode

In simultaneous master mode, the exposure period occurs

during readout. The frame synchronization waveforms are

shown in Figure13 and Figure 14. The exposure and readout

happen in parallel rather than sequentially, making this the

fastest mode of operation.

Readout Time > Exposure Time

LED_OUT

Readout Time

FRAME_VALID

LINE_VALID

Vertical Blanking

D

(9:0)

OUT

XXX

Figure 13. Simultaneous Master Mode Synchronization Waveforms #1

Exposure Time > Readout Time

LED_OUT

Exposure Time

FRAME_VALID

LINE_VALID

Vertical Blanking

XXX

D

(9:0 XXX

XXX

OUT

(9:0)

OUT

)

Figure 14. Simultaneous Master Mode Synchronization Waveforms #2

Sequential Master Mode

When exposure time is greater than the sum of vertical

blank and window height, the number of vertical blank rows

is increased automatically to accommodate the exposure

time.

In sequential master mode the exposure period is followed

by readout. The frame synchronization waveforms for

sequential master mode are shown in Figure15. The frame

rate changes as the integration time changes.

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31

MT9V032

LED_OUT

Exposure Time

FRAME_VALID

LINE_VALID

XXX

(9:0)

D

XXX

OUT

Figure 15. Sequential Master Mode Synchronization Waveforms

Snapshot Mode

In snapshot mode the sensor accepts an input trigger

signal which initiates exposure, and is immediately

followed by readout. Figure 16 shows the interface signals

used in snapshot mode. In snapshot mode, the start of the

integration period is determined by the externally applied

EXPOSURE pulse that is input to the MT9V032. The

integration time is preprogrammed via the two−wire serial

interface on R0x0B. After the frame’s integration period is

complete the readout process commences and the syncs and

data are output. Sensor in snapshot mode can capture a single

image or a sequence of images. The frame rate may only be

controlled by changing the period of the user supplied

EXPOSURE pulse train. The frame synchronization

waveforms for snapshot mode are shown in Figure 17.

EXPOSURE

SYSCLK

PIXCLK

LINE_VALID

FRAME_VALID

CONTROLLER

MT9V032

D

)

(9:0)

OUT

Figure 16. Snapshot Mode Frame Synchronization Waveforms

EXPOSURE

Exposure Time

LED_OUT

FRAME_VALID

LINE_VALID

(9:0)

D

XXX

D

)

(9:0 XXX

OUT

XXX

OUT

Figure 17. Snapshot Mode Frame Synchronization Waveforms

Slave Mode

In slave mode, the exposure and readout are controlled

using the EXPOSURE, STFRM_OUT, and STLN_OUT

pins. When the slave mode is enabled, STFRM_OUT and

STLN_OUT become input pins.

The start and end of integration are controlled by

EXPOSURE and STFRM_OUT pulses, respectively. While

a STFRM_OUT pulse is used to stop integration, it is also

used to enable the readout process.

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MT9V032

After integration is stopped, the user provides

It is recommended that the user program the vertical blank

register (R0x06) with a value of 4, and achieve additional

vertical blanking between frames by delaying the

application of the STFRM_OUT pulse.

The elapsed time between the rising edge of STLN_OUT

and the first valid pixel data is [horizontal blanking register

(R0x05) + 4] clock cycles.

STLN_OUT pulses to trigger row readout. A full row of data

is read out with each STLN_OUT pulse. The user must

provide enough time between successive STLN_OUT

pulses to allow the complete readout of one row.

It is also important to provide additional STLN_OUT

pulses to allow the sensors to read the vertical blanking rows.

1−row

time

Exposure

(input)

1−row

STFRM_OUT

time

2 master

clocks

(input)

LED_OUT

(output)

STLN_OUT

(input)

LINE_VALID

(output)

98 master

clocks

Integration Time

Vertical Blanking

(def=45 lines)

Figure 18. Slave Mode Operation

Signal Path

The MT9V032 signal path consists of a programmable

gain, a programmable analog offset, and a 10−bit ADC. See

“Black Level Calibration” for the programmable offset

operation description.

Gain Selection

(R0x35 or

result of AGC)

ADC Data

(9:0)

Pixel Output

(reset minus signal)

×

10 (12) bit ADC

+

Offset Correction

Voltage (R0x48 or

result of BLC)

C1

Σ

C2

Figure 19. Signal Path

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33

MT9V032

ON−CHIP BIASES

ADC Voltage Reference

The ADC voltage reference is programmed through

R0x2C, bits 2:0. The ADC reference ranges from 1.0V to

2.1V. The default value is 1.4V. The increment size of the

voltage reference is 0.1V from 1.0V to 1.6V (R0x2C[2:0]

values 0 to 6). At R0x2C[2:0] = 7, the reference voltage

jumps to 2.1V.

The effect of the ADC calibration does not scale with

VREF. Instead it is a fixed value relative to the output of the

analog gain stage. At default, one LSB of calibration equals

It is very important to preserve the correct values of the

other bits in R0x2C. The default register setting is 0x0004.

V_Step Voltage Reference

This voltage is used for pixel high dynamic range

operations, programmable from R0x31 through R0x34.

Chip Version

Chip version registers R0x00 and R0xFF are read−only.

two LSB in output data (1LSB

1mV).

= 2mV, 1LSB

=

Offset

ADC

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34

MT9V032

WINDOW CONTROL

Registers R0x01 column start, R0x02 Row Start, R0x03

window height (row size), and R0x04 window width

(column size) control the size and starting coordinates of the

window.

The values programmed in the window height and width

registers are the exact window height and width out of the

sensor. The window start value should never be set below

four.

To read out the dark rows set bit 6 of R0x0D. In addition,

bit 7 of R0x0D can be used to display the dark columns in

the image.

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MT9V032

BLANKING CONTROL

Horizontal blanking and vertical blanking registers

R0x05 and R0x06 respectively control the blanking time in

a row (horizontal blanking) and between frames (vertical

blanking).

• Vertical blanking is specified in terms of numbers of

rows.

The actual imager timing can be calculated using Table4

and Table

5 which describe “Row Timing and

• Horizontal blanking is specified in terms of pixel

FRAME_VALID/LINE_VALID signals.” The minimum

number of vertical blank rows is 4.

clocks.

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36

MT9V032

PIXEL INTEGRATION CONTROL

Total Integration

R0x0B Total Shutter Width (In Terms of Number of

Rows)

is changed through the two−wire serial interface while

FRAME_VALID is asserted for frame n, the first frame

output using the new integration time is frame (n + 2).

Similarly, when automatic exposure control is enabled, any

change to the integration time for frame n first appears in

frame (n + 2) output.

This register (along with the window width and horizontal

blanking registers) controls the integration time for the

pixels.

t

The actual total integration time, INT, is:

t_INT+ (Number of rows of integration x row time) ) overhead

The sequence is as follows:

(eq. 1)

1. During frame n, the new integration time is held in

the R0x0B live register.

where:

2. At the start of frame (n + 1), the new integration

time is transferred to the exposure control module.

Integration for each row of frame (n + 1) has been

completed using the old integration time. The

earliest time that a row can start integrating using

the new integration time is immediately after that

row has been read for frame (n + 1). The actual

time that rows start integrating using the new

integration time is dependent on the new value of

the integration time.

3. When frame (n + 1) is read out, it is integrated

using the new integration time. If the integration

time is changed (R0x0B written) on successive

frames, each value written is applied to a single

frame; the latency between writing a value and it

affecting the frame readout remains at two frames.

However, when automatic exposure control is

disabled, if the integration time is changed through

the two−wire serial interface after the falling edge

of FRAME_VALID for frame n, the first frame

output using the new integration time becomes

frame (n + 3).

• The number of rows integration is equal to the result of

automatic exposure control (AEC) which may vary

from frame to frame, or, if AEC is disabled, the value in

R0x0B

• Row time = (R0x04 + R0x05) master clock periods

• Overhead = (R0x04 + R0x05 – 255) master clock

periods

Typically, the value of R0x0B (total shutter width) is

limited to the number of rows per frame (which includes

vertical blanking rows), such that the frame rate is not

affected by the integration time. If R0x0B is increased

beyond the total number of rows per frame, it is required to

add additional blanking rows using R0x06 as needed. A

t

second constraint is that INT must be adjusted to avoid

banding in the image from light flicker. Under 60Hz flicker,

this means frame time must be a multiple of 1/120 of a

second. Under 50Hz flicker, frame time must be a multiple

of 1/100 of a second.

Changes to Integration Time

With automatic exposure control disabled (R0xAF, bit 0

is cleared to LOW), and if the total integration time (R0x0B)

FRAME_VALID

New Integration

Int = 200 rows

Int = 300 rows

Programmed

Actual

Integration

Int = 300 rows

Int = 200 rows

LED_OUT

Image Data

Output Image with

Int = 200 rows

Output

Image with

Int = 300 rows

Frame Start

Figure 20. Latency When Changing Integration

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37

MT9V032

Exposure Indicator

The exposure indicator is controlled by:

• R0x1B LED_OUT control

• R0x0A shutter width control

• R0x31–R0x34 V_Step voltages

In the MT9V032, high dynamic range (that is, R0x0F, bit

6 = 1) is achieved by controlling the saturation level of the

pixel (HDR or high dynamic range gate) during the exposure

period. The sequence of the control voltages at the HDR gate

is shown in Figure 21. After the pixels are reset, the step

voltage, V_Step, which is applied to HDR gate, is set up at

The MT9V032 provides an output pin, LED_OUT, to

indicate when the exposure takes place. When R0x1B bit 0

is clear, LED_OUT is HIGH during exposure. By using

R0x1B, bit 1, the polarity of the LED_OUT pin can be

inverted.

V1 for integration time t then to V2 for time t , then V3 for

1

2

High Dynamic Range

High dynamic range is controlled by:

• R0x08 shutter width 1

• R0x09 shutter width 2

time t , and finally it is parked at V4, which also serves as

3

an antiblooming voltage for the photodetector. This

sequence of voltages leads to a piecewise linear pixel

response, illustrated (in approximates) in Figure 21.

Exposure

V

(3.3V)

AA

V

(3.3V)

AA

V3~1.0V

V1~1.4V

V2~1.2V

V4~0.8V

tt

11

HDR

Voltage

t

2

t

3

Figure 21. Sequence of Control Voltages at the HDR Gate

dV3

dV2

dV1

Light Intensity

1/t

1

3

2

Figure 22. Sequence of Voltages in a Piecewise Linear Pixel Response

The parameters of the step voltage V_Step which takes

values V1, V2, and V3 directly affect the position of the knee

points in Figure 22.

There are two ways to specify the knee points timing, the

first by manual setting (default) and the second by automatic

knee point adjustment.

Light intensities work approximately as a reciprocal of the

partial exposure time. Typically, 1 is the longest exposure,

2 shorter, and so on. Thus the range of light intensities is

When the auto adjust enabler is set to HIGH (LOW by

default), the MT9V032 calculates the knee points

automatically using the following equations:

t

shortest for the first slope, providing the highest sensitivity.

The register settings for V_Step and partial exposures are:

V1 = R0x31, bits 4:0

V2 = R0x32, bits 4:0

V3 = R0x33, bits 4:0

t₁+ t_INT* t₂* t₃

(eq. 2)

(eq. 3)

(eq. 4)

åt₂+ t_INTx(1ń2)^{R0x0A,bits3:0}

åt₃+ t_INTx(1ń2)^{R0x0A,bits7:4}

t

As a default for auto exposure, 2 is 1/16 of INT, 3 is 1/64

of INT.

V4 = R0x34, bits 4:0

t

INT = 1 + 2 + 3

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MT9V032

t

Variable ADC Resolution

When the auto adjust enabler is disabled (default), 1, 2,

t

By default, ADC resolution of the sensor is 10−bit.

Additionally, a companding scheme of 12−bit into 10−bit is

enabled by the R0x1C (28). This mode allows higher ADC

resolution which means less quantization noise at low−light,

and lower resolution at high light, where good ADC

quantization is not so critical because of the high level of the

photon’s shot noise.

and 3 may be programmed through the two−wire serial

interface:

t₁+ (R0x08, bits 14:0)

(eq. 5)

(eq. 6)

(eq. 7)

t₂+ (R0x09, bits 14:0) * (R0x08,bits 14:0)

t₃+ t_INT* t₁* t₂

t

INT may be based on the manual setting of R0x0B or the

result of the AEC. If the AEC is enabled then the auto knee

adjust must also be enabled.

10−bit

Codes

1,024

768

8 to 1 Companding (2,048 256)

4 to 1 Companding (1,536 384)

2 to 1 Companding (256 128)

512

256

12−bit

Codes

No companding (256 256)

256 512 1,024 2,048

4,096

Figure 23. 12−to 10−Bit Companding Chart

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39

MT9V032

GAIN SETTINGS

Changes to Gain Settings

When the digital gain settings (R0x80–R0x98) are

changed, the gain is updated on the next frame start.

However, the latency for an analog gain change to take effect

depends on the automatic gain control.

(n + 1); if the automatic gain control is disabled, the gain

changed for frame n first appears in frame (n + 2).

Both analog and digital gain change regardless of whether

the integration time is also changed simultaneously.

If automatic gain control is enabled (R0xAF, bit 1 is set to

HIGH), the gain changed for frame n first appears in frame

FRAME_VALID

New Gain

Programmed

Gain = 3.5X

Gain = 3.0X

Actual

Gain

Gain = 3.0X

Gain = 3.5X

Output Image with

Gain = 3.0X

Output

Image with

Gain = 3.5X

Image Data

Frame Start

Figure 24. Latency of Analog Gain Change When AGC Is Disabled

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40

MT9V032

Analog Gain

Analog gain is controlled by:

For values 16–31: each LSB increases analog gain

0.0625v/v. A value of 16 = 1X gain. Range: 1X to 1.9375X.

For values 32–64: each 2 LSB increases analog gain

0.125v/v (that is, double the gain increase for 2 LSB).

Range: 2X to 4X. Odd values do not result in gain increases;

the gain increases by 0.125 for values 32, 34, 36, and so on.

• R0x35 global gain

The formula for gain setting is:

Gain + Bits[6 : 0] x 0.0625

(eq. 8)

The analog gain range supported in the MT9V032 is

1X–4X with a step size of 6.25 percent. To control gain

manually with this register, the sensor must NOT be in AGC

mode. When adjusting the luminosity of an image, it is

recommended to alter exposure first and yield to gain

increases only when the exposure value has reached a

maximum limit.

Digital Gain

Digital gain is controlled by:

• R0x99–R0xA4 tile coordinates

• R0x80–R0x98 tiled digital gain and weight

In the MT9V032, the image may be divided into 25 tiles,

as shown in Figure 25, through the two−wire serial interface,

and apply digital gain individually to each tile.

(eq. 9)

Analog gain + bits(6 : 0) x 0.0625 for values16 * 31

Analog gain + bits(6 : 0) ń 2x 0.125 for values 32 * 64

(eq. 10)

X

0/5

X

3/5

X

4/5

X

1/5

X

2/5

X

5/5

Y

0/5

x4_y0

x0_y0

x1_y0

1/5

x4_y1

x4_y2

x0_y1

x0_y2

x1_y1

x1_y2

Y

2/5

Y

3/5

Y

4/5

Y

5/5

x4_y3

x4_y4

x0_y3

x0_y4

x1_y3

x1_y4

Figure 25. Tiled Sample

Black Level Calibration

Registers 0x99–0x9E and 0x9F–0xA4 represent the

Black level calibration is controlled by:

coordinates X −X

and Y −Y

in Figure 25,

0/5

5/5

0/5

5/5

respectively.

• R0x4C

• R0x42

Digital gains of registers 0x80–0x98 apply to their

corresponding tiles. The MT9V032 supports a digital gain

of 0.25−3.75X.

• R0x46–R0x48

The MT9V032 has automatic black level calibration

on−chip, and if enabled, its result may be used in the offset

correction shown in Figure 26.

The formula for digital gain setting is:

Digital gain + Bits[3 : 0] x 0.25

(eq. 11)

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41

MT9V032

Gain Selection

(R0x35 or

result of AGC)

V

REF

(R0x2C)

ADC Data

(9:0)

Pixel Output

(reset minus signal)

×

10 (12) bit ADC

+

Offset Correction

Voltage (R0x48 or

result of BLC)

C1

Σ

C2

Figure 26. Black Level Calibration Flow Chart

The automatic black level calibration measures the

average value of pixels from 2 dark rows (1 dark row if row

bin 4 is enabled) of the chip. (The pixels are averaged as if

they were light−sensitive and passed through the appropriate

gain.)

This row average is then digitally low−pass filtered over

many frames (R0x47, bits 7:5) to remove temporal noise and

random instabilities associated with this measurement.

Then, the new filtered average is compared to a minimum

acceptable level, low threshold, and a maximum acceptable

level, high threshold.

To avoid oscillation of the black level from below to

above, the region the thresholds should be programmed so

the difference is at least two times the offset DAC step size.

In normal operation, the black level calibration

value/offset correction value is calculated at the beginning

of each frame and can be read through the two−wire serial

interface from R0x48. This register is an 8−bit signed two’s

complement value.

However, if R0x47, bit 0 is set to “1,” the calibration value

in R0x48 may be manually set to override the automatic

black level calculation result. This feature can be used in

conjunction with the “show dark rows” feature (R0x0D, bit

6) if using an external black level calibration circuit.

The offset correction voltage is generated according to the

following formulas:

If the average is lower than the minimum acceptable level,

the offset correction voltage is increased by a programmable

offset LSB in R0x4C. (Default step size is 2 LSB Offset =

1 ADC LSB at analog gain = 1X.)

If it is above the maximum level, the offset correction

voltage is decreased by 2 LSB (default).

Offset Correction Voltage + (8 * bit signed twoȀs complement calibration value, * 127to127) x 0.5mV

(eq. 12)

(eq. 13)

ADC input voltage + (Pixel Output Voltage ) Offset Correction Voltage) x Analog Gain

Row−wise Noise Correction

Row−wise noise correction is controlled by the following

registers:

correction is in addition to the general black level correction

applied to the whole sensor frame and cannot be used to

replace the latter. The dark average is subtracted from each

pixel belonging to the same row, and then a positive constant

is added (R0x72, bits 7:0). This constant should be set to the

dark level targeted by the black level algorithm plus the

noise expected on the measurements of the averaged values

from dark columns; it is meant to prevent clipping from

negative noise fluctuations.

• R0x70 row noise control

• R0x72 row noise constant

• R0x73 dark column start

When the row−wise noise cancellation algorithm is

enabled, the average value of the dark columns read out is

used as a correction for the whole row. The row−wise

Pixel value + ADC value * dark column average ) row noise constant

(eq. 14)

On a per−row basis, the dark column average is calculated

from a programmable number of dark columns (pixels)

values (R0x70, bits 3:0). The default is 10 dark columns. Of

these, the maximum and minimum values are removed and

then the average is calculated. If R0x70, bits 3:0 are set to

“0” (2 pixels), it is essentially equivalent to disabling the

dark average calculation since the average is equal to “0”

after the maximum and minimum values are removed.

R0x73 is used to indicate the starting column address of

dark pixels that the row−noise correction algorithm uses for

calculation. In the MT9V032, dark columns which may be

used are 759–776. R0x73 is used to select the starting

column for the calculation.

One additional note in setting the row−noise correction

register:

777 t (R0x73, bits9 : 0) ) number of dark pixels programmed in R0x70, bits3 : 0 * 1

(eq. 15)

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42

MT9V032

This is to ensure the column pointer does not go beyond

the limit the MT9V032 can support.

Automatic exposure control (AEC) and automatic gain

control (AGC) can be individually enabled or disabled by

R0xAF. When AEC is disabled (R0xAF[0] = 0), the sensor

uses the manual exposure value in R0x0B. When AGC is

disabled (R0xAF[1] = 0), the sensor uses the manual gain

value in R0x35. See ON Semiconductor Technical Note

TN−09−81, “MT9V032 AEC and AGC Functions,” for

further details.

Automatic Gain Control and Automatic Exposure

Control

The integrated AEC/AGC unit is responsible for ensuring

that optimal auto settings of exposure and (analog) gain are

computed and updated every frame.

EXP. LPF EXP. SKIP MANUAL EXP. AEC ENABLE

(R0xA8)

(R0xA6)

(R0x08)

(R0Xaf[0])

To exposure

MAX. EXPOSURE

(R0xBD)

timing control

R0xBB

0

1

AEC

UNIT

AEC

OUTPUT

MIN EXP

1

HISTOGRAM

GENERATOR

UNIT

DESIRED BIN

(desired luminance)

(R0xA5)

To analog

gain control

AGC OUTPUT

1

0

AGC

UNIT

MIN GAIN

16

MAX. GAIN

(R0x36)

R0xBA

GAIN LPF GAIN SKIP MANUAL GAIN

(R0xAB) (R0xA9) (R0x35)

AGC ENABLE

(R0xAF[1])

Figure 27. Controllable and Observable AEC/AGC Registers

Hard Reset of Logic

The exposure is measured in row−time by reading

R0xBB. The exposure range is 1 to 2047. The gain is

measured in gain−units by reading R0xBA. The gain range

is 16 to 63 (unity gain = 16 gain−units; multiply by 1/16 to

get the true gain).

When AEC is enabled (R0xAF[0] = 1), the maximum auto

exposure value is limited by R0xBD; minimum auto

exposure is fixed at 1 row.

The RC circuit for the MT9V032 uses a 10kW resistor and

a 0.1mF capacitor. The rise time for the RC circuit is 1ms

maximum.

Soft Reset of Logic

Soft reset of logic is controlled by:

• R0x0C reset

Bit 0 is used to reset the digital logic of the sensor while

preserving the existing two−wire serial interface

configuration. Furthermore, by asserting the soft reset, the

sensor aborts the current frame it is processing and starts

a new frame. Bit 1 is a shadowed reset control register bit to

explicitly reset the automatic gain and exposure control

feature.

When AGC is enabled (R0xAF[1] = 1), the maximum

auto gain value is limited by R0x36; minimum auto gain is

fixed to 16 gain−units.

The exposure control measures current scene luminosity

and desired output luminosity by accumulating a histogram

of pixel values while reading out a frame. The desired

exposure and gain are then calculated from this for

subsequent frame.

These two bits are self−resetting bits and also return to “0”

during two−wire serial interface reads.

Pixel Clock Speed

STANDBY Control

The pixel clock speed is same as the master clock

(SYSCLK) at 26.66 MHz by default. However, when

column binning 2 or 4 (R0x0D, bit 2 or 3) is enabled, the

pixel clock speed is reduced by half and one−fourth of the

master clock speed respectively. See “Read Mode Options”

and “Column Binning” for additional information.

The sensor goes into standby mode by setting STANDBY

to HIGH. Once the sensor detects that STANDBY is

asserted, it completes the current frame before disabling the

digital logic, internal clocks, and analog power enable

signal. To release the sensor from the standby mode, reset

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MT9V032

STANDBY back to LOW. The LVDS must be powered to

continues until R0x0E bit 0 is cleared to return to normal

operation.

ensure that the device is in standby mode. See

“Appendix B – Power−On Reset and Standby Timing” for

more information on standby.

In some applications when monitor mode is enabled, the

purpose of capturing frames is to calibrate the gain and

exposure of the scene using automatic gain and exposure

control feature. This feature typically takes less than 10

frames to settle. In case a larger number of frames is needed,

the value of R0xC0 may be increased to capture more

frames.

During the sleep period, none of the analog circuitry and

a very small fraction of digital logic (including

a five−minute timer) is powered. The master clock

(SYSCLK) is therefore always required.

Monitor Mode Control

Monitor mode is controlled by:

• R0x0E monitor mode enable

• R0xC0 monitor mode image capture control

The sensor goes into monitor mode when R0x0E bit 0 is

set to HIGH. In this mode, the sensor first captures

a programmable number of frames (R0xC0), then goes into

a sleep period for five minutes. The cycle of sleeping for five

minutes and waking up to capture a number of frames

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MT9V032

READ MODE OPTIONS

Row Flip

(Also see “Output Data Format” and “Output Data

Timing”.)

By setting bit 4 of R0x0D the readout order of the rows is

reversed, as shown in Figure 29.

Column Flip

By setting bit 5 of R0x0D the readout order of the columns

is reversed, as shown in Figure 28.

LINE_VALID

Normal readout

P4,1

(9:0)

P4,2

(9:0)

P4,3

(9:0)

P4,4

(9:0)

P4,5

(9:0)

P4,6

(9:0)

D

)

(9:0)

OUT

Reverse readout

P4,n P4,n−1 P4,n−2

P4,n−4 P4,n−5

P4,n−3

(9:0)

D

(9:0)

DOUT(9:0

OUT

)

Figure 28. Readout of 6 Pixels in Normal and Column Flip Output Mode

LINE_VALID

Normal readout

Row4

(9:0)

Row5

(9:0)

Row6

(9:0)

Row7

(9:0)

Row8

7(9:0)

Row9

(9:0)

D

)

(9:0)

OUT

Reverse readout

Row482

(9:0)

Row483

(9:0)

Row480 Row479

Row481

(9:0)

Row484

(9:0)

D

)

(9:0)

OUT

7(9:0)

(9:0)

Figure 29. Readout of 6 Rows in Normal and Row Flip Output Mode

Pixel Binning

mode may work in conjunction with image flip. The binning

operation increases SNR but decreases resolution.

Enabling row bin2 and row bin4 improves frame rate by

2x and 4x respectively. The feature of column binning does

not increase the frame rate in less resolution modes.

In addition to windowing mode in which smaller

resolution (CIF, QCIF) is obtained by selecting small

window from the sensor array, the MT9V032 also provides

the ability to show the entire image captured by pixel array

with smaller resolution by pixel binning. Pixel binning is

based on combining signals from adjacent pixels by

averaging. There are two options: binning 2 and binning 4.

When binning 2 is on, 4 pixel signals from 2 adjacent rows

and columns are combined. In binning 4 mode, 16 pixels are

combined from 4 adjacent rows and columns. The image

Row Binning

By setting bit 0 or 1 of R0x0D, only half or one−fourth of

the row set is read out, as shown in Figure 30 below. The

number of rows read out is half or one−fourth of what is set

in R0x03.

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MT9V032

LINE_VALID

Normal readout

Row4

(9:0)

Row5

(9:0)

Row6

(9:0)

Row7

(9:0)

Row8

7(9:0)

Row9 Row10 Row11

(9:0) (9:0) (9:0)

D

(9:0)

OUT

LINE_VALID

Row Bin 2 readout

Row4 Row6 Row8 Row10

(9:0) (9:0) (9:0) (9:0)

D

(9:0)

OUT

LINE_VALID

Row Bin 4 readout

Row4 Row8

(9:0) (9:0)

D

(9:0)

OUT

Figure 30. Readout of 8 Pixels in Normal and Row bin Output Mode

Column Binning

In setting bit 2 or 3 of R0x0D, the pixel data rate is slowed

down by a factor of either two or four, respectively. This is

due to the overhead time in the digital pixel data processing

chain. As a result, the pixel clock speed is also reduced

accordingly.

LINE_VALID

Normal readout

D1 D2

D3

D4

D5

D6

D7

D8

(9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0)

D

)

(9:0)

OUT

PIXCLK

LINE_VALID

Column Bin 2 readout

D12

(9:0)

D34

(9:0)

D56

(9:0)

D78

(9:0)

D

(9:0

OUT

D

(9:0)

OUT

)

PIXCLK

LINE_VALID

Column Bin 4 readout

d1234

(9:0)

d5678

(9:0)

D

(9:0

OUT

D

(9:0)

OUT

)

PIXCLK

Figure 31. Readout of 8 Pixels in Normal and Column Bin Output Mode

Interlaced Readout

rows). By setting R0x07[2:0] = 2, only one field is read out;

consequently, the number of rows read out is half what is set

in R0x03. The row start address (R0x02) determines which

field gets read out; if the row start address is even, the even

field is read out; if row start address is odd, the odd field is

read out.

The MT9V032 has two interlaced readout options. By

setting R0x07[2:0] = 1, all the even−numbered rows are read

out first, followed by a number of programmable field

blanking (R0xBF, bits 7:0), and then the odd−numbered

rows and finally vertical blanking (minimum is 4 blanking

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MT9V032

P

…………P

P

4,n−1 4,n

00 00 00 ………… 00 00 00

4,1 4,2 4,3

P

…………P

P

6,0 6,1 6,2

6,n−1 6,n

VALID IMAGE − Even Field

………P

P

m−2,n−2 m−2,n

HORIZONTAL

BLANKING

m−2,0 m−2,2

P

…………P

P

m,2 m,2

m,n−1 m,n

00 00 00 …………………… 00 00 00

FIELD BLANKING

P

…………P

P

5,1 5,2 5,3

5,n−1 5,n

00 00 00 ………… 00 00 00

P

7,n−1 7,n

7,0 7,1 7,2

VALID IMAGE − Odd Field

………P P

00 00 00 ………… 00 00 00

P

m−3,1 m−3,2

m−3,n−1 m−3,n

P

…………P

P

m,1 m,1

m,n−1 m,n

VERTICAL BLANKING

00 00 00 ……………………………… 00 00 00

Figure 32. Spatial Illustration of Interlaced Image Readout

When interlaced mode is enabled, the total number of

blanking rows are determined by both field blanking register

(R0xBF) and vertical blanking register (R0x06). The

followings are their equations.

Field Blanking + R0xBF, bits 7 : 0

(eq. 16)

Vertical Blanking + R0x06, bits 8 : 0 * R0xBF, bits 7 : 0

(eq. 17)

with

minimum vertical blanking requirement + 4

(eq. 18)

Similar to progressive scan, FRAME_VALID is logic

LOW during the valid image row only. Binning should not

be used in conjunction with interlaced mode.

reading out four rows and two vertical blanking rows are

shown in Figure 33. In the last format, the LINE_VALID

signal is the XOR between the continuous LINE_VALID

signal and the FRAME_VALID signal.

LINE_VALID

By setting bit 2 and 3 of R0x74, the LINE_VALID signal

can get three different output formats. The formats for

Default

FRAME_VALID

LINE_VALID

Continuously

FRAME_VALID

LINE_VALID

XOR

FRAME_VALID

LINE_VALID

Figure 33. Different LINE_VALID Formats

LVDS Serial (Stand−Alone/Stereo) Output

either be data from a single sensor (stand−alone) or

stream−merged data from two sensors (self and its

stereoscopic slave pair). The appendices describe in detail

the topologies for both stand−alone and stereoscopic modes.

There are two standard deserializers that can be used. One

for a stand−alone sensor stream and the other from a

stereoscopic stream. The deserializer attached to a

The LVDS interface allows for the streaming of sensor

data serially to a standard off−the−shelf deserializer up to

five meters away from the sensor. The pixels (and controls)

are packeted—12−bit packets for stand−alone mode and

18−bit packets for stereoscopy mode. All serial signalling

(CLK and data) is LVDS. The LVDS serial output could

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47

MT9V032

stand−alone sensor is able to reproduce the standard parallel

writes through the two−wire serial interface are done in such

a way that both sensors can get their configuration updates

at once. The inter−sensor serial link is designed in such a

way that once the slave PLL locks and the data−dly,

shft−clk−dly and stream−latency−sel are configured, the

master sensor streams good stereo content irrespective of

any variation voltage and/or temperature as long as it is

within specification. The configuration values of data−dly,

output (8−bit pixel data, LINE_VALID, FRAME_VALID

and PIXCLK). The deserializer attached to a stereoscopic

sensor is able to reproduce 8−bit pixel data from each sensor

(with embedded LINE_VALID and FRAME_VALID) and

pixel−clk. An additional (simple) piece of logic is required

to extract LINE_VALID and FRAME_VALID from the

8−bit pixel data. Irrespective of the mode

(stereoscopy/stand−alone),

LINE_VALID

and

shft−clk−dly and

stream−latency−sel are

either

FRAME_VALID are always embedded in the pixel data.

In stereoscopic mode, the two sensors run in lock−step,

implying all state machines are in the same state at any given

time. This is ensured by the sensor−pair getting their

sys−clks and sys−resets in the same instance. Configuration

predetermined from the board layout or can be empirically

determined by reading back the stereo−error flag. This flag

gets asserted when the two sensor streams are not in sync

when merged. The combo_reg is used for out−of−sync

diagnosis.

Internal

PIXCLK

Internal

Parallel

Data

P41 P42 P43 P44 P45 P46

P51 P52 P53 P54 P55 P56

Internal

Line_Valid

Internal

Frame_Valid

External

Serial

1023

0

1023

1

P41 P42 P43 P44 P45 P46

2

1

P51 P52 P53 P54 P55 P56

3

Data Out

NOTES: 1. External pixel values of 0, 1, 2, 3, are reserved (they only convey control information).

Any raw pixel of value 0, 1, 2 and 3 will be substituted with 4.

2. The external pixel sequence 1023, 0 1023 is a reserved sequence (conveys control

information). Any raw pixel sequence of 1023, 0, 1023 will be substituted with 1023, 4, 1023.

Figure 34. Serial Output Format for 6x2 Frame

LVDS Output Format

consists of a start bit, 8−bit pixel data (with sync codes), the

line valid bit, the frame valid bit and the stop bit. For 10−bit

pixel mode (R0xB6[0] = 1), the packet consists of a start bit,

10−bit pixel data, and the stop bit.

In stand−alone mode, the packet size is 12 bits (2 frame

bits and 10 payload bits); 10−bit pixels or 8−bit pixels can be

selected. In 8−bit pixel mode (R0xB6[0] = 0), the packet

Table 9. LVDS PACKET FORMAT IN STAND−ALONE MODE (Stereoscopy Mode Bit De−Asserted)

Use_10−bit_pixels Bit De−Asserted

(8−Bit Mode)

Use_10−bit_pixels Bit Asserted

12 Bit Packet

Bit[0]

(10−Bit Mode)

1’b1(Start bit)

PixelData[0]

PixelData[1]

PixelData[2]

PixelData[3]

PixelData[4]

PixelData[5]

PixelData[6]

PixelData[7]

PixelData[8]

PixelData[9]

1’b0(Stop bit)

1’b1(Start bit)

PixelData[2]

PixelData[3]

PixelData[4]

PixelData[5]

PixelData[6]

PixelData[7]

PixelData[8]

PixelData[9]

Line_Valid

Bit[1]

Bit[2]

Bit[3]

Bit[4]

Bit[5]

Bit[6]

Bit[7]

Bit[8]

Bit[9]

Bit[10]

Bit[11]

Frame_Valid

1’b0(Stop bit)

In stereoscopic mode (see Figure 47), the packet size is 18

bits (2 frame bits and 16 payload bits). The packet consists

of a start bit, the master pixel byte (with sync codes), the

slave byte (with sync codes), and the stop bit.)

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MT9V032

Table 10. LVDS PACKET FORMAT IN STEREOSCOPY MODE (Stereoscopy Mode Bit Asserted)

18−bit Packet

Function

Bit[0]

1’b1 (Start bit)

Bit[1]

Bit[2]

Master Sensor Pixel Data [2]

Master Sensor Pixel Data [3]

Master Sensor Pixel Data [4]

Master Sensor Pixel Data [5]

Master Sensor Pixel Data [6]

Master Sensor Pixel Data [7]

Master Sensor Pixel Data [8]

Master Sensor Pixel Data [9]

Slave Sensor Pixel Data [2]

Slave Sensor Pixel Data [3]

Slave Sensor Pixel Data [4]

Slave Sensor Pixel Data [5]

Slave Sensor Pixel Data [6]

Slave Sensor Pixel Data [7]

Slave Sensor Pixel Data [8]

Slave Sensor Pixel Data [9]

1’b0 (Stop bit)

Bit[3]

Bit[4]

Bit[5]

Bit[6]

Bit[7]

Bit[8]

Bit[9]

Bit[10]

Bit[11]

Bit[12]

Bit[13]

Bit[14]

Bit[15]

Bit[16]

Bit[17]

Control signals LINE_VALID and FRAME_VALID can

be reconstructed from their respective preceding and

succeeding flags that are always embedded within the pixel

data in the form of reserved words.

Table 11. RESERVED WORDS IN THE PIXEL DATA STREAM

Pixel Data Reserved Word

Flag

Precedes frame valid assertion

Precedes line valid assertion

0

1

2

3

Succeeds line valid de−assertion

Succeeds frame valid de−assertion

When LVDS mode is enabled along with column binning

(bin 2 or bin 4, R0x0D[3:2]), the packet size remains the

same but the serial pixel data stream repeats itself depending

on whether 2X or 4X binning is set:

• For bin 2, LVDS outputs double the expected data

(pixel 0,0 is output twice in sequence, followed by pixel

0,1 twice, . . .).

The receiving hardware will need to undersample the

output stream getting data either every 2 clocks (bin 2) or

every 4 (bin 4) clocks.

If the sensor provides a pixel whose value is 0,1, 2, or 3

(that is, the same as a reserved word) then the outgoing serial

pixel value is switched to 4

• For bin 4, LVDS outputs 4 times the expected data

(pixel 0,0 is output 4 times in sequence followed by

pixel 0,1 times 4, . . .).

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MT9V032

ELECTRICAL SPECIFICATIONS

Table 12. DC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V +0.3V; T_A= Ambient = 25°C)

Typi

cal

Symbol

Definition

Condition

Minimum

Maximum

Unit

VIH

Input high voltage

VPWR − 0.5

–

VPWR + 0.3

V

VIL

Input low voltage

–0.3

0.8

V

No pull−up resistor;

VIN = VPWR or VGND

15.0

mA

IIN

Input leakage current

–15.0

VOH

VOL

Output high voltage

Output low voltage

Output high current

Output low current

Analog power supply

Analog supply current

Digital power supply

Digital supply current

IOH = –4.0mA

VPWR −0.7

–

0.3

–

V

IOL = 4.0mA

–

–9.0

–

IOH

VOH = VDD − 0.7

VOL = 0.7

–

mA

V

IOL

–

9.0

3.6

60.0

3.6

60

VAA

Default settings

Default settings, CLOAD= 10pF

3.0

–

3.3

35.0

3.3

35.0

3.3

IPWRA

VDD

mA

V

3.0

–

mA

V

IPWRD

Pixel array power sup-

ply

3.6

VAAPIX

Default settings

3.0

1.4

3.3

13.0

3

3.0

3.6

15.0

4

mA

V

IPIX

Pixel supply current

LVDS power supply

LVDS supply current

Default settings

0.5

3.0

VLVDS

ILVDS

11.0

mA

Analog standby supply

current

IPWRA Standby

STDBY = VDD

2

1

–

IPWRD Standby

Clock Off

Digital standby supply

current with clock off

2

4

–

mA

STDBY = VDD, CLKIN = 0 MHz

STDBY= VDD, CLKIN = 27 MHz

IPWRD Standby

Clock On

Digital standby supply

current with clock on

1.05

mA

LVDS DRIVER DC SPECIFICATIONS

Output differential volt-

–

400

50

mV

|VOD|

age

250

Change in VOD between

complementary output

states

|DVOD|

VOS

RLOAD = 100

–

Output offset voltage

1.0

1.2

–

1.4

35

mV

W

1%

Change in VOS between

complementary output

states

DVOS

–

10

1

12

10

Output current when

mA

IOS

IOZ

driver shorted to ground

Output current when

driver is tri−state

mA

LVDS RECEIVER DC SPECIFICATIONS

| VGPD| < 925mV

–

100

20

mV

Input differential

Input current

VIDTH+

–100

–

mA

Iin

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MT9V032

Table 13. ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Minimum

Maximum

Unit

VSUPPLY

Power supply voltage (all supplies)

–0.3

–

4.5

V

ISUPPLY

IGND

Total power supply current

Total ground current

DC input voltage

200

mA

V

–

VIN

–0.3

–40

VDD + 0.3

+125

VOUT

DC output voltage

V

1

TSTG

Storage temperature

°C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

5. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Table 14. AC ELECTRICAL CHARACTERISTICS (VPWR = 3.3V 0.3V; T = Ambient = 25°C; Output Load = 10pF)

A

Definition

Symbol

Condition

Min

Typ

Max

Unit

SYSCLK

Input clock frequency

Note 1

13.0

26.6

27.0

MHz

Clock duty cycle

Input clock rise time

Input clock fall time

45.0

50.0

55.0

5

%

ns

t

1

3

2

7

R

t

5

F

SYSCLK to PIXCLK

propagation delay

11

CLOAD = 10pF

tPLHP

tPD

PIXCLK to valid DOUT(9:0)

propagation delay

–2

0

2

ns

tSD

tHD

Data setup time

Data hold time

14

–2

16

0

–

2

ns

PIXCLK to LINE_VALID

propagation delay

CLOAD = 10pF

tPFLR

tPFLF

PIXCLK to FRAME_VALID

propagation delay

–2

0

2

ns

6. The frequency range specified applies only to the parallel output mode of operation.

Propagation Delays for PIXCLK and Data Out Signals

The pixel clock is inverted and delayed relative to the

master clock. The relative delay from the master clock

(SYSCLK) rising edge to both the pixel clock (PIXCLK)

falling edge and the data output transition is typically 7ns.

Note that the falling edge of the pixel clock occurs at

approximately the same time as the data output transitions.

See Table 14 for data setup and hold times.

Propagation Delays for FRAME_VALID and

LINE_VALID Signals

The LINE_VALID and FRAME_VALID signals change

on the same rising master clock edge as the data output. The

LINE_VALID goes HIGH on the same rising master clock

edge as the output of the first valid pixel’s data and returns

LOW on the same master clock rising edge as the end of the

output of the last valid pixel’s data.

As shown in the Output Data Timing, FRAME_VALID

goes HIGH 143 pixel clocks before the first

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51

MT9V032

t

R

F

SYSCLK

PIXCLK

t

PLH

P

t

PD

t

SD

HD

D

(9:0)

OUT

Figure 35. Propagation Delays for PIXCLK and Data Out Signals

t

PFLR

PFLF

PIXCLK

FRAME_VALID

LINE_VALID

FRAME_VALID

LINE_VALID

Figure 36. Propagation Delays for FRAME_VALID and LINE_VALID Signals

Performance Specifications

Table 15 summarizes the specification for each

performance parameter.

Table 15. PERFORMANCE SPECIFICATIONS

Parameter

Sensitivity

DSNU

Unit

LSB

%

Minimum

400

Typical

572

Maximum

745

Test Number

1

2

3

4

5

N/A

2.3

7.0

PRNU

N/A

1.3

4.0

Dynamic Range

SNR

dB

52.0

54.4

37.3

N/A

dB

33.0

N/A

NOTES: All specifications address operation is at T = 25°C ( 3°C) and supply voltage = 3.3V. Image sensor was tested without a lens.

A

Multiple images were captured and analyzed.

Setup: VDD = VAA = VAAPIX = LVDSVDD = 3.3V. Testing was done with default frame timing and default register settings, with

the exception of AEC/AGC, row noise correction, and auto black level, which were disabled.

Performance definitions are detailed in the following sections.

Test 1: Sensitivity

Test 3: Photo Response Nonuniformity (PRNU)

A flat−field light source (90 lux, color temperature

4400K, broadband, with IR cut filter) is used as an

illumination source. Signals are measured in LSB on the

sensor output. Two series of four frames are captured and

averaged (pixel−by−pixel) into one average frame, one

series is captured under illuminated conditions, and one is

captured in the dark. PRNU is expressed as a percentage

relating the standard deviation of the average frames

difference (illuminated frame − dark frame) to the average

illumination level:

A flat−field light source (90 lux, color temperature

4400K, broadband, w/ IR cut filter) is used as an

illumination source. Signals are measured in LSB on the

sensor output. A series of four frames are captured and

averaged to obtain a scalar sensitivity output code.

Test 2: Dark Signal Nonuniformity (DSNU)

The image sensor is held in the dark. Analog gain is

changed to the maximum setting of 4X. Signals are

measured in LSB on the sensor output. A series of four

frames are captured and averaged (pixel−by−pixel) into one

average frame. DSNU is calculated as the standard deviation

of this average frame.

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MT9V032

Where ꢀ is the temporal noise measured in the dark at 4X

gain.

t

N

1

p

ǒ

Ǔ²

_@ȍ

Ǹ

S_illumination(i) * S_dark(i)

N

i+1

p

(eq. 19)

PRNU + 100

N

p

1

ȍ

_i+1(S_illumination

Test 5: Signal−to−Noise Ratio

(i))

N_p

A flat−field light source (90 lux, color temperature

4400K, broadband, with IR cut filter) is used as an

illumination source. Signals are measured in LSB on the

sensor output. Two consecutive illuminated frames are

captured. Temporal noise is calculated as the average pixel

value of the difference frame (according to the formula

shown in Test 4).

The signal−to−noise ratio is calculated as the ratio of the

average signal level to the temporal noise according to the

following formula:

WhereS

(i) is the signal measured for the i−th pixel

from the average illuminated frame, S

measured for the i−th pixel from the average dark frame, and

N is the total number of pixels contained in the array.

illumination

is the signal

dark

p

Test 4: Dynamic Range

A temporal noise measurement is made with the image

sensor in the dark and analog gain changed to the maximum

setting of 4X. Signals are measured in LSB on the sensor

output. Two consecutive dark frames are captured.

Temporal noise is calculated as the average pixel value of the

difference frame:

₍₍ȍ

N_pi+1S_1i)ńN_p)

.

(eq. 22)

Signal * to * Noise * Ratio + 20 log

s

t

N_pi+1(S_1i* S_2i)²

t

_{s +}Ǹ^ȍ

(eq. 20)

Where σ is the temporal noise measured from the

i

illuminated frames, S is the signal measured for the i−th

1i

2 @ N_p

pixel from the first frame, and N is the total number of

p

Where S is the signal measured for the i−th pixel from the

pixels contained in the array.

1i

first frame, S is the signal measured for the i−th pixel from

2i

Two−Wire Serial Bus Timing

the second frame, and N is the total number of pixels

p

The two−wire serial bus operation requires certain

minimum master clock cycles between transitions. These

are specified in the following diagrams in master clock

cycles.

contained in the array.

The dynamic range is calculated according to the

following formula:

(4 1022)

.

(eq. 21)

DynamicRange + 20 log

s

t

4

SCLK

S_DATA

Figure 37. Serial Host Interface Start Condition Timing

4

SCLK

SDATA

NOTE: All timing are in units of master clock cycle.

Figure 38. Serial Host Interface Stop Condition Timing

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53

MT9V032

4

SCLK

SDATA

NOTE: SDATA is driven by an off-chip transmitter.

Figure 39. Serial Host Interface Data Timing for WRITE

5

SCLK

SDATA

NOTE: SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor off-chip.

Figure 40. Serial Host Interface Data Timing for READ

6

3

SCLK

SDATA

Sensor pulls down

SDATA pin

Figure 41. Acknowledge Signal Timing After an 8-Bit WRITE to the Sensor

7

6

SCLK

S^DATA

Sensor tri−states S^DATApin

(turns off pull down)

NOTE: After a READ, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is

complete, the master must generate a “No Acknowledge” by leaving SDATA to float HIGH. On the following cycle,

a start or stop bit may be used.

Figure 42. Acknowledge Signal Timing After an 8-Bit READ from the Sensor

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54

MT9V032

TEMPERATURE REFERENCE

The MT9V032 contains a temperature reference circuit

that can be used to measure relative temperatures. Contact

your ON Semiconductor field applications engineer (FAE)

for more information on using this circuit.

40

Blue

35

30

Green (B)

Green (R)

Red

25

20

15

10

5

0

350

450

550

650

750

850

950

1050

Wavelength (nm)

Figure 43. Typical Quantum Efficiency − Color

60

50

40

30

20

10

0

350

450

550

650

750

850

950

1050

Wavelength (nm)

Figure 44. Typical Quantum Efficiency − Monochrome

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MT9V032

2.3 0.2

D

A

1.7

Seating

plane

8.8

48X R 0.15

1.75

0.8

TYP

4.4

47X

1.0 0.2

48

1

48X

0.40 0.05

5.215

4.84

11.43

8.8

4X

4.4

5.715

0.8 TYP

0.2

5.215

5.715

C

11.43

B

Lead finish:

Au plating, 0.50 microns

minimum thickness

over Ni plating, 1.27 microns

minimum thickness

Substrate material: alumina ceramic 0.7 thickness

Wall material: alumina ceramic

Lid material: borosilicate glass 0.55 thickness

H CTR

∅0.20

First

A B C

clear

pixel

V CTR

A B C

10.9 0.1

CTR

∅0.20

Image

sensor die:

0.675 thickness

Optical

A

1

center

10.9 0.1

CTR

area

0.05

0.10 A

Optical area:

1.400 0.125

Maximum rotation of optical area relative to package edges: 1º

Maximum tilt of optical area relative to seating plane A:50 microns

Maximum tilt of optical area relative to top of cover glass D:100 microns

Note: 1. Optical center = package center

0.90

for reference only

0.35

for reference only

NOTES: 1. All dimensions in millimeters.

2. Optical center = Package center

Figure 45. Package Mechanical Drawing (CASE 848AQ)

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MT9V032

APPENDIX A − SERIAL CONFIGURATIONS

With the LVDS serial video output, the deserializer can be

up to 8 meters from the sensor. The serial link can save on

the cabling cost of 14 wires (D^OUT[9:0], LINE_VALID,

FRAME_VALID, PIXCLK, GND). Instead, just three wires

(two serial LVDS, one GND) are sufficient to carry the video

signal.

SER_DATAOUT_N must be connected to a deserializer

(clocked at approximately the same system clock

frequency).

Figure46 shows how a standard off−the−shelf deserializer

(National Semiconductor DS92LV1212A) can be used to

retrieve the standard parallel video signals of D^OUT(9:0),

LINE_VALID and FRAME_VALID.

Configuration of Sensor for Stand − Alone Serial

Output with Internal PLL

In this configuration, the internal PLL generates the

shift−clk (x12). The LVDS pins SER_DATAOUT_P and

26.6 Mhz

CLK

Osc.

LVDS

SER_DATAIN

Sensor

LVDS

BYPASS_CLKIN

LVDS

SER_DATAOUT

8 meters (maximum)

SHIFT_CLKOUT

26.6 Mhz

Osc.

DS92LV1212A

8

2

PIXEL

LINE_VALID

FRAME_VALID

8−bit configuration shown

Figure 46. Stand−Alone Topology

Typical configuration of the sensor:

1. Power up sensor.

pins SER_DATAOUT_P and SER_DATAOUT_N must be

connected to a deserializer (clocked at approximately the

same system clock frequency).

Figure47 shows how a standard off−the−shelf deserializer

can be used to retrieve back D^OUT(9:2) for both the master

and slave sensors. Additional logic is required to extract out

LINE_VALID and FRAME_VALID embedded within the

pixel data stream.

2. Enable LVDS driver (set R0xB3[4]= 0).

3. De−assert LVDS power−down (set R0xB1[1] = 0.

4. Issue a soft reset (set R0x0C[0] = 1 followed by

R0x0C[0] = 0.

If necessary:

5. Force sync patterns for the deserializer to lock (set

R0xB5[0] = 1).

6. Stop applying sync patterns (set R0xB5[0] = 0).

Configuration of Sensor for

Stereoscopic Serial Output with Internal

PPL

In this configuration the internal PLL generates the

shift−clk (x18) in phase with the system−clock. The LVDS

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MT9V032

MASTER

SENSOR

SLAVE

26.6 MHz

Osc.

LVDS

SER_DATAIN

LVDS

SER_DATAIN

LVDS

BYPASS_CLKIN

SENSOR

LVDS

BYPASS_CLKIN

LVDS

SER_DATAOUT

SHIFT_CLKOUT

5 meters (maximum)

LVDS

SER_DATAOUT

LVDS

SHIFT_CLKOUT

26.6 MHz

Osc.

DS92LV16

8

2

PIXEL

FROM

SLAVE

PIXEL

FROM

MASTER

LV and FV are embedded in the data stream

Figure 47. Stereoscopic Topology

Typical configuration of the master and slave sensors:

1. Power up the sensors.

R0xB3[2:0], and R0xB4[1:0] appropriately). Use

R0xB7 and R0xB8 to get lockstep feedback from

stereo_error_flag.

2. Broadcast WRITE to de−assert LVDS

power−down (set R0xB1[1] = 0).

3. Individual WRITE to master sensor putting its

internal PLL into bypass mode (set R0xB1[0] = 1).

4. Broadcast WRITE to both sensors to set the

stereoscopy bit (set R0x07[5] = 1).

5. Make sure all resolution, vertical blanking,

horizontal blanking, window size, and AEC/AGC

configurations are done through broadcast WRITE

to maintain lockstep.

6. Broadcast WRITE to enable LVDS driver (set

R0xB3[4] = 0).

7. Broadcast WRITE to enable LVDS receiver (set

R0xB2[4] = 0).

8. Individual WRITE to master sensor, putting its

internal PLL into bypass mode (set R0xB1[0] = 1).

9. Individual WRITE to slave sensor, enabling its

internal PLL (set R0xB1[0] = 0).

10. Individual WRITE to slave sensor, setting it as a

stereo slave (set R0x07[6] = 1).

11. Individual WRITEs to master sensor to minimize

the inter−sensor skew (set R0xB2[2:0],

12. Broadcast WRITE to issue a soft reset (set

R0x0C[0] = 1 followed by R0x0C[0] = 0).

NOTE: The stereo_error_flag is set if a mismatch has

occurred at a reserved byte (slave and master

sensor’s codes at this reserved byte must match).

If the flag is set, steps 11 and 12 are repeated

until the stereo_error_flag remains cleared.

Broadcast and Individual Writes for Stereoscopic

Topology

In stereoscopic mode, the two sensors are required to run

in lockstep. This implies that control logic in each sensor is

in exactly the same state as its pair on every clock. To ensure

this, all inputs that affect control logic must be identical and

arrive at the same time at each sensor.

These inputs include:

• system clock

• system reset

• two−wire serial interface clk − SCL

• two−wire serial interface data − SDA

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MT9V032

L

26.6 MHz

Osc.

S_CTRL_ADR[0] CLK

S_CTRL_ADR[0]

CLK

L

MASTER

SENSOR

SLAVE

SENSOR

CLK

SCL

SDA

SCL

SDA

HOST

SCL

SDA

Host launches SCL and SDA on positive

edge of SYSCLK

All system clock lengths (L) must be equal.

SCL and SDA lengths to each sensor (from the host) must also be equal.

Figure 48. Two−Wire Serial Interface Configuration in Stereoscopic Mode

The setup in Figure 48 shows how the two sensors can

allows the host to perform either a broadcast or a one−to−one

access.

Broadcast WRITES are performed by setting the same

S_CTRL_ADR input bit for both slave and master sensor.

Individual WRITES are performed by setting opposite

S_CTRL_ADR input bit for both slave and master sensor.

Similarly, individual READs are performed by setting

opposite S_CTRL_ADR input bit for both slave and master

sensor.

maintain lockstep when their configuration registers are

written through the two−wire serial interface. A WRITE to

configuration registers would either be broadcast

(simultaneous WRITES to both sensors) or individual

(WRITE to just one sensor at a time). READs from

configuration registers would be individual (READs from

just one sensor at a time).

One of the two serial interface slave address bits of the

sensor is hardwired. The other is controlled by the host. This

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59

MT9V032

APPENDIX B − POWER−ON RESET AND STANDBY TIMING

Reset, Clocks, and Standby

There are no constraints concerning the order in which the

various power supplies are applied; however, the MT9V032

requires reset in order operate properly at power−up. Refer

to Figure 49 for the power−up, reset, and standby sequences.

non−Low−Power

Low−Power

non−Low−Power

Wake

up

Power

down

Power

up

Standby

Active

Pre−Standby

V

LVDS

DD, DD

V

AA,

VAAPIX

MIN 20 SYSCLK cycles

RESET #

Note 3

STANDBY

MIN 10 SYSCLK cycles

SYSCLK

MIN 10 SYSCLK cycles

Does not

respond to

serial

interface

when

SCLK, S

DATA

Two−Wire Serial I/F

STANDBY = 1

D

[9:0]

OUT

D

[9:0]

OUT

Driven = 0

DATA OUTPUT

1. All output signals are defined during initial power−up with RESET# held LOW without SYSCLK being active. To properly

reset the rest of the sensor, during initial power−up, assert RESET# (set to LOW state) for at least 750ns after all power

supplies have stabilized and SYSCLK is active (being clocked). Driving RESET# to LOW state does not put the part in

a low power state.

2. Before using two−wire serial interface,wait for 10 SYSCLK rising edges after RESET# is de−asserted.

3. Once the sensor detects that STANDBY has been asserted, it completes the current frame readout before entering

standby mode. The user must supply enough SYSCLKs to allow a complete frame raedout. See Table 4, “Frame Time,”

for more information.

4. In standby, all video data and synchronization output signals are High−Z.

5. In standby, the two−wire serial interface is not active.

Figure 49. Power−up, Reset, Clock and Standby Sequence

Standby Assertion Restrictions

maintaining STANDBY assertion for a minimum

of one frame period.

2. Asserting STANDBY at the end of valid frame

readout (falling edge of FRAME_VALID) and

maintaining STANDBY assertion for a minimum

of [5 + R0x06] row−times.

STANDBY cannot be asserted at any time. If STANDBY

is asserted during a specific window within the vertical

blanking period, the MT9V032 may enter a permanent

standby state. This window (that is, dead zone) occurs prior

to the beginning of the new frame readout. The permanent

standby state is identified by the absence of the

FRAME_VALID signal on frame readouts. Issuing a

hardware reset (RESET# set to LOW state) will return the

image sensor to default startup conditions.

When STANDBY is asserted during the vertical blanking

period (FRAME_VALID is LOW), the STANDBY signal

must not change state between [Vertical Blanking Register

(R0x06) − 5] row−times and [Vertical Blanking Register

+ 5] row−times after the falling edge of FRAME_VALID.

This dead zone can be avoided by:

1. Asserting STANDBY during the valid frame

readout time (FRAME_VALID is HIGH) and

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60

MT9V032

Dead Zone

10 row−times

5 row−times

FRAME_VALID

Vertical Blanking Period

(R0x06) row−times

Figure 50. STANDBY Restricted Location

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MT9V032/D

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61


型号：	MT9V032C12STCH-GEVB
厂家：	ONSEMI
描述：	1/3âInch Wide VGA CMOS Digital Image Sensor
文件：	总61页 (文件大小：371K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT9V032C12STCH-GEVB [ONSEMI]

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