N01L6183AT27IT [ONSEMI]
1Mb Ultra-Low Power Asynchronous CMOS SRAM; 1MB超低功耗异步SRAM CMOS
| 型号： | N01L6183AT27IT |
| 厂家： | 
ONSEMI |
| 描述： | 1Mb Ultra-Low Power Asynchronous CMOS SRAM |
| 文件： | 总10页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N01L6183A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Features
Overview
• Single Wide Power Supply Range
1.65 to 2.2 Volts
The N01L6183A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 65,536 words by 16 bits. The device
is designed and fabricated using ON
• Very low standby current
0.5µA at 1.8V (Typical)
• Very low operating current
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N01L6183A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
0.7mA at 1.8V and 1µs (Typical)
• Very low Page Mode operating current
0.5mA at 1.8V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.2V
o
o
temperature range of -40 C to +85 C and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Standby
Operating
Current (Icc),
Typical
Operating
Power
Current (ISB),
Part Number
Package Type
Speed
Temperature Supply (Vcc)
Typical
N01L6183AB
N01L6183AT
N01L6183AB2
N01L6183AT2
48 - BGA
44 - TSOP II
70ns @ 1.8V
85ns @ 1.65V
0.7 mA @
1MHz
-40oC to +85oC
1.65V - 2.2V
0.5 µA
48 - BGA Green
44 - TSOP II Green
Pin Configurations
Pin Descriptions
1
2
3
A0
A3
4
A1
A4
A6
A7
NC
5
A2
6
A4
1
PIN
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
ONE
A6
A2
3
LB
OE
NC
A7
A
B
C
D
E
F
A1
4
OE
Pin Name
A0-A15
Pin Function
A0
5
UB
I/O8
I/O0
UB
CE
CE
6
LB
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
7
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
I/O9 I/O10 A5
I/O1 I/O2
I/O3 VCC
I/O4 VSS
8
WE
CE
OE
LB
UB
9
VSS I/O11
VCC I/O12
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
I/O14 I/O13 A14
A15 I/O5 I/O6
I/O15
NC
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
A8
I/O0-I/O15
A9
A10
A11
NC
VCC
VSS
48 Pin BGA (top)
6 x 8 mm
NC
Power
Ground
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 8
Publication Order Number:
N01L6183A/D
N01L6183A
Functional Block Diagram
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Output
Mux
Page
4K Page
x 16 word
x 16 bit
Address
Inputs
Address
Decode
Logic
I/O0 - I/O7
A4 - A15
and
RAM Array
Buffers
I/O8 - I/O15
CE
WE
OE
UB
LB
Control
Logic
Functional Description
1
CE
WE
OE
UB
LB
MODE
POWER
I/O0 - I/O15
Standby2
Active
Write3
Read
Active
H
L
L
L
L
X
X
L
X
X
X3
X
H
L1
L1
L1
X
H
L1
L1
L1
High Z
High Z
Data In
Data Out
High Z
Standby
Active
Active -> Standby4
Active -> Standby4
Standby4
H
H
L
H
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any
external influence.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
Rev. 8 | Page 2 of 10 | www.onsemi.com
N01L6183A
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 3.0
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
260oC, 10sec
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Typ1
Item
Symbol
Test Conditions
Min.
Max
Unit
VCC
VDR
VIH
VIL
Supply Voltage
Data Retention Voltage
Input High Voltage
1.65
1.2
0.7VCC
1.8
2.2
V
V
Chip Disabled3
VCC+0.3
0.3VCC
V
Input Low Voltage
–0.3
V
VOH
VOL
ILI
IOH = 0.2mA
IOL = -0.2mA
VCC–0.3
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
0.3
0.5
0.5
V
VIN = 0 to VCC
µA
µA
ILO
OE = VIH or Chip Disabled
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
ICC1
ICC2
0.7
8
3.0
16
mA
mA
@ 1 µs Cycle Time2
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
@ 85 ns Cycle Time2
Page Mode Operating Supply Current
@ 85ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
ICC3
3
mA
µA
VCC=2.2 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f = 0
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
20
VIN = VCC or 0V
Chip Disabled
Maximum Standby Current3
ISB1
0.5
10
5
µA
µA
tA= 85oC, VCC = 2.2 V
VCC = 1.2V, VIN = VCC or 0
Chip Disabled, tA= 85oC
Maximum Data Retention Current3
IDR
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and are not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE high). In order to achieve low standby current all inputs must be
within 0.2 volts of either VCC or VSS
Rev. 8 | Page 3 of 10 | www.onsemi.com
N01L6183A
Power Savings with Page Mode Operation (WE = V )
IH
Page Address (A4 - A15 )
Word Address (A0 - A3)
CE
Open page
...
Word 16
Word 1
Word 2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev. 8 | Page 4 of 10 | www.onsemi.com
N01L6183A
Timing Test Conditions
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 30pF
-40 to +85 oC
Operating Temperature
Timing
1.65 - 2.2 V
1.8 - 2.2 V
Item
Symbol
Units
Min.
Max.
Min.
Max.
tRC
tAA
Read Cycle Time
85
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
85
85
35
30
70
70
30
25
tCO
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
tOE
tLB, tUB
tLZ
10
5
10
5
tOLZ
tLBZ, tUBZ
tHZ
10
10
30
30
30
25
25
25
tOHZ
tLBHZ, tUBHZ
tOH
5
5
tWC
85
50
50
50
50
0
70
40
40
40
40
0
tCW
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tAW
t
LBW, tUBW
tWP
tAS
Address Setup Time
tWR
Write Recovery Time
0
0
tWHZ
tDW
Write to High-Z Output
25
20
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
35
0
tDH
tOW
10
10
ns
Rev. 8 | Page 5 of 10 | www.onsemi.com
N01L6183A
Timing of Read Cycle (CE = OE = V , WE = V )
IL
IH
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Timing Waveform of Read Cycle (WE= V )
IH
t
RC
Address
t
AA
t
HZ
t
CO
CE
OE
t
LZ
t
OHZ
t
OE
t
OLZ
t
t
LB, UB
LB, UB
t
t
t
t
LBLZ, UBLZ
LBHZ, UBHZ
High-Z
Data Valid
Data Out
Rev. 8 | Page 6 of 10 | www.onsemi.com
N01L6183A
Timing Waveform of Write Cycle (WE control)
t
WC
Address
t
WR
t
AW
t
CW
CE
t
, t
LBW UBW
LB, UB
t
WP
t
AS
WE
t
t
DH
DW
High-Z
Data Valid
Data In
Data Out
t
WHZ
t
OW
High-Z
Timing Waveform of Write Cycle (CE Control)
t
WC
Address
CE
t
t
AW
WR
t
CW
t
AS
t
, t
LBW UBW
UB, LB
WE
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
t
WHZ
High-Z
Data Out
Rev. 8 | Page 7 of 10 | www.onsemi.com
N01L6183A
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
SEE DETAIL B
DETAIL B
1.10±0.15
o
o
0 -8
0.20
0.00
0.80mm REF
Note:
1. All dimensions in millimeters
2. Package dimensions exclude molding flash
Rev. 8 | Page 8 of 10 | www.onsemi.com
N01L6183A
Ball Grid Array Package
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
Z
0.05
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
6±0.10
8±0.10
0.375
0.375
1.125
1.375
FULL
Rev. 8 | Page 9 of 10 | www.onsemi.com
N01L6183A
Ordering Information
Part Number
Package
Shipping Method
N01L6183AT7I
N01L6183AT27I
N01L6183AB7I
N01L6183AB27I
N01L6183AT7IT
N01L6183AT27IT
N01L6183AB7IT
N01L6183AB27IT
Leaded 44-TSOP II
Green 44-TSOP II (RoHS Compliant)
Leaded 48-BGA
Green 48-BGA (RoHS Compliant)
Leaded 44-TSOP II
Green 44-TSOP II (RoHS Compliant)
Leaded 48-BGA
Tray
Tray
Tray
Tray
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Green 48-BGA (RoHS Compliant)
Revision History
Revision #
Date
Change Description
A
B
Jan. 2001
Apr. 2001
Initial advance release
Changed operating voltage to 2.2V. Other minor erratas.
Part number change from EM064U16, modified Overview and Features, added
Page Mode Operation diagam, revised Operating Characteristics table, Func-
tional Description table and Ordering Information diagram
C
Dec. 2001
D
E
F
Nov. 2002
Oct. 2004
Nov. 2005
Replaced Isb and Icc on Product Family table with typical values
Added Pb-Free and Green Package Option
Removed Pb-Free Pkg, added Greenn Pkg & RoHS Compliant
G
8
September 2006 Converted to AMI Semiconductor
July 2008
Converted to ON Semiconductor and new part numbers
ON Semiconductor and
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further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
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consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical
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Rev. 8 | Page 10 of 10 | www.onsemi.com
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