N02L63W2AB25IT [ONSEMI]

2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K × 16 bit; 2MB超低功耗异步SRAM CMOS 128K × 16位


型号：	N02L63W2AB25IT
厂家：	ONSEMI
描述：	2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K × 16 bit 2MB超低功耗异步SRAM CMOS 128K × 16位静态存储器
文件：	总11页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

N02L63W2A

2Mb Ultra-Low Power Asynchronous CMOS SRAM

128K × 16 bit

Features

• Single Wide Power Supply Range

Overview

The N02L63W2A is an integrated memory device

containing a 2 Mbit Static Random Access Memory

organized as 131,072 words by 16 bits. The device

is designed and fabricated using ON

2.3 to 3.6 Volts

• Very low standby current

2.0µA at 3.0V (Typical)

• Very low operating current

2.0mA at 3.0V and 1µs (Typical)

Semiconductor’s advanced CMOS technology to

provide both high-speed performance and ultra-low

power. The device operates with two chip enable

(CE1 and CE2) controls and output enable (OE) to

allow for easy memory expansion. Byte controls

(UB and LB) allow the upper and lower bytes to be

accessed independently and can also be used to

deselect the device. The N02L63W2A is optimal

for various applications where low-power is critical

such as battery backup and hand-held devices.

The device can operate over a very wide

• Very low Page Mode operating current

0.8mA at 3.0V and 1µs (Typical)

• Simple memory control

Dual Chip Enables (CE1 and CE2)

Byte control for independent byte operation

Output Enable (OE) for memory expansion

• Low voltage data retention

Vcc = 1.8V

• Very fast output enable access time

30ns OE access time

temperature range of -40 C to +85 C and is

available in JEDEC standard packages compatible

with other standard 128Kb x 16 SRAMs.

• Automatic power down to standby mode

• TTL compatible three-state output driver

• Compact space saving BGA package avail-

able

Product Family

Standby

Current

Power

Supply

(Vcc)

Operating

Current (Icc),

Typical

Operating

Part Number

Package Type

Speed

Temperature

(I_SB), Typical

N02L63W2AB

N02L63W2AT

N02L63W2AB2

N02L63W2AT2

48 - BGA

44 - TSOP II

55ns @ 2.7V

70ns @ 2.3V

-40^oC to +85^oC

2.3V - 3.6V

2 µA

2 mA @ 1MHz

48 - BGA Green

44 - TSOP II Green

July 2008 - Rev. 9

Publication Order Number:

N02L63W2A/D

N02L63W2A

Pin Configuration

A₀

A₃

A₁

A₄

A₂

ONE

CE2

I/O₈

I/O₀

CE1

I/O0

I/O1

I/O2

I/O3

VCC

VSS

I/O4

I/O5

I/O6

I/O7

A16

A15

A14

A13

A12

I/O15

I/O14

I/O13

I/O12

VSS

VCC

I/O11

I/O10

I/O9

I/O8

CE2

I/O₉I/O₁₀A₅

A₆

A₇

I/O₁I/O₂

I/O₃V_CC

V_SSI/O₁₁

V_CCI/O₁₂

A₁₆I/O₄V_SS

A₁₅I/O₅I/O₆

I/O₁₄I/O₁₃A₁₄

I/O₁₅

A₁₂

A₉

A₁₃

A₁₀

I/O₇

A₈

A₁₁

A10

A11

48 Pin BGA (top)

6 x 8 mm

Pin Descriptions

Pin Name

A₀-A₁₆

CE1, CE2

I/O₀-I/O₁₅

Pin Function

Address Inputs

Write Enable Input

Chip Enable Input

Output Enable Input

Lower Byte Enable Input

Upper Byte Enable Input

Data Inputs/Outputs

V_CC

V_SS

Power

Ground

Not Connected

Rev. 9 | Page 2 of 11 | www.onsemi.com

N02L63W2A

Functional Block Diagram

Word

Address

Inputs

Address

Decode

Logic

A0 - A3

Input/

Output

Mux

Page

32K Page

x 16 word

x 16 bit

Address

Inputs

I/O0 - I/O7

Address

Decode

Logic

A4 - A16

and

RAM Array

Buffers

I/O8 - I/O15

CE1

CE2

Control

Logic

Functional Description

CE1

CE2

MODE

POWER

I/O₀- I/O₁₅

Standby²

X³

L¹

High Z

Data In

Data Out

High Z

Standby

Active

Standby

Write³

Read

Active

1. When UB and LB are in select mode (low), I/O₀- I/O₁₅are affected as shown. When LB only is in the select mode only I/O₀- I/O₇

are affected as shown. When UB is in the select mode only I/O₈- I/O₁₅are affected as shown.

2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally

isolated from any external influence and disabled from exerting any influence externally.

3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.

Capacitance

Item

Symbol

C_IN

Test Condition

Min

Max

Unit

V_IN= 0V, f = 1 MHz, T_A= 25^oC

Input Capacitance

I/O Capacitance

C_I/O

1. These parameters are verified in device characterization and are not 100% tested

Rev. 9 | Page 3 of 11 | www.onsemi.com

N02L63W2A

Absolute Maximum Ratings

Item

Symbol

V_IN,OUT

V_CC

Rating

–0.3 to V_CC+0.3

–0.3 to 4.5

500

Unit

Voltage on any pin relative to V_SS

Voltage on V_CCSupply Relative to V_SS

Power Dissipation

P_D

^oC

T_STG

Storage Temperature

–40 to 125

T_A

Operating Temperature

-40 to +85

260^oC, 10sec

T_SOLDER

Soldering Temperature and Time

1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operating section of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Operating Characteristics (Over Specified Temperature Range)

Typ¹

Item

Symbol

Test Conditions

Min.

Max

Unit

V_CC

V_DR

V_IH

V_IL

Supply Voltage

Data Retention Voltage

Input High Voltage

2.3

1.8

3.0

3.6

V_CC+0.3

0.6

Chip Disabled³

1.8

Input Low Voltage

–0.3

V_OH

V_OL

I_LI

I_OH= 0.2mA

I_OL= -0.2mA

V_CC–0.2

Output High Voltage

Output Low Voltage

Input Leakage Current

Output Leakage Current

0.2

0.5

V_IN= 0 to V_CC

µA

I_LO

OE = V_IHor Chip Disabled

VCC=3.6 V, V_IN=V_IHor V_IL

Chip Enabled, I_OUT= 0

Read/Write Operating Supply Current

I_CC1

I_CC2

2.0

4.0

@ 1 µs Cycle Time²

VCC=3.6 V, V_IN=V_IHor V_IL

Chip Enabled, I_OUT= 0

Read/Write Operating Supply Current

12.0

16.0

@ 70 ns Cycle Time²

Page Mode Operating Supply Current

@ 70ns Cycle Time²(Refer to Power

Savings with Page Mode Operation

diagram)

VCC=3.6 V, V_IN=V_IHor V_IL

Chip Enabled, I_OUT= 0

I_CC3

4.0

2.0

V_CC=3.6 V, V_IN=V_IHor V_IL

Chip Enabled, I_OUT= 0,

f = 0

Read/Write Quiescent Operating Sup-

ply Current³

I_CC4

3.0

V_IN= V_CCor 0V

Chip Disabled

Maximum Standby Current³

I_SB1

20.0

10.0

µA

t_A= 85^oC, VCC = 3.6 V

Vcc = 1.8V, V_IN= V_CCor 0

Chip Disabled, t_A= 85^oC

Maximum Data Retention Current³

I_DR

1. Typical values are measured at Vcc=Vcc Typ., T_A=25°C and not 100% tested.

2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive

output capacitance expected in the actual system.

3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all

inputs must be within 0.2 volts of either VCC or VSS.

Rev. 9 | Page 4 of 11 | www.onsemi.com

N02L63W2A

Power Savings with Page Mode Operation (WE = V )

Page Address (A4 - A16)

Word Address (A0 - A3)

Open page

...

Word 16

Word 1

Word 2

CE1

CE2

LB, UB

Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal

organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power

saving feature.

The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open

and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant

bits and addressing the 16 words within the open page, power is reduced to the page mode value which is

considerably lower than standard operating currents for low power SRAMs.

Rev. 9 | Page 5 of 11 | www.onsemi.com

N02L63W2A

Timing Test Conditions

Item

0.1V_CCto 0.9 V_CC

Input Pulse Level

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

5ns

0.5 V_CC

CL = 30pF

-40 to +85 ^oC

Operating Temperature

Timing

2.3 - 3.6 V

2.7 - 3.6 V

Item

Symbol

Units

Min.

Max.

Min.

Max.

t_RC

t_AA

t_CO

t_OE

Read Cycle Time

Address Access Time

Chip Enable to Valid Output

Output Enable to Valid Output

Byte Select to Valid Output

Chip Enable to Low-Z output

Output Enable to Low-Z Output

Byte Select to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Byte Select Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

_LB, t_UB

t_LZ

t_OLZ

t_LBZ, t_UBZ

t_HZ

t_OHZ

_LBHZ, t_UBHZ

t_OH

t_WC

t_CW

Chip Enable to End of Write

Address Valid to End of Write

Byte Select to End of Write

Write Pulse Width

t_AW

t_LBW, t_UBW

t_WP

t_AS

Address Setup Time

t_WR

Write Recovery Time

t_WHZ

t_DW

Write to High-Z Output

Data to Write Time Overlap

Data Hold from Write Time

End Write to Low-Z Output

t_DH

t_OW

Rev. 9 | Page 6 of 11 | www.onsemi.com

N02L63W2A

Timing of Read Cycle (CE1 = OE = V , WE = CE2 = V )

Address

Previous Data Valid

Data Valid

Data Out

Timing Waveform of Read Cycle (WE=V )

Address

CE1

CE2

OHZ

OLZ

LB, UB

LBHZ, UBHZ

LBLZ, UBLZ

High-Z

Data Valid

Data Out

Rev. 9 | Page 7 of 11 | www.onsemi.com

N02L63W2A

Timing Waveform of Write Cycle (WE control)

Address

CE1

CE2

, t

LBW UBW

LB, UB

High-Z

Data Valid

Data In

Data Out

WHZ

High-Z

Timing Waveform of Write Cycle (CE1 Control)

Address

CE1

(for CE2 Control, use

inverted signal)

, t

LBW UBW

LB, UB

Data Valid

Data In

WHZ

High-Z

Data Out

Rev. 9 | Page 8 of 11 | www.onsemi.com

N02L63W2A

44-Lead TSOP II Package (T44)

18.41±0.13

11.76±0.20

10.16±0.13

0.80mm REF

0.45

0.30

SEE DETAIL B

DETAIL B

1.10±0.15

0 -8

0.20

0.00

0.80mm REF

Note:

1. All dimensions in inches (Millimeters)

2. Package dimensions exclude molding flash

Rev. 9 | Page 9 of 11 | www.onsemi.com

N02L63W2A

Ball Grid Array Package

0.28±0.05

1.24±0.10

A1 BALL PAD

CORNER (3)

1. 0.35±0.05 DIA.

2. SEATING PLANE - Z

0.15

0.05

TOP VIEW

SIDE VIEW

1. DIMENSION IS MEASURED AT THE

MAXIMUM SOLDER BALL DIAMETER.

PARALLEL TO PRIMARY Z.

A1 BALL PAD

CORNER

2. PRIMARY DATUM Z AND SEATING

PLANE ARE DEFINED BY THE

SPHERICAL CROWNS OF THE

SOLDER BALLS.

3. A1 BALL PAD CORNER I.D. TO BE

MARKED BY INK.

K TYP

J TYP

BOTTOM VIEW

Dimensions (mm)

e = 0.75

BALL

MATRIX

TYPE

6±0.10

8±0.10

0.375

1.125

1.375

FULL

Rev. 9 | Page 10 of 11 | www.onsemi.com

N02L63W2A

Ordering Information

Part Number

Package

Shipping Method

N02L63W2AT5I

N02L63W2AT25I

N02L63W2AB5I

N02L63W2AB25I

N02L63W2AT5IT

N02L63W2AT25IT

N02L63W2AB5IT

N02L63W2AB25IT

Leaded 44-TSOP II

Green 44-TSOP II (RoHS Compliant)

Leaded 48-BGA

Green 48-BGA (RoHS Compliant)

Leaded 44-TSOP II

Green 44-TSOP II (RoHS Compliant)

Leaded 48-BGA

Tray

Tape & Reel

Green 48-BGA (RoHS Compliant)

Revision History

Revision

Date

Change Description

Jan. 2001

May 2001

Sept. 2001

Initial Preliminary Release

Changed access time to 55 ns

Minor parametric modifications. Full production release.

Part number change from EM128J16, modified Overview and Features, added

Page Mode Operation diagram, revised Operating Characteristics table, Package

diagram, Functional Description table and Ordering Information diagram

Dec. 2001

Nov. 2002

Oct. 2004

Nov. 2005

Replaced Isb and Icc on Product Family table with typical values

Added Pb-Free and Green Package Option

Removed Pb-Free Pkg., added Green Pkg, RoHS compliant

September 2006 Converted to AMI Semiconductor

July 2008

Converted to ON Semiconductor and new part numbers

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without

further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does

SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special,

consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical

experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as

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Rev. 9 | Page 11 of 11 | www.onsemi.com

N02L63W2AB25IT [ONSEMI]

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