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N04L163WC2AT2-55I [ONSEMI]

256KX16 STANDARD SRAM, 70ns, PDSO44, GREEN, TSOP2-44;
N04L163WC2AT2-55I
型号： N04L163WC2AT2-55I
厂家： ONSEMI    ONSEMI
描述：

256KX16 STANDARD SRAM, 70ns, PDSO44, GREEN, TSOP2-44

静态存储器 光电二极管 内存集成电路
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AMI Semiconductor, Inc.  
ULP Memory Solutions  
670 North McCarthy Blvd. Suite 220  
Milpitas, CA 95035  
N04L163WC2A  
PH: 408-935-7777, FAX: 408-935-7770  
4Mb Ultra-Low Power Asynchronous CMOS SRAM  
256K × 16 bit  
Overview  
Features  
The N04L163WC2A is an integrated memory  
device containing a 4 Mbit Static Random Access  
Memory organized as 262,144 words by 16 bits.  
The device is designed and fabricated using AMI  
Semiconductor’s advanced CMOS technology to  
provide both high-speed performance and ultra-low  
power. The device operates with two chip enable  
(CE1 and CE2) controls and output enable (OE) to  
allow for easy memory expansion. Byte controls  
(UB and LB) allow the upper and lower bytes to be  
accessed independently and can also be used to  
deselect the device. The N04L163WC2A is optimal  
for various applications where low-power is critical  
such as battery backup and hand-held devices.  
The device can operate over a very wide  
• Single Wide Power Supply Range  
2.3 to 3.6 Volts  
• Very low standby current  
4.0µA at 3.0V (Typical)  
• Very low operating current  
2.0mA at 3.0V and 1µs (Typical)  
• Very low Page Mode operating current  
0.8mA at 3.0V and 1µs (Typical)  
• Simple memory control  
Dual Chip Enables (CE1 and CE2)  
Output Enable (OE) for memory expansion  
• Low voltage data retention  
Vcc = 1.8V  
o
o
temperature range of -40 C to +85 C and is  
available in JEDEC standard packages compatible  
with other standard 256Kb x 16 SRAMs  
• Very fast output enable access time  
25ns OE access time  
• Automatic power down to standby mode  
• TTL compatible three-state output driver  
• Compact space saving BGA package avail-  
able - RoHS Compliant option  
Product Family  
Standby  
Power  
Supply  
(Vcc)  
Operating  
Current (Icc),  
Typical  
Operating  
Speed  
Current(ISB),  
Part Number  
Package Type  
Temperature  
Options  
Typical  
N04L163WC2AB  
N04L163WC2AT  
N04L163WC2AB2  
N04L163WC2AT2  
48 - BGA  
44 - TSOP II  
70ns @ 2.7V  
55ns @ 2.7V  
o
o
2.3V - 3.6V  
4 µA  
2 mA @ 1MHz  
-40 C to +85 C  
48 - BGA Green  
44 - TSOP II Green  
Pin Configuration  
Pin Descriptions  
1
2
3
A0  
A3  
4
A1  
A4  
A6  
A7  
5
A2  
6
A4  
1
PIN  
A5  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A3  
2
ONE  
A6  
A2  
3
LB  
OE  
CE2  
A7  
A
B
C
D
E
F
Pin Name  
A0-A17  
WE  
CE1, CE2  
OE  
LB  
UB  
I/O0-I/O15  
Pin Function  
A1  
4
OE  
A0  
5
UB  
I/O8  
I/O0  
UB  
CE1  
Address Inputs  
Write Enable Input  
Chip Enable Input  
CE1  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
VSS  
I/O4  
I/O5  
I/O6  
I/O7  
WE  
A16  
A15  
A14  
A13  
A12  
6
LB  
7
I/O15  
I/O14  
I/O13  
I/O12  
VSS  
VCC  
I/O11  
I/O10  
I/O9  
I/O8  
CE2  
A8  
I/O9 I/O10 A5  
VSS I/O11 A17  
I/O1 I/O2  
I/O3 VCC  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Output Enable Input  
Lower Byte Enable Input  
Upper Byte Enable Input  
Data Inputs/Outputs  
VCC I/O12  
A16 I/O4 VSS  
A15 I/O5 I/O6  
NC  
I/O14 I/O13 A14  
I/O15  
NC  
A12  
A9  
A13  
A10  
I/O7  
NC  
NC  
A8  
WE  
A11  
G
H
A9  
VCC  
VSS  
NC  
Power  
Ground  
Not Connected  
A10  
A11  
48 Pin BGA (top)  
6 x 8 mm  
A17  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
1
AMI Semiconductor, Inc.  
Functional Block Diagram  
N04L163WC2A  
Word  
Address  
Inputs  
Address  
Decode  
Logic  
A0 - A3  
Input/  
Page  
16K Page  
x 16 word  
x 16 bit  
Address  
Inputs  
Output  
Address  
Decode  
Logic  
I/O0 - I/O7  
Mux  
A4 - A17  
and  
RAM Array  
Buffers  
I/O8 - I/O15  
CE1  
CE2  
WE  
OE  
Control  
Logic  
UB  
LB  
Functional Description  
1
CE1  
CE2  
WE  
OE  
UB  
LB  
MODE  
POWER  
I/O0 - I/O15  
Standby2  
Standby2  
H
X
L
L
L
L
X
L
H
H
H
H
X
X
X
L
X
X
X
X3  
L
X
X
H
L1  
L1  
L1  
X
X
H
L1  
L1  
L1  
High Z  
High Z  
High Z  
Data In  
Data Out  
High Z  
Standby  
Standby  
Standby  
Active  
Standby  
Write3  
Read  
Active  
H
H
Active  
H
Active  
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7  
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.  
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally  
isolated from any external influence and disabled from exerting any influence externally.  
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.  
1
Capacitance  
Item  
Symbol  
CIN  
Test Condition  
Min  
Max  
8
Unit  
pF  
VIN = 0V, f = 1 MHz, TA = 25oC  
VIN = 0V, f = 1 MHz, TA = 25oC  
Input Capacitance  
I/O Capacitance  
CI/O  
8
pF  
1. These parameters are verified in device characterization and are not 100% tested  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
2
AMI Semiconductor, Inc.  
N04L163WC2A  
1
Absolute Maximum Ratings  
Item  
Symbol  
VIN,OUT  
VCC  
Rating  
–0.3 to VCC+0.3  
–0.3 to 4.5  
500  
Unit  
V
Voltage on any pin relative to VSS  
Voltage on VCC Supply Relative to VSS  
Power Dissipation  
V
PD  
mW  
oC  
oC  
oC  
TSTG  
Storage Temperature  
–40 to 125  
TA  
Operating Temperature  
-40 to +85  
260oC, 10sec  
TSOLDER  
Soldering Temperature and Time  
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not  
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
Operating Characteristics (Over Specified Temperature Range)  
Typ1  
Item  
Symbol  
Test Conditions  
Min.  
Max  
Unit  
VCC  
VDR  
VIH  
VIL  
Supply Voltage  
Data Retention Voltage  
Input High Voltage  
2.3  
1.8  
3.0  
3.6  
3.6  
VCC+0.3  
0.6  
V
V
Chip Disabled3  
1.8  
V
Input Low Voltage  
–0.3  
V
VOH  
VOL  
ILI  
IOH = 0.2mA  
IOL = -0.2mA  
VCC–0.2  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
Output Leakage Current  
V
0.2  
0.5  
0.5  
V
VIN = 0 to VCC  
µA  
µA  
ILO  
OE = VIH or Chip Disabled  
VCC=3.6 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0  
Read/Write Operating Supply Current  
ICC1  
ICC2  
2.0  
3.0  
mA  
mA  
@ 1 µs Cycle Time2  
VCC=3.6 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0  
Read/Write Operating Supply Current  
10.0  
16.0  
@ 70 ns Cycle Time2  
Page Mode Operating Supply Current  
@ 70ns Cycle Time2 (Refer to Power  
Savings with Page Mode Operation  
diagram)  
VCC=3.6 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0  
ICC3  
4.0  
4.0  
mA  
mA  
VCC=3.6 V, VIN=VIH or VIL  
Chip Enabled, IOUT = 0,  
f = 0  
Read/Write Quiescent Operating Sup-  
ply Current3  
ICC4  
2.0  
VIN = VCC or 0V  
Chip Disabled  
Maximum Standby Current3  
ISB1  
20.0  
10  
µA  
µA  
tA= 85oC, VCC = 3.6 V  
Vcc = 1.8V, VIN = VCC or 0  
Chip Disabled, tA= 85oC  
Maximum Data Retention Current3  
IDR  
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.  
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive  
output capacitance expected in the actual system.  
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all  
inputs must be within 0.2 volts of either VCC or VSS.  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
3
AMI Semiconductor, Inc.  
Power Savings with Page Mode Operation (WE = V )  
N04L163WC2A  
IH  
Page Address (A4 - A17)  
Word Address (A0 - A3)  
Open page  
...  
Word 16  
Word 1  
Word 2  
CE1  
CE2  
OE  
LB, UB  
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal  
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power  
saving feature.  
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open  
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant  
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is  
considerably lower than standard operating currents for low power SRAMs.  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
4
AMI Semiconductor, Inc.  
Timing Test Conditions  
N04L163WC2A  
Item  
0.1VCC to 0.9 VCC  
Input Pulse Level  
Input Rise and Fall Time  
Input and Output Timing Reference Levels  
Output Load  
5ns  
0.5 VCC  
CL = 30pF  
-40 to +85 oC  
Operating Temperature  
Timing  
-70  
-55  
Item  
Symbol  
2.3 - 2.65 V  
Min. Max.  
2.7 - 3.6 V  
2.7 - 3.6 V  
Units  
Min.  
Max.  
Min.  
Max.  
tRC  
tAA  
tCO  
tOE  
Read Cycle Time  
85  
70  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Access Time  
Chip Enable to Valid Output  
85  
85  
30  
85  
70  
70  
25  
70  
55  
55  
25  
55  
Output Enable to Valid Output  
Byte Select to Valid Output  
t
LB, tUB  
tLZ  
tOLZ  
tBZ  
Chip Enable to Low-Z output  
Output Enable to Low-Z Output  
Byte Select to Low-Z Output  
Chip Disable to High-Z Output  
Output Disable to High-Z Output  
Byte Select Disable to High-Z Output  
Output Hold from Address Change  
10  
5
10  
5
10  
5
10  
0
10  
0
10  
0
tHZ  
20  
20  
20  
20  
20  
20  
20  
20  
20  
tOHZ  
tBHZ  
tOH  
0
0
0
0
0
0
10  
10  
10  
tWC  
tCW  
tAW  
tBW  
tWP  
tAS  
Write Cycle Time  
Chip Enable to End of Write  
Address Valid to End of Write  
Byte Select to End of Write  
Write Pulse Width  
85  
50  
50  
50  
40  
0
70  
50  
50  
50  
40  
0
55  
45  
45  
45  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Setup Time  
tWR  
tWHZ  
tDW  
tDH  
Write Recovery Time  
0
0
0
Write to High-Z Output  
Data to Write Time Overlap  
Data Hold from Write Time  
End Write to Low-Z Output  
20  
20  
20  
40  
0
40  
0
40  
0
tOW  
5
5
5
ns  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
5
AMI Semiconductor, Inc.  
N04L163WC2A  
Timing of Read Cycle (CE1 = OE = V , WE = CE2 = V )  
IL  
IH  
t
RC  
Address  
Data Out  
t
AA  
t
OH  
Previous Data Valid  
Data Valid  
Timing Waveform of Read Cycle (WE=V )  
IH  
t
RC  
Address  
t
AA  
t
HZ  
CE1  
CE2  
t
CO  
t
LZ  
t
OHZ  
t
OE  
OE  
t
OLZ  
t
t
LB, UB  
LB, UB  
t
t
BLZ  
BHZ  
High-Z  
Data Valid  
Data Out  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
6
AMI Semiconductor, Inc.  
N04L163WC2A  
Timing Waveform of Write Cycle (WE control)  
t
WC  
Address  
t
WR  
t
AW  
CE1  
CE2  
t
CW  
t
BW  
LB, UB  
WE  
t
t
AS  
WP  
t
t
DH  
DW  
High-Z  
Data Valid  
Data In  
t
WHZ  
t
OW  
High-Z  
Data Out  
Timing Waveform of Write Cycle (CE1 Control)  
t
WC  
Address  
t
t
AW  
WR  
t
CE1  
CW  
(for CE2 Control, use  
inverted signal)  
t
AS  
t
BW  
LB, UB  
WE  
t
t
WP  
t
t
DH  
DW  
Data Valid  
Data In  
t
LZ  
WHZ  
High-Z  
Data Out  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
7
AMI Semiconductor, Inc.  
N04L163WC2A  
44-Lead TSOP II Package (T44)  
18.41±0.13  
11.76±0.20  
10.16±0.13  
0.80mm REF  
0.45  
0.30  
SEE DETAIL B  
DETAIL B  
1.10±0.15  
o
o
0 -8  
0.20  
0.00  
0.80mm REF  
Note:  
1. All dimensions in inches (Millimeters)  
2. Package dimensions exclude molding flash  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
8
AMI Semiconductor, Inc.  
Ball Grid Array Package  
N04L163WC2A  
0.28±0.05  
1.24±0.10  
D
A1 BALL PAD  
CORNER (3)  
1. 0.35±0.05 DIA.  
E
2. SEATING PLANE - Z  
0.15  
Z
0.05  
Z
TOP VIEW  
SIDE VIEW  
1. DIMENSION IS MEASURED AT THE  
MAXIMUM SOLDER BALL DIAMETER.  
PARALLEL TO PRIMARY Z.  
A1 BALL PAD  
CORNER  
SD  
2. PRIMARY DATUM Z AND SEATING  
PLANE ARE DEFINED BY THE  
SPHERICAL CROWNS OF THE  
SOLDER BALLS.  
e
SE  
3. A1 BALL PAD CORNER I.D. TO BE  
MARKED BY INK.  
K TYP  
J TYP  
e
BOTTOM VIEW  
Dimensions (mm)  
e = 0.75  
BALL  
D
E
MATRIX  
TYPE  
SD  
SE  
J
K
6±0.10  
8±0.10  
0.375  
0.375  
1.125  
1.375  
FULL  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
9
AMI Semiconductor, Inc.  
N04L163WC2A  
Ordering Information  
N04L163WC2AX-XX I  
55 = 55ns  
70 = 70ns  
Performance  
T = 44-pin TSOP II  
B = 48-ball BGA  
Package Type  
T2 = 44-pin TSOP II Green Package (RoHS Compliant)  
B2 = 48-ball BGA Green Package (RoHS Complliant)  
Revision History  
Revision  
Date  
Change Description  
A
Jan. 2001  
Initial Preliminary Release  
Part number change from EM256J16, modified Overview and Features, added  
Page Mode Operation diagram, revised Operating Characteristics table, Package  
diagram, Functional Description table and Ordering Information diagram  
B
Dec. 2001  
C
D
E
F
G
H
I
Nov. 2002  
February 2003  
August 2004  
Oct 2004  
Nov. 2005  
September 2006  
October 2007  
Replaced Isb and Icc on Product Family table with typical values  
Added 55ns sort  
Removed 55ns sort  
Added Pb-Free and Green Package Option  
Removed Pb-Free Pkg., added Green Pkg and RoHS Compliant was added  
Converted to AMI Semiconductor  
Added 55ns performance sort  
© 2006-2007 AMI Semiconductor, Inc. All rights reserved.  
AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice.  
AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration pur-  
poses only and they vary depending upon specific applications.  
AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of  
any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be  
expected to result in significant injury or death, including life support systems and critical medical instruments.  
(DOC# 14-02-017 REV I ECN# 01-1268)  
The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com.  
10  

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