N24RF04EDTPT3G_技术文档

N24RF04E

RFID 4 Kb EEPROM Tag

ISO 15693 RF, I²C Bus,

Energy Harvesting

Description

The N24RF04E is a RFID/NFC tag with a 4 Kb EEPROM device,

offering both contactless and contact interface. In addition to the

ISO/IEC 15693 radio frequency identification (RFID) interface

www.onsemi.com

2

protocol, the device features an I C interface to communicate with

2

a microcontroller. The I C contact interface requires an external

SOIC 8

CASE 751BD

TSSOP8, 4.4x3

CASE 948AL

power supply.

The 4 Kb EEPROM array is internally organized as 128 x 32 bits in

2

PIN CONFIGURATION

RF mode and as 512 x 8 bits when accessed from the I C interface.

V

CC

OUT

Features

AN

RF WIP/BUSY

SCL

1

• Contactless Transmission of Data

AN

2

• ISO 15693 / ISO 18000−3 Mode1 Compliant

♦ Vicinity Range Communication (up to 150 cm)

♦ Air Interface Communication at 13.56 MHz (HF)

♦ To Tag: ASK Modulation with 1.65 Kbit/s or 26.48 Kbit/s Data

Rate

V

SDA

SS

SOIC (W, X), TSSOP (Y)

PIN FUNCTION

Pin Name

SDA

Function

Serial Data

♦ From Tag: Load Modulation Using Manchester Coding with

423 kHz and 484 kHz Subcarriers in Low (6.6 Kbit/s) or High

(26 Kbit/s) Data Rate Mode. Supports the 53 Kbit/s Data Rate

with Fast Commands

SCL

Serial Clock

AN1, AN2

Antenna Coil

V

CC

Power Supply

Ground

• Read & Write 32−bit Block Mode

• Anti−collision Support

• Security:

V

SS

V

OUT

Energy Harvesting Output

RF WIP/BUSY

Internal Write or RF command

in progress

♦ 64−bit Unique Identifier (UID)

♦ Multiple 32−bit Passwords and Lock Feature for Each User

Memory Sector

MARKING DIAGRAMS

2

• Supports Fast (400 kHz) and Fast−Plus (1 MHz) I C Protocol

• 1.8 V to 5.5 V Supply Voltage Range

• 4−Byte Page Write Buffer

RF04EH

AYMZZZ

04EH

AYMZZZ

2

• I C Timeout

2

• Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs

(SCL and SDA)

A

= Assembly Site Code

• 128 Blocks x 32 Bits (4 Sectors of 32 Blocks Each): RF Mode

Y

M

= Production Year (Last Digit)

= Production Month Code

2

• 512 x 8 Bits I C Mode

ZZZ = Last 3 Characters of Assembly Lot Number

• 2,000,000 Program/Erase Cycles

• 200 Year Data Retention

ORDERING INFORMATION

See detailed ordering and shipping information on page 22 of

this data sheet.

• −40_C to +105_C Temperature Range

• Configurable Output Pin: RF Write in Progress or RF Busy

• Energy Harvesting Analog Output

• SOIC, TSSOP 8−lead Packages

*For additional information on our Pb−Free strategy

and soldering details, please download the

ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant*

1

Publication Order Number:

November, 2018 − Rev. 1

N24RF04E/D

N24RF04E

V

CC

AN1

AN2

SCL

SDA

N24RF04E

V

OUT

RF WIP/BUSY

V

SS

Figure 1. Functional Symbol

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

−65 to +150

−40 to +105

−0.5 to 6.5

28

Unit

°C

V

Storage Temperature

Ambient Operating Temperature

Voltage on SCL, SDA, RF WIP/BUSY and V pins with respect to Ground (Note 1)

CC

RF Input Voltage Peak to Peak Amplitude between AN1 and AN2, VSS pad floating

AC Voltage on AN1 or AN2 with respect to GND

V

−1 to 15

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2

1. During transitions, the voltage undershoot on any pin should not exceed 1 V for more than 20 ns. Voltage overshoot on the SCL and SDA I C

pins should not exceed the absolute maximum ratings, irrespective of VCC.

Table 2. RELIABILITY CHARACTERISTICS − EEPROM (Note 2)

Symbol

Parameter

Endurance

Test Conditions

Max

2,000,000

800,000

300,000

200

Unit

NEND

Write Cycles (Note 3)

T

≤ 25_C, 1.8 V < V_CC< 5.5 V

A

T = 85_C, 1.8 V < V_CC< 5.5 V

A

T = 105_C, 1.8 V < V_CC< 5.5 V

A

TDR

Data Retention

T = 25_C

A

Year

2. Determined through qualification/characterization.

3. A Write Cycle refers to writing a Byte or a Page.

www.onsemi.com

2

N24RF04E

Table 3. DC CHARACTERISTICS − I²C MODE (V = 1.8 V to 5.5 V, T = −40°C to +105°C, unless otherwise specified)

CC

A

Symbol

Parameter

Test Conditions

Min

−

Max

0.15

0.2

Unit

ICCR

Supply Current (Read Mode)

Read,

= 400 kHz

V

CC

V

CC

V

CC

= 1.8 V

= 2.5 V

= 5.5 V

mA

f

SCL

−

0.3

ICCW

ISB1

Supply Current (Write Mode)

Standby Current

Write Cycle

−

0.4

mA

V

IN

= GND or V

No RF Field on antenna coil

−

10

CC

Both V Supply and RF Field on

−

100

CC

antenna coil

IL

Input Leakage Current

Output Leakage Current

Input Low Voltage

V

= GND or V

−2

2

mA

V

IN

CC

ILO

SDA = Hi Z, V

= GND or V

OUT CC

VIL1

VIH1

VIL2

VIH2

VOL1

VOL2

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

≥ 2.5 V

< 2.5 V

−0.5

0.3 V

CC

Input High Voltage

Input Low Voltage

0.7 V

V

+0.5

V

CC

−0.5

0.25 V

V

CC

Input High Voltage

Output Low Voltage

0.75 V

V

+0.5

V

CC

≥ 2.5 V, I = 3.0 mA

−

0.4

0.2

V

OL

< 2.5 V, I = 2.1 mA

V

OL

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 4. PIN IMPEDANCE CHARACTERISTICS

Symbol

Parameter

Conditions

Max

8

Unit

pF

C

(Note 4)

I/O Pin Capacitance (SDA, RF WIP/BUSY)

Input Capacitance (other pins)

V

= 0 V

IN

6

pF

IN

4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

and JEDEC test methods.

www.onsemi.com

3

N24RF04E

Table 5. AC CHARACTERISTICS − I²C MODE (Note 5) (V = 1.8 V to 5.5 V, T_A= −40°C to +105°C, unless otherwise specified)

CC

2

I C Fast

Min

I C Fast Plus

Max

400

20000

−

Min

25

0.45

0.40

0.25

0

Max

1000

Unit

kHz

ms

Symbol

FSCL

Parameter

Clock Frequency

25

1.3

0.6

0

tLOW

Low Period of SCL Clock

20000

tHIGH

High Period of SCL Clock

START Condition Setup Time

START Condition Hold Time

Data In Hold Time

ms

tSU:STA

tHD:STA

tHD:DAT

tSU:DAT

t_R(Note 6)

t_F(Note 6)

tSU:STO

tBUF

ms

20000

−

20000

−

ms

Data In Setup Time

100

−

50

−

ns

SDA and SCL Rise Time

SDA and SCL Fall Time

300

−

100

−

ns

−

ns

STOP Condition Setup Time

Bus Free Time Between STOP and START

SCL Low to Data Out Valid

Data Out Hold Time

0.6

1.3

−

0.25

0.5

−

ms

−

ms

tAA

0.9

−

0.4

−

ms

tDH

100

−

50

−

ns

T_i(Note 6)

tWR

Noise Pulse Filtered at SCL and SDA Inputs

Write Cycle Time

50

5

ns

−

5

−

ms

t_PU(Notes 6, 7)

Power−up to Ready Mode

−

1

−

1

5. Test conditions according to “AC Test Conditions” table.

6. Tested initially and after a design or process change that affects this parameter.

7. t_PUis the delay between the time V_CCis stable and the device is ready to accept commands.

Table 6. AC TEST CONDITIONS

Parameter

Input Levels

Condition

0.2 x V to 0.8 x V

CC

Input Rise and Fall Times

Output Reference Levels

Output Load

≤ 50 ns

0.5 x V

CC

Current Source: I = 3 mA (V ≥ 2.5 V); I = 2 mA (V < 2.5 V); C = 100 pF

OL

CC

OL

CC

L

www.onsemi.com

4

N24RF04E

Table 7. RF CHARACTERISTICS (T_A= −40°C to +105°C, unless otherwise specified)

Symbol

Parameter

External RF signal frequency

Operating field

Test Conditions

Min

13.553

150

Typ

13.56

−

Max

13.567

5000

30

Unit

MHz

mA/m

%

f

CC

H_ISO

MI_Carrier (10%)

10% Carrier Modulation Index MI = (a − b) / (a + b)

150 mA/m

< H_ISO

< 1000 mA/m

10

−

H_ISO

> 1000 mA/m

15

−

30

%

t

10% Fall and Low Time

10% Minimum Low Time

10% Rise Time

t1 = t2

6.0

4.5

0

−

9.44

t1

ms

%

1:10%

2:10%

3:10%

t1 = 9.44 ms

MI = (a − b) / (a + b)

t1 = t2

4.5

100

9.44

t1

MI_Carrier (100%) 100% Carrier Modulation Index

95

6.0

2.1

0

t

100% Fall and Low Time

ms

1:100%

2:100%

3:100%

4:100%

−

100% Minimum Pulse Width Low Time

100% Rise Time

t1 = 9.44 ms

3

100% Rise Time to 60% of Amplitude

0

0.8

1

t

Minimum delay from Carrier generation to first Data 150 mA/m

−

MIN C D

< H_ISO

< 1000 mA/m

H_ISO > 1000 mA/m

fCC/32

−

2

−

ms

kHz

ms

f

Subcarrier Frequency High

423.75

484.28

320.9

5.758

26

SH

f

Subcarrier Frequency Low

fCC/28

−

SL

t

N24RF04E Tag Response Time

RF Write Time (with internal Verify)

Internal Tuning Capacitor (TSSOP−8) (Note 10)

4352/FS

78080/FS

318.4

5.753

−

323.5

5.763

−

RESP

t

ms

pF

WRF

C

f = 13.56 MHz;

Van1 − Van2 = 1 Vp−p

TUN

V

RF Input Voltage between AN1 and AN2 (peak to

peak), V_SSpad floating (Note 10)

−

−1

−

22

11

−

V

−

MAX 1

V

AC voltage on AN1 or AN2 with respect to GND

(Note 10)

−

MAX 2

V

RF Input Voltage between AN1 and AN2 (peak to

peak), VSS pad floating (Note 10)

4

−

MIN 1

AC voltage on AN1 or AN2 with respect to GND

(Note 10)

−

2.1

−

MIN 2

V

Backscattered Level (ISO Test)

RF Off Time

ISO10373−7

Chip reset

10

2

−

mV

ms

BACK

T

−

RF OFF

8. Characterized only.

9. All measurements performed on an antenna with the following characteristics:

· External size: 72 mm x 42 mm

· Number of turns: 7

· Antenna is printed on the PCB plated with 35 mm of Cooper

· Track width: 0.8 mm

· Space: 0.5 mm

· Coil: 5 mH

10.Characterized at room temperature only.

www.onsemi.com

5

N24RF04E

105%

100%

95%

60%

5%

t

2

t

1

t

4

t

3

The clock recovery must be operational after t max.

4

Figure 2. 100% Modulation Waveform

hf

y

t

2

hr

t

3

t

1

a

b

t

y

0.05 (a − b)

hf, hr 0.1 (a − b) max

Figure 3. 10% Modulation Waveform

Power−On Reset (POR)

• AN1, AN2: These inputs are used to connect the device to

an external antenna. The coil is used to power and access

the device through the ISO 15693 and ISO 18000−3 mode

1 RF protocols

• RF WIP/BUSY: This configurable output signal is used

either to indicate that the N24RF04E is executing an

internal write cycle from the RF channel or that an RF

command is in progress. RF WIP and signals are available

only when the N24RF04E is powered by the Vcc pin. It

is an open drain output and a pull−up resistor must be

The N24RF04E incorporates Power−On Reset (POR)

circuitry which protects the internal logic against powering

up in the wrong state. The N24RF04E will power up into

Standby mode after V exceeds the POR trigger level and

CC

will power down into Reset mode when V drops below the

CC

POR trigger level. This bi−directional POR behavior

protects the device against ‘brown−out¢ failure following a

temporary loss of power.

Pin Description

• SCL: The Serial Clock input pin accepts the clock signal

generated by the Master

• SDA: The Serial Data I/O pin accepts input data and

delivers output data. In transmit mode, this pin is open

drain. Data is acquired on the positive edge, and is

delivered on the negative edge of SCL

connected from RF WIP/BUSY to V

CC

• V : This analog output pin is used to deliver the analog

OUT

voltage Vout available when the Energy harvesting mode

is enabled and the RF field strength is sufficient. When the

Energy harvesting mode is disabled or the RF field

strength is not sufficient, the energy harvesting analog

voltage output Vout is in High−Z state

www.onsemi.com

6

N24RF04E

Functional Description

The N24RF04E is a dual interface RFID/NFC tag with

4 Kb EEPROM.

In RF mode, the read and write access is done by 32−bit

block. Read and Write access is controlled by a Sector

Security Status (SSS) byte which includes 5 significant bits:

Sector Lock bit, two Read / Write protection bits and two

Password Control Bits.

The device follows the ISO 15693 and ISO 18000−3 mode

1 standard for the radio frequency power and signal interface

via the 13.56 MHz carrier. When connected to an antenna

coil, no external power supply is required, as the operating

power is derived from the RF energy The communication

from the RF Reader to the N24RF04E tag takes place using

the ASK modulation with a 1.65 Kb/s data rate using the

1/256 pulse coding or a data rate of 26.48 Kb/s using the 1/4

pulse coding. The communication from the EEPROM tag to

the RF reader takes place via load modulation using

Manchester coding with 423 kHz and 484 kHz subcarrier

frequencies at 6.62 Kb/s or 26.48 Kb/s data rate. The device

supports also the 53 Kb/s fast mode.

2

In I C mode, a sector has 128 bytes that can be

individually accessed for Read and Write. Each sector can

be protected against write operations using the

2

I C−Write_Lock bit from the 4−bit block area.

The N24RF04E features a 64−bit block to store the 64−bit

Unique Identifier (UID) per the ISO 15963 requirements.

The UID value is written by ON Semiconductor during

manufacturing and it is used during the anti−collision

sequence.

The system memory area also includes the application

family identifier (AFI) and a data storage family identifier

(DSFID) used in the anti−collision algorithm.

The N24RF04E supports the Inter−Integrated Circuit

2

(I C) Bus protocol. The protocol relies on the use of a Master

The access to the user memory area requires the A2 bit

from the Slave address byte (Figure 6) set to “0”. All system

memory blocks (Table 8) are accessed with A2 bit set to “1”

device, which provides the clock and directs bus traffic and

Slave devices which execute requests. The N24RF04E

operates as a Slave device with a 4−bit device identifier code

2

Unique Identifier

(1010b) according to the I C standard definition.

The N24RF is programed at the factory with a 64−bit

unique identifier. The UID conforms to IS0 15693 / ISO

18000 and is read−only. The UID is comprised of:

• Eight MSBs with a value of 0xE0

• IC manufacturer code for ON Semiconductor 0x67

• Unique 48 bit serial number

Memory Organization

In the RF mode, the user memory area is organized into

4 sectors of 32 blocks each for a total of 128 blocks x 32 bits.

2

The memory access from the I C interface is organized as

512 x 8 bits, divided into 4 sectors of 128 bytes each. The

user and system memory organization is shown in Figure 4.

Each memory sector can be individually read and/or write

protected using a specific password. The N24RF04E

provides four 32−bit blocks to store three RF password and

MSB

63

56

55

48

47

0

2

0xE0

0x67

Unique serial number

one I C password codes.

Table 8. SYSTEM MEMORY

2

I C Byte

Address

Bits [31:24]

SSS 3 (00h)

−

Bits [23:16]

SSS 2 (00h)

−

Bits [15:8]

SSS 1 (00h)

−

Bits [7:0]

A2=1

0

SSS 0 (00h)

2

A2=1

2048

2304

I C Write Lock [3:0] (00h)

2

I C password

(0000 0000h)

A2=1

2308

2312

2316

RF password 1

(0000 0000h)

RF password 2

(0000 0000h)

RF password 3

(0000 0000h)

A2=1

2320

2324

2328

2332

2336

DSFID (FFh)

UID

AFI (00h)

UID

ON reserved

UID

Configuration byte (F4h)

UID

UID (E0h)

ON reserved

−

UID (67h)

UID

Mem Size (03 7Fh)

IC Ref (2Eh)

Control Register

−

www.onsemi.com

7

N24RF04E

Sector

Area

Table 11. PASSWORD CONTROL BITS

0

1

2

3

1 Kbit EEPROM Sector

b4, b3

Password

00

01

10

11

Sector not protected by password

Sector protected by Password 1

Sector protected by Password 2

Sector protected by Password 3

System

2

I C Password

System

RF Password 1

RF Password 2

RF Password 3

8−bit DSFID

8−bit AFI

I²C Bus Protocol

The 2−wire I C bus consists of two lines, SCL and SDA,

connected to the V supply via pull−up resistors. The

Master provides the clock to the SCL line, and either the

Master or the Slaves drive the SDA line. A ‘0’ is transmitted

by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data

transfer may be initiated only when the bus is not busy (see

AC Characteristics). During data transfer, SDA must remain

stable while SCL is HIGH.

2

CC

64−bit UID

2

4−bit I C Write Lock bits

20−bit SSS

Figure 4. Memory Organization

START/STOP Condition

Sector Security Status

An SDA transition while SCL is HIGH creates a START

or STOP condition (Figure 5). The START consists of

a HIGH to LOW SDA transition, while SCL is HIGH.

Absent the START, a Slave will not respond to the Master.

The STOP completes all commands, and consists of a LOW

to HIGH SDA transition, while SCL is HIGH.

The five Sector Security Status bits are organized as

follows (Table 9):

Table 9. SECTOR SECURITY STATUS BITS

b4

b3

b2

b1

b0

Password control bits

Read/Write

Protection bits

Sector

Lock

Device Addressing

The Master addresses a Slave by creating a START

condition and then broadcasting an 8−bit Slave address. For

the N24RF64, the first four bits of the Slave address are set

to 1010. The A2 bit is used to control the access to the user

or system memory area. The next 2 bits are set to 11. The

R/W bit tells the Slave whether the Master intends to read (1)

or write (0) data (Figure 6).

The Sector Lock bit enables (1) or disables (0) the sector

protection. The read/write protection bits (Table 10)

determine whether reading and/or writing the sector is

permitted. The password control bits (Table 11) determine

whether and which password protects the sector.

Table 10. READ/WRITE PROTECTION BITS

Acknowledge

After processing the Slave address, the Slave responds

with an acknowledge (ACK) by pulling down the SDA line

during the 9th clock cycle (Figure 7). The Slave will also

acknowledge all address bytes and every data byte presented

in Write mode if the addressed location is not write

protected. In Read mode the Slave shifts out a data byte, and

then releases the SDA line during the 9th clock cycle. As

long as the Master acknowledges the data, the Slave will

continue transmitting. The Master terminates the session by

not acknowledging the last data byte (NoACK) and by

issuing a STOP condition. Bus timing is illustrated in

Figure 8.

Sector

Lock

(b0)

Sector Access

When Password

Presented

Sector Access

When Password

Not Presented

b2, b1

xx

0

1

Read

Write

Read

Write

No Write

Write

00

01

10

No Read No Write

11

No Write No Read No Write

www.onsemi.com

8

N24RF04E

SCL

SDA

START

CONDITION

STOP

CONDITION

Figure 5. START/STOP Conditions

DEVICE ADDRESS

1

0

1

0

A2

1

R/W

NOTE: A2 bit is used to control the memory addressing: A2 = 0: User memory area; A2 = 1: System memory area

Figure 6. Slave Address Bits

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY

(RECEIVER)

SCL FROM

MASTER

1

8

9

DAT A OUTPUT

FROM TRANSMITTER

DAT A OUTPUT

FROM RECEIVER

ACK SETUP (≥ t

)

SU:DAT

START

ACK DELAY (≤ t

)

AA

Figure 7. Acknowledge Timing

t

R

F

HIGH

t

LOW

SCL

t

HD:DAT

SU:STA

t

SU:STO

t

SU:DAT

HD:STA

SDA IN

t

BUF

t

DH

AA

SDA OUT

Figure 8. Bus Timing

www.onsemi.com

9

N24RF04E

WRITE OPERATIONS

data, the internal byte address is incremented up to the end

of page, where it then wraps around (within the page). New

data can therefore replace data loaded earlier. Following the

STOP, data loaded during the Page Write session will be

Byte Write

To write data to memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘0’. The Master then sends two

address bytes and a data byte and concludes the session by

creating a STOP condition on the bus. The Slave responds

with ACK after every byte sent by the Master (Figure 9). The

STOP starts the internal Write cycle, and while this

written to memory in a single internal Write cycle (t ).

WR

Acknowledge Polling

As soon (and as long) as internal Write is in progress, the

Slave will not acknowledge the Master. This feature enables

the Master to immediately follow−up with a new Read or

Write request, rather than wait for the maximum specified

operation is in progress (t ), the SDA output is tri−stated

WR

and the Slave does not acknowledge the Master (Figure 10).

Write time (t ) to elapse. Upon receiving a NoACK

WR

response from the Slave, the Master simply repeats the

request until the Slave responds with ACK.

The remainder of the instruction is identical to a normal

Page Write.

Page Write

The Byte Write operation can be expanded to Page Write,

by sending more than one data byte to the Slave before

issuing the STOP condition (Figure 11). Up to 4 distinct data

bytes can be loaded into the internal Page Write Buffer

starting at the address provided by the Master. The page

address is latched, and as long as the Master keeps sending

Delivery State

The N24RF04E is shipped erased, i.e., all bytes from user

memory area are FFh.

BUS ACTIVITY:

S

T

A

R

T

ADDRESS

BYTE

ADDRESS

BYTE

a −a

7 0

S

T

O

P

DATA

BYTE

SLAVE

MASTER

ADDRESS

a

−a

15

8

S

* * * * * * *

P

A

C

K

A

C

K

A

C

K

A

C

K

SLAVE

*a15 − a9 = Don’t Care Bits

Figure 9. Byte Write Sequence

SCL

SDA

ACK

8th Bit

Byte n

t

WR

ADDRESS

STOP

CONDITION

START

CONDITION

Figure 10. Write Cycle Timing

BUSACTIVITY: S

ADDRESS

BYTE

ADDRESS

BYTE

a −a

7 0

DATA

BYTE

n

DATA

BYTE

n+1

DATA

BYTE

n+P

T

S

T

O

P

A

SLAVE

R

ADDRESS

MASTER

a

−a

15

8

T

S

P

* * * * * * *

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

SLAVE

*a15 − a9 = Don’t Care Bits

Figure 11. Page Write Sequence

www.onsemi.com

10

N24RF04E

READ OPERATIONS

equal to 0 and the A2 bit equal to 1 (system memory). The

device acknowledges this and expects two I C password

2

Immediate Read

address bytes, 09h and 00h. The device responds to each

address byte with an ACK. The device then expects the 4

password data bytes, the validation code, 09h, and a resend

of the 4 password data bytes. The most significant byte of the

password is sent first, followed by the least significant bytes.

The 32−bit password must be sent twice to prevent any

data corruption during the sequence. If the two 32−bit

passwords sent are not exactly the same, the command will

not be accepted.

To read data from memory, the Master creates a START

condition on the bus and then broadcasts a Slave address

with the R/W bit set to ‘1’. The Slave responds with ACK

and starts shifting out data residing at the current address.

After receiving the data, the Master responds with NoACK

and terminates the session by creating a STOP condition on

the bus (Figure 12). The Slave then returns to Standby mode.

Selective Read

When the bus master generates a Stop condition

immediately after the Ack bit, an internal delay equivalent

to the write cycle time is triggered. A Stop condition at any

other time does not trigger the internal delay. During that

delay, the N24RF04E compares the 32 received data bits

To read data residing at a specific address, the selected

address must first be loaded into the internal address register.

This is done by starting a Byte Write sequence, whereby the

Master creates a START condition, then broadcasts a Slave

address with the R/W bit set to ‘0’ and then sends two

address bytes to the Slave. Rather than completing the Byte

Write sequence by sending data, the Master then creates a

START condition and broadcasts a Slave address with the

R/W bit set to ‘1’. The Slave responds with ACK after every

byte sent by the Master and then sends out data residing at

the selected address. After receiving the data, the Master

responds with NoACK and then terminates the session by

creating a STOP condition on the bus (Figure 13).

2

with the 32 bits of the stored I C password.

If the values match, the write access rights to all protected

sectors are modified after the internal delay. If the values do

not match, the protected sectors remains protected.

During the internal delay, the SDA output is tri−stated and

the Slave does not acknowledge the Master.

I²C Write Password

2

The I C Write Password command is used to overwrite the

2

32−bit I C password block. This command is used in I C

Sequential Read

2

mode to update the I C password value. It cannot be used to

If, after receiving data sent by the Slave, the Master

responds with ACK, then the Slave will continue

transmitting until the Master responds with NoACK

followed by STOP (Figure 14). During Sequential Read the

internal byte address is automatically incremented up to the

end of memory, where it then wraps around to the beginning

of memory.

modify any of the RF passwords. After the write cycle, the

2

new I C password value is automatically activated. The I C

password value can only be modified after issuing a valid

2

I C Present Password command.

Following a Start condition, the master sends a write

instruction with the slave address with the Read/Write bit

equal to 0 and the A2 bit equal to 1 (system memory). The

2

I²C SECURITY

device acknowledges this and expects two I C password

In the I²C mode it is possible to protect each memory

sector from user area against write operations. The sector

write access is controlled using the 4−bit I2C_Write_Lock

address bytes, 09h and 00h. The device responds to each

address byte with an ACK. The device then expects the 4

password data bytes, the validation code, 07h, and a resend

of the 4 password data bytes. The most significant byte of the

password is sent first, followed by the least significant bytes.

2

bit area and the 32−bit I C password. There are two

2

commands to control the I C password: I C Present

2

Password and I C Write Password.

N24RF04E is shipped with the default I C password

00000000h. By default, the password is activated.

The 32−bit password must be sent twice to prevent any

data corruption during the sequence. If the two 32−bit

passwords sent are not exactly the same, the command will

not be accepted.

When the bus master generates a Stop condition

immediately after the Ack bit, the internal write cycle is

triggered. A Stop condition at any other time does not trigger

the internal write cycle.

I²C Present Password

The I C Present Password command is used to modify the

write access rights of the sectors protected by the I C

Write−Lock bits, including the password itself. N24RF04E

2

will allow this only if the correct password is presented, via

2

I C bus. If the password is correct, the access rights remain

2

activated until a new I C Present Password command is

received, or the device is powered off.

Following a Start condition, the master sends a write

instruction with the slave address with the Read/Write bit

During the internal write cycle, the SDA output is

tri−stated and the Slave does not acknowledge the Master.

www.onsemi.com

11

N24RF04E

BUS ACTIVITY:

MASTER

N

O

A

C

K

S

T

A

R

T

S

T

SLAVE

ADDRESS

O

P

S

P

A

C

K

DATA

BYTE

SLAVE

8

9

SCL

SDA

8th Bit

DATA OUT

NO ACK

STOP

Figure 12. Immediate Read Sequence and Timing

BUS ACTIVIT Y:

MASTER

S

T

S

N

O

A

C

K

T

A

R

S

T

O

P

ADDRESS

BYTE

A

R

SLAVE

ADDRESS

SLAVE

ADDRESS

BYTE

a

−a

8

15

T

S

P

* * * * * * *

A

C

K

A

C

K

A

C

K

A

C

K

DATA

BYTE

SLAVE

*a15 − a9 = Don’t Care Bits

Figure 13. Selective Read Sequence

N

BUS ACTIVITY:

MASTER

O

S

SLAVE

ADDRESS

A T

O

C

K P

P

A

C

K

A

C

K

A

C

K

A

C

K

DATA

BYTE

n

DATA

BYTE

n+1

DATA

BYTE

n+x

DATA

BYTE

n+2

SLAVE

Figure 14. Sequential Read Sequence

Configuration Byte

The configuration byte, as shown in Table 12, contains

8−bit non−volatile.

Table 12. CONFIGURATION BYTE

2

I C byte Address

7

6

5

4

3

2

1

0

A2=1

2320

x

RF WIP/BUSY

EH_mode

EH_cfg1

NOTE: bit 4− bit 7 = don’t care bits

The EH_cfg0 and EH_cfg1 (Energy Harvesting

configuration) bits determine the limit of the current

The typical characteristics of the V

configuration are shown in Figure 15.

vs. I

for each

OUT

Load

consumption on the V

pin. They are set/reset in RF mode

OUT

by using the WriteEHCfg command.

www.onsemi.com

12

N24RF04E

EH_cfg = 01, H_ISO = 2.4 A/m

EH_cfg = 00, H_ISO = 3.5 A/m

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

Iload [mA]

−40°C

+25°C

+90°C

+105°C

−40°C

+25°C

+90°C

+105°C

EH_cfg = 10, H_ISO = 1.6 A/m

EH_cfg = 11, H_ISO = 1 A/m

5

4

3

2

1

0

5

4

3

2

1

0

1

2

3

4

5

0

1

2

3

4

5

Iload [mA]

+25°C

Iload [mA]

+25°C

−40°C

+90°C

+105°C

−40°C

+90°C

+105°C

Figure 15. VOUT vs. ILOAD

The EH_mode (Energy Harvesting mode) bit determine

the value of the EH_enable bit from the control register after

power−up (Table 14). This is set/reset in RF mode by using

the WriteEHCfg command.

The RF WIP/BUSY bit is used to configure the RF

WIP/BUSY output. When set to 0, the RF WIP/BUSY

output is configured in the RF busy mode and the RF

WIP/BUSY output is tied to 0 from the SOF until to the end

of the RF command. When set to1, the RF WIP/BUSY

output is configured in the RF write in progress mode and the

RF WIP/BUSY output is tied to 0 during an internal write

cycle. During an I C write operation the RF WIP/BUSY

output is in High−Z state. This is set/reset in the RF mode by

2

using the WriteDOCfg command.

2

In the I C mode, the configuration byte can be read and

2

write by using an I C instruction.

Control Register

The control register, as shown in Table 13, contains 8−bit

volatile.

Table 13. CONTROL REGISTER

2

I C byte Address

7

6

5

4

3

2

1

0

A2=1

2336

WTL

0

FIELD_ON

EH_enable

NOTE: bit 1- bit 7 = read−only bits

The EH_enable (Energy Harvesting enable) bit is

set/reset by using the SetRstEHEn command in the RF mode

or by using a write instruction in the I C mode. When set

to 1, the Energy Harvesting mode is enabling and when set

to 0, the Energy Harvesting mode is disabling. After

power−up, this bit is updated according to the value of the

EH_mode bit from Configuration byte (Table 12).

The FIELD_ON bit indicates if the RF field is strong

enough to execute RF commands. When the FIELD_ON is

1 the N24RF04E is able to execute RF commands and when

2

www.onsemi.com

13

N24RF04E

the FIELD_ON is 0 the N24RF04E is not able to execute RF

write cycle and set to 1 at the end of the internal write cycle.

commands.

This bit is read−only and reset to 0 after power−up.

2

The WTL (Write Time Latch) bit indicates whether the

device has performed a write operation. This bit is

automatically reset to 0 at the beginning of each internal

In the I C mode the control register can be read and write

2

by using an I C instruction.

Table 14. EH_enable BIT AFTER POWER−UP

EH_mode

EH_enable after Power−up

Energy Harvesting after Power−up

0

1

0

enabled

disabled

www.onsemi.com

14

N24RF04E

Communication from RF Reader to N24RF04E Tag

RF MODE OPERATION

The communication between the RF Reader and memory

tag uses the ASK (Amplitude Shift Keying) modulation.

The received signal is demodulated by the ASK

demodulator of the memory tag. The N24RF04E supports

both 100% and 10% modulation index. The Reader selects

which index is used. Figure 2 shows the 100% ASK

modulation waveform.

The data transmission uses pulse position coding

described in the ISO 15693: 1 out of 256 data coding with

a resulting data rate of 1.65 Kb/s or 1 out of 4 data coding

with a data rate of 26.48 Kb/s.

The communication protocol between the RF Reader and

the N24RF04E tag is based on the RTF technique (Reader

Talks First):

• Activation of the N24RF04E memory tag by the

electromagnetic field of the RF Reader

• Transmission of a command / request by the RF Reader

• Transmission of a response by the memory tag

The memory tag operates continuously under the

electromagnetic field (H) generated by the RF Reader. The

transmission of data and power is based on inductive

The request from RF Reader to the memory tag consists

of: a request SOF, flags, command code, parameters, data,

2−byte CRC, a request EOF. The SOF defines the data

coding mode that will be used by the RF Reader for the

following command. Figure 16 shows a SOF to select 1 out

of 256 data coding and Figure 17 illustrates the SOF to select

1 out of 4.

coupling using the carrier frequency (f ) as 13.56 MHz

7 kHz per ISO 15693 standard.

Each request from the Reader and each response from the

N24RF04E tag are organized in a frame, delimited by a start

of frame (SOF) and an end of frame (EOF).

C

9.44 ms

37.76 ms

Figure 16. Request SOF for 1 Out of 256 Data Coding

9.44 ms

9.44 ms 9.44 ms

37.76 ms

Figure 17. Request SOF for 1 Out of 4 Data Coding

Communication from N24RF64 Tag to RF Reader

supported by the memory tag using one carrier and two

carriers format.

The communication between the N24RF04E memory tag

and the RF reader uses the load modulation with Manchester

data coding. Via the inductive coupling, the carrier is loaded

to generate a subcarrier with fs frequency. The device

supports the one−subcarrier with 423.75 kHz (fc/32)

frequency and two−subcarrier response with 423.75 kHz

(fc/32) and 484.28 kHz (fc/28) frequencies. The

one−subcarrier or two−subcarrier response format is

selected by the RF Reader.

The N24RF04E responds using the low or high data rate

for standard commands. The fast commands use a data rate

multiplied by two. The data rate is selected by the RF Reader

through the protocol header. Table 15 shows the data rates

Table 15. TAG RESPONSE DATA RATES

One−

Two−

Subcarrier Subcarrier

Command Type

Data Rate

Standard Commands

Low

6.62 Kb/s

(fc/2048)

6.67 Kb/s

(fc/2032)

Fast Commands

Standard Commands

Fast Commands

Low

High

13.24 Kb/s

(fc/1024)

N/A

26.48 Kb/s

(fc/512)

26.69 Kb/s

(fc/508)

52.97 Kb/s

(fc/256)

N/A

www.onsemi.com

15

N24RF04E

The N24RF64 supports the following commands in RF mode:

Table 16. RF COMMAND DESCRIPTION

Nr

1

Command Name

Inventory

Command Description

Perform the anticollision sequence

2

Stay quiet

Set the N24RF04E in the quiet state

Read the requeted block

3

Read single block

Write single block

Read multiple blocks

Select

4

Write the requested block if it is not locked

Read the requested blocks

5

6

Set the N24RF04E in the selected state

Set the N24RF04E in the ready state

Write the AFI register

7

Reset to ready

Write AFI

8

9

Lock AFI

Lock the AFI register

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Write DSFID

Write the DSFID register

Lock DSFID

Lock the DSFID register.

Get system information

Get multiple block security status

Write sector password

Lock sector

Read the system information value

Read the sector security status of the requested blocks

Write the selected password

Write the sector security status bits of the requested sector

Allows the user to present a password to unprotect the sectors or to change the password

Read the requested block

Present sector password

Fast read single block

Fast inventory initiated

Fast initiate

Perform the anticollision sequence if the internal initiate flag is set

Set the internal initiate flag

Fast read multiple blocks

Inventory initiated

Initiate

Read the requested blocks

Perform the anticollision sequence if the internal initiate flag is set

Set the internal initiate flag

ReadCfg

Read the Configuration byte

WriteEHCfg

Write the energy harvesting configuration bits into the Configuration byte

Write the EH_enable bit into the Control register

Read the Control register

SetRstEHEn

CheckEHEn

WriteDOCfg

Write the RF WIP/BUSY bit into the Configuration byte

Table 17. RF COMMAND FORMAT

IC Mfg.

Code

Optional

AFI

Nr. Crt.

Function

SOF

Flags

Command

UID

Number

Data

CRC16 EOF

1

Inventory

x

8 bits

01h

−

8 bits

(Note 12)

0 to 8

bytes

(Note 15)

16 bits

x

2

3

Stay quiet

x

8 bits

02h

20h

−

8 bytes

−

16 bits

x

Read single

block

8 bytes

(Note 11)

8 bits

(Note 13)

4

5

6

Write single

block

x

8 bits

21H

23H

25h

−

8 bytes

−

8 bits

32 bits

16 bits

x

(Note 11)

(Note 13)

Read multiple

blocks

8 bytes

(Note 11)

8 bits

(Note 13)

8 bits

(Note 16)

Select

8 bytes

−

www.onsemi.com

16

N24RF04E

Table 17. RF COMMAND FORMAT (continued)

IC Mfg.

Code

Optional

AFI

Nr. Crt.

Function

SOF

Flags Command

UID

Number

Data

CRC16 EOF

7

Reset to

ready

x

8 bits

26h

27h

28h

29h

2Ah

2Bh

2Ch

−

8 bytes

−

16 bits

x

(Note 11)

8

Write AFI

x

−

8 bytes

(Note 11)

−

8 bits

9

Lock AFI

8 bytes

(Note 11)

−

8 bits

−

10

11

12

13

Write DSFID

Lock DSFID

8 bytes

(Note 11)

8 bytes

(Note 11)

GET system

information

8 bytes

(Note 11)

−

Get multiple

block security

status

8 bytes

(Note 11)

8 bits

(Note 13)

8 bits

(Note 16)

14

15

16

17

18

Write sector

password

x

8 bits

B1h

B2h

B3h

C0h

C1h

67h

8 bytes

−

8 bits

32 bits

8 bits

32 bits

−

16 bits

x

(Note 11)

(Note 14)

Lock sector

8 bytes

(Note 11)

8 bits

(Note 13)

Present sector

password

8 bytes

(Note 11)

−

8 bits

(Note 14)

Fast read

single block

8 bytes

(Note 11)

−

8 bits

(Note 13)

Fast inventory

initiated

−

8 bits

(Note 12)

0 to 8

bytes

(Note 15)

19

20

Fast initiate

x

8 bits

C2h

C3h

67h

−

16 bits

x

Fast read

multiple blocks

8 bytes

(Note 11)

8 bits

(Note 13)

8 bits

(Note 16)

21

Inventory

initiated

x

8 bits

D1h

67h

−

8 bits

(Note 12)

0 to 8

bytes

(Note 15)

16 bits

x

22

23

Initiate

x

8 bits

D2h

A0h

67h

−

16 bits

x

ReadCfg

8 bytes

(Note 11)

24

25

26

27

WriteEHCfg

SetRstEHEn

CheckEHEn

WriteDoCfg

x

8 bits

A1h

A2h

A3h

A4h

67h

8 bytes

−

8 bits

−

16 bits

x

(Note 11)

8 bytes

(Note 11)

8 bytes

(Note 11)

8 bytes

(Note 11)

8 bits

11. UID optional.

12.Mask length.

13.Block number/First block number.

14.Password number.

15.Mask value.

16.Number of blocks.

www.onsemi.com

17

N24RF04E

Table 18. INSTRUCTION RESPONSE FORMAT (No Error)

Nr.

Crt.

Flags

Response

Memory

Size

IC

Ref

Function

SOF

Data Byte

UID

DSFID

AFI

Data

CRC16 EOF

1

Inventory

x

00h

DSFID

8

−

16 bits

x

bytes

2

3

Stay quiet

−

Read single

block

x

00h

SSS

(Note 17)

32 bits

16 bits

x

4

5

Write single

block

x

00h

−

16 bits

x

Read multiple

blocks

SSS

(Note 17, 18)

32 bits

(Note 18)

6

7

Select

Reset to ready

Write AFI

x

00h

−

16 bits

x

−

8

−

9

Lock AFI

−

10

11

12

Write DSFID

Lock DSFID

−

Get system

information

0Fh

8

8 bits

8

bits

16 bits

8 bits

bytes

13

14

Get multiple

block security

status

x

00h

SSS

(Note 18)

−

16 bits

x

Write sector

password

−

15

16

Lock sector

x

00h

−

16 bits

x

Present sector

password

17

Fast read

single block

x

00h

SSS

(Note 17)

−

32 bits

16 bits

x

18

19

20

Fast inventory

Initiated

x

00h

DSFID

8

−

16 bits

x

bytes

Fast initiate

DSFID

8

bytes

Fast read

multiple blocks

SSS

(Note 17, 18)

−

32 bits

(Note 18)

21

22

Inventory

initiated

x

00h

DSFID

8

−

16 bits

x

bytes

Initiate

DSFID

8

bytes

23

24

25

26

27

ReadCfg

WriteEHCfg

SetRstEHEn

CheckEHEn

WriteDoCfg

x

00h

−

8 bits

16 bits

x

−

8 bits

−

17.SSS optional (FL_OPT = 1).

18.Repeated as needed.

www.onsemi.com

18

N24RF04E

Table 19. INSTRUCTION RESPONSE FORMAT (Error Flag = 1)

Flags

Response

Nr. Crt.

1

Function

Inventory

SOF

−

x

Error Code

−

CRC16

−

EOF

−

x

−

2

Stay quiet

−

3

Read single block

Write single block

Read multiple block

Select

01h

−

8 bits

−

16 bits

−

4

x

5

x

6

x

7

Reset to ready

Write AFI

x

8

x

9

Lock AFI

x

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Write DSFID

x

Lock DSFID

x

Get system information

Get multiple block security status

Write sector password

Lock sector

x

Present sector password

Fast read single block

Fast inventory initiated

Fast initiate

x

−

x

−

x

−

Fast read multiple blocks

Inventory initiated

Initiate

01h

−

8 bits

−

16 bits

−

x

−

x

−

ReadCfg

01h

8 bits

16 bits

WriteEHCfg

x

SetRstEHEn

x

CheckEHEn

x

WriteDoCfg

x

www.onsemi.com

19

N24RF04E

Table 20. RESPONSE ERROR CODE

Error Code

02h

−

03h

−

x

0Fh

−

10h

11h

−

12h

−

13h

−

14h

−

15h

−

Nr. Crt.

Function

Inventory

1

2

−

x

Stay quiet

−

3

Read single block

Write single block

Read multiple blocks

Select

−

x

4

−

x

−

x

−

x

−

5

−

x

−

x

6

−

x

−

x

−

7

Reset to ready

Write AFI

−

x

−

8

−

x

−

x

−

9

Lock AFI

−

x

−

x

−

x

−

10

11

12

13

Write DSFID

Lock DSFID

−

x

−

x

−

x

−

x

−

x

−

Get system information

−

x

−

Get multiple block security

status

−

x

−

14

15

16

17

18

19

20

21

22

23

24

25

26

27

Write sector password

Lock sector

x

−

x

−

x

−

x

−

x

−

x

−

x

−

x

−

x

−

x

−

x

Present sector password

Fast read single block

Fast inventory initiated

Fast initiate

x

−

x

−

x

−

x

Fast read multiple blocks

Inventory initiated

Initiate

−

ReadCfg

WriteEHCfg

SetRstEHEn

−

x

CheckEHEn

WriteDoCfg

Table 21. ERROR CODE

Error Code

02h

Meaning

The command is not recognized

The option is not supported

Error with no information given

03h

0Fh

10h

The specified block is not available (doesn’t exist)

11h

The specified block is already locked and thus cannot be locked again

The specified block is locked and its content cannot be changed

The specified block was not successfully programmed

The specified block was not successfully locked

12h

13h

14h

15h

The specified block is read−protected

www.onsemi.com

20

N24RF04E

Table 22. REQUEST FLAGS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Protocol

Extension

Flag

Data

Rate

Flag

Sub −

Carrier

Flag

Option Address Nb_Slots Select

AFI

Flag

Inventory

Flag

0

Flag

−

Flag

0/1

−

Flag

−

RFU

Nr. Crt.

Function

Inventory

1

2

3

4

5

0

0/1

−

0

1

0

0/1

Stay quiet

0

1

0

Read single block

Write single block

0/1

−

0/1

−

Read multiple

blocks

−

6

7

Select

Reset to ready

Write AFI

0

1

−

0

−

0

0/1

0

0/1

8

0/1

0

9

Lock AFI

10

11

12

Write DSFID

Lock DSFID

Get system

information

13

14

Get multiple

block security

status

0

0/1

−

0/1

−

0

0/1

Write sector

password

0/1

15

16

Lock sector

0

0/1

0

0/1

−

0/1

−

0

0/1

Present sector

password

17

18

Fast read single

block

0

0/1

0

0/1

−

0/1

−

0

1

0/1

0

Fast inventory

initiated

−

0/1

−

0/1

19

20

Fast initiate

0

−

0

−

0

0/1

0

Fast read

multiple blocks

0/1

21

Inventory

iInitiated

0

−

0/1

−

0/1

0

1

0/1

22

23

24

25

26

27

Initiate

0

−

0

−

0

0/1

ReadCfg

0/1

WriteEHCfg

SetRstEHEn

CheckEHEn

WriteDoCfg

0/1

0

0/1

www.onsemi.com

21

N24RF04E

ORDERING INFORMATION

Specific Device

†

Device Order Number

Marking

Package Type

Temperature Range

Lead Finish

Shipping

N24RF04EDWPT3G

RF04EH

SOIC−8

NiPdAu

3000 / Tape & Reel

−40°C to 105°C

(Pb−Free)

N24RF04EDTPT3G

04EH

TSSOP−8

NiPdAu

-40°C to 105°C

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

19.All packages are RoHS−compliant (Pb−Free, Halogen−free).

20.Contact factory for availability.

2

ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.

www.onsemi.com

22

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−8, 150 mils

CASE 751BD

ISSUE O

DATE 19 DEC 2008

SYMBOL

MIN

NOM

MAX

1.35

A

1.75

A1

b

0.10

0.33

0.19

4.80

5.80

3.80

0.25

0.51

0.25

5.00

6.20

4.00

c

E1

E

D

E

E1

e

h

L

θ

1.27 BSC

0.25

0.40

0º

0.50

1.27

8º

PIN # 1

IDENTIFICATION

TOP VIEW

D

h

A1

θ

A

c

e

b

L

SIDE VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34272E

SOIC 8, 150 MILS

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TSSOP8, 4.4x3.0, 0.65P

CASE 948AL

ISSUE A

DATE 20 MAY 2022

q

GENERIC

MARKING DIAGRAM*

XXX

YWW

AG

XXX = Specific Device Code

Y

= Year

WW = Work Week

A

G

= Assembly Location

= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may

or may not be present. Some products may

not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON34428E

TSSOP8, 4.4X3.0, 0.65P

PAGE 1 OF 1

onsemi and

are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves

the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	N24RF04EDTPT3G
厂家：	ONSEMI
描述：	Dual Interface RFID 4 Kb EEPROM Tag ISO 15693 RF, I2C Bus, Energy Harvesting 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管商用集成电路
文件：	总25页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

N24RF04EDTPT3G [ONSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E