NB3H60113GH3MTR2G [ONSEMI]
2.5 V Programmable OmniClock Generator with Differential LVDS Output. ;
| 型号： | NB3H60113GH3MTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V Programmable OmniClock Generator with Differential LVDS Output. |
| 文件： | 总12页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
2.5 V Programmable OmniClock
Generator
with Differential LVDS Output
WDFN8
CASE 511AT
NB3H60113GH3
The NB3H60113GH3, which is a member of the OmniClock family,
is a one−time programmable (OTP), low power PLL−based clock
generator that supports differential 125 MHz frequency output.
The device accepts a single ended LVCMOS reference Clock as input.
It generates one differential LVDS output. The device can be powered
down using the Power Down pin (PD#).
MARKING DIAGRAM
1
H3MG
G
H3 = Specific Device Code
M
G
= Date Code
= Pb−Free Device
Features
• Member of the OmniClock Family of Programmable Clock
Generators
(Note: Microdot may be in either location)
• Operating Power Supply: 2.5 V 10%
• I/O Standards
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
♦ Input: LVCMOS Clock
♦ Output: LVDS
• 1 Programmable Differential Clock Output of 125 MHz
• Input Frequency Range
♦ Reference Clock: 25 MHz
• Power Saving mode through Power Down Pin
• Programming and Evaluation Kit for Field Programming and Quick
Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
• These are Pb−Free Devices
Typical Applications
• Telecom Networks
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
March, 2022 − Rev. 0
NB3H60113GH3/D
NB3H60113GH3
BLOCK DIAGRAM
VDD
PD#
Output Control
Clock Control
Configuration
Memory
Output
Divider
Frequency
Diff
Buffer
CLK0
PLL Block
Phase
Detector
CLKIN
NC
Charge
Pump
Clock Buffer
Oscillator
and AGC
VCO
Output
Divider
Diff
Buffer
CLK1
NC
Feedback
Divider
GND
Notes:
1. CLK0 and CLK1 can be configured to be LVDS differential output.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
CLKIN
NC
1
8
7
6
5
NC
2
3
4
VDD
NB3H60113GH3
PD#
GND
CLK1
CLK0
Figure 2. Pin Connections (Top View) – WDFN8
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2
NB3H60113GH3
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
CLKIN
NC
Pin Type
Input
Description
1
2
3
25 MHz single−ended reference input clock
Output
Input
No connect, to be left open floating
PD#
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set out-
puts Low. Internal pull−down resistor. This pin needs to be pulled High for normal operation
of the chip.
4
5
GND
Ground
Power supply ground
CLK0
DIFF
Output
Supports 125 MHz LVDS differential signal. The differential outputs will be complementary
LOW/HIGH until the PLL has locked and the frequency has stabilized.
6
CLK1
DIFF
Output
Supports 125 MHz LVDS differential signal. The differential outputs will be complementary
LOW/HIGH until the PLL has locked and the frequency has stabilized.
7
8
VDD
NC
Power
Output
2.5 V power supply
No connect, to be left open floating
Table 2. POWER DOWN FUNCTION TABLE
PD#
0
Function
Device Powered Down
Device Powered Up
1
FUNCTIONAL DESCRIPTION
The NB3H60113GH3 is a 2.5 V programmable
differential clock generator, designed to meet the clock
requirements for Telecom markets. It has a small package
size and it requires low power during operation and while in
standby. This device provides the ability to configure a
number of parameters as detailed in the following section.
The One−Time Programmable memory allows
programming and storing of one configuration in the
memory space.
0.1 mF and 0.01 mF close to the VDD pin as shown in
Figure 3.
Clock Input
Input Frequency
The clock input block can be programmed to use a single
ended reference clock source 25 Mhz.
Programmable Clock Outputs
Output Type and Frequency
Power Supply
The NB3H60113GH3 provides one 125 MHz differential
output.
Device Supply
Here CLK0 and CLK1 configured for LVDS differential
clocking. Refer to the Application Schematic in Figure 3.
The NB3H60113GH3 is designed to work with a 2.5 V
VDD power supply. In order to suppress power supply noise
it is recommended to connect decoupling capacitors of
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3
NB3H60113GH3
VDD (2.5 V)
0.01 mF
0.1 mF
1 mF
Reference
Clock Input
CLK0
CLK1
CLKIN
25 MHz
125 Mhz LVDS
Differential Clock
NB3H60113GH3
GND
VDD
PD#
Figure 3. Power Supply Noise Suppression and Differential Output Application setup
Control Inputs
functions are disabled by default and when PD# pin is pulled
high the chip functions are activated.
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS active Low
Master Reset that disables the device and sets outputs Low.
By default it has an internal pull−down resistor. The chip
Configuration Space
NB3H60113GH3 has one Configuration. Table 3 shows
the device configuration.
Table 3. EXAMPLE CONFIGURATION
Output
Enable
Input Frequency
Output Frequency
VDD
Notes
25 MHz
CLK0 = 125 MHz
CLK1 = 125 MHz
2.5 V
CLK0 = Y
CLK1 = Y
CLK0/CLK1 = LVDS CLK2: NC
Table 4. ATTRIBUTES
Characteristic
ESD Protection Human Body Model
Value
2 kV
50 kW
Internal Input Default State Pull up/ down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
MSL1
UL 94 V−0 @ 0.125 in
130 k
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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4
NB3H60113GH3
Table 5. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
Parameter
Positive power supply with respect to Ground
Rating
−0.5 to +4.6
−0.5 to VDD + 0.5
−40 to +85
−65 to +150
265
Unit
V
VDD
V , V
Input/Output Voltage with respect to chip ground
Operating Ambient Temperature Range (Industrial Grade)
Storage temperature
V
I
O
T
A
°C
°C
°C
T
STG
SOL
T
Max. Soldering Temperature (10 sec)
q
Thermal Resistance (Junction−to−ambient)
(Note 3)
0 lfpm
500 lfpm
129
84
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−case)
35 to 40
125
°C/W
°C
JC
T
Junction temperature
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
Table 6. RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Core Power Supply Voltage
Reference Clock Frequency
Condition
2.5 V operation
Min
Typ
2.5
25
Max
Unit
V
V
DD
2.25
2.75
fclkin
Single ended clock Input
MHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
NB3H60113GH3
Table 7. DC ELECTRICAL CHARACTERISTICS (V = 2.5 V 10%; GND = 0 V, T = −40°C to 85°C, Notes 4, 9)
DD
A
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I
Power Supply current for core
Configuration Dependent.
13
mA
DD_2.5 V
V
= 2.5 V, T = 25°C,
A
DD
CLKIN = 25 MHz
CLK[0:1] = 125 MHz
I
Power Down Supply Current
Input HIGH Voltage
PD# is Low to make all outputs OFF
20
mA
PD
V
V
Pin XIN
0.65 V
V
DD
IH
DD
Pin PD#
0.85 V
V
DD
DD
V
IL
Input LOW Voltage
V
Pin XIN
0
0
0.35 V
0.15 V
DD
DD
Pin PD#
Zo
Nominal Output Impedance
Configuration Dependent
22
80
W
R
Internal Pull up/ Pull down resistor
V
DD
= 2.5 V
kW
PUP/PD
LVDS OUTPUTS (Notes 5 and 6)
Differential Output Voltage
V
250
0
450
25
mV
mV
mV
mV
mV
mV
mA
OD_LVDS
DeltaV
Change in Magnitude of VOD for Complementary Output States
Offset Voltage
OD_LVDS
OS_LVDS
V
1200
Delta V
Change in Magnitude of VOS for Complementary Output States
0
25
OS_LVDS
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 8)
V
V
= 2.5 V
= 2.5 V
1425
1075
20
1600
OH_LVDS
DD
DD
V
900
OL_LVDS
I
f
= 125 MHz
DD_LVDS
out
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Measurement taken with differential clock terminated with test load of 2 pF. See Figure 6.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx–.
6. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 5.
7. VOHmax = VOSmax + 1/2 VODmax.
8. VOLmax = VOSmin − 1/2 VODmax.
9. Parameter guaranteed by design verification not tested in production.
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6
NB3H60113GH3
Table 8. AC ELECTRICAL CHARACTERISTICS (V = 2.5 V 10%, GND = 0 V, T = −40°C to 85°C, Note 10)
DD
A
Symbol
Parameter
Conditions
Min
Typ
125
3.0
Max
Unit
MHz
ms
fout
Differential Output Frequency
Stabilization time from Power−up
Stabilization time from Power Down
t
t
V
DD
= 2.5 V with Frequency Modulation
PU
PD
Time from falling edge on PD# pin to
tri−stated outputs (Asynchronous)
3.0
ms
Eppm
Synthesis Error
Configuration Dependent
0
ppm
ps
DIFFERENTIAL OUTPUT (CLK1, CLK0) (V = 2.5 V 10%; T = −40°C to 85°C, Note 10)
DD
A
t
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz input,
100
JITTER−2.5 V
f
= 125 MHz, SS off
out
(Notes 10 and 11, see Figure 7)
Cycle−Cycle Peak to Peak Jitter
Rise Time
Configuration Dependent. 25 MHz input,
100
ps
ps
ps
%
f
= 125 MHz, SS off
out
(Notes 10, and 11, see Figure 7)
t
Measured between 20% to 80%
DD
175
175
700
700
r 2.5 V
V
= 2.5 V
LVDS
LVDS
t
Fall Time
Measured between 20% to 80%
f 2.5 V
V
DD
= 2.5 V
t
Output Clock Duty Cycle
V
= 2.5 V;
DC
DD
Duty Cycle of Ref clock is 50%
PLL Clock
Reference Clock
45
40
50
50
55
60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of
the output. For application specific AC performance parameters, please contact onsemi.
11. Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
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NB3H60113GH3
SCHEMATIC FOR OUTPUT TERMINATION
VDD (2.5 V)
Reference
Clock Input
CLKIN
CLK0
CLK1
Z
= 50 W
O
Differential
Output
R = 100 W
Z
O
= 50 W
Receiver
NB3H60113GH3
GND
VDD
PD#
Figure 4. Typical Termination for Differential Signaling Device Load
PARAMETER MEASUREMENT TEST CIRCUITS
CLK1
Hi−Z Probe
Hi−Z Probe
Measurement
Equipment
LVDS
Clock
100 W
CLK0
Figure 5. LVDS Parameter Measurement
TIMING MEASUREMENT DEFINITIONS
t
2
t
t
= 100 * t /t
1 2
DC
t
1
= t
2
Period
80%
20%
80%
20%
Vcross = 50% of output swing
DVcross
t
r
t
f
Figure 6. Differential Measurement for AC Parameters
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8
NB3H60113GH3
t
period−jitter
50% of CLK Swing
Clock
Output
t
t
(N+1)cycle
Ncycle
50% of CLK Swing
Clock
Output
t
= t
− t
CTC−jitter
(N+1)cycle Ncycle (over 1000 cycles)
Figure 7. Period and Cycle−Cycle Jitter Measurement
Tpower-up
Tpower-down
PD#
VIH
VIL
CLK Output
Figure 8. Output Enable/ Disable and Power Down Functions
APPLICATION GUIDELINES
VDD
Output Interface and Terminations
The NB3H60113GH3 consists of a Output Driver to
support LVDS standards. Termination techniques required
is as shown in Figure 4.
Iss
LVDS Interface
Differential signaling like LVDS has inherent advantage
of common mode noise rejection and low noise emission,
and thus a popular choice clock distribution in systems.
CLK1
+
RT
100 W
TIA/EIA−644 or LVDS is
a standard differential,
Vout
_
point−to−point bus topology that supports fast switching
speeds and has benefit of low power consumption. The
driver consists of a low swing differential with constant
current of 3.5 mA through the differential pair, and
generates switching output voltage across a 100 W
terminating resistor (externally connected or internal to the
CLK0
+
_
Vin
Iss
2
receiver). Power dissipation in LVDS standard ((3.5 mA) x
100 W = 1.2 mW) is thus much lower than other differential
signalling standards.
Figure 9. Simplified LVDS Output Structure with
Termination
A fan−out LVDS buffer (like onsemi’s NB6N1xS and
NB6L1xS) can be used as an extension to provide clock
signal to multiple LVDS receivers to drive multiple
point−to−point links to receiving node.
Recommendation for Clock Performance
Clock performance is specified in terms of Jitter in time
the domain and Phase noise in frequency domain. Details
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9
NB3H60113GH3
Ringing
Overshoot
and measurement techniques of Cycle−cycle jitter, period
jitter, TIE jitter and Phase Noise are explained in application
note AND8459/D.
(Positive)
In order to have a good clock signal integrity for minimum
data errors, it is necessary to reduce the signal reflections.
Reflection coefficient can be zero only when the source
impedance equals the load impedance. Reflections are based
on signal transition time (slew rate) and due to impedance
mismatch. Impedance matching with proper termination is
required to reduce the signal reflections. The amplitude of
overshoots is due to the difference in impedance and can be
minimized by adding a series resistor (Rs) near the output
pin. Greater the difference in impedance, greater is the
amplitude of the overshoots and subsequent ripples. The
ripple frequency is dependant on the signal travel time from
the receiver to the source. Shorter traces results in higher
ripple frequency, as the trace gets longer the travel time
increases, reducing the ripple frequency. The ripple
frequency is independent of signal frequency, and only
depends on the trace length and the propagation delay. For
eg. On an FR4 PCB with approximately 150 ps/ inch of
propagation rate, on a 2 inch trace, the ripple frequency = 1
/ (150 ps * 2 inch * 5) = 666.6 MHz; [5 = number of times
the signal travels, 1 trip to receiver plus 2 additional round
trips]
Overshoot
(Negative)
Figure 10. Signal Reflection Components
PCB Design Recommendation
For a clean clock signal waveform it is necessary to have
a clean power supply for the device. The device must be
isolated from system power supply noise. A 0.1 mF and a
2.2 mF decoupling capacitor should be mounted on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin and the
ground via should be kept thicker and as short as possible.
All the VDD pins should have decoupling capacitors.
Stacked power and ground planes on the PCB should be
large. Signal traces should be on the top layer with minimum
vias and discontinuities and should not cross the reference
planes. The termination components must be placed near the
source or the receiver. In an optimum layout all components
are on the same side of the board, minimizing vias through
other signal layers.
PCB traces should be terminated when trace length tr/f /
(2* tprate); tr/f = rise/ fall time of signal, tprate =
propagation rate of trace.
Device Applications
The NB3H60113GH3 is targeted mainly for the Telecom
market segment and can be used as per the examples below
Figure 11.
VDD
PD#
Output Control
Clock Control
Configuration
Memory
Output
Divider
Frequency
LVCMOS
Diff
CLK0
Buffer
PLL Block
Phase
Detector
CLKIN
LVDS
Charge
Pump
Clock Buffer
Oscillator
and AGC
VCO
Output
Divider
Diff
Buffer
CLK1
NC
NC
Feedback
Divider
GND
Figure 11. Application as Level Translator
NOTE: LVCMOS signal level cannot be translated to a higher level of LVCMOS voltage.
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10
NB3H60113GH3
ORDERING INFORMATION
Device
†
Case
Package
Shipping
NB3H60113GH3MTR2G
511AT
DFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NB3H60113GH3
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
2.00 BSC
0.50 BSC
D
E
e
DETAIL B
L
0.40
---
0.50
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
A
ALTERNATE
CONSTRUCTIONS
8X
0.05
C
A1
A3
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
7X
0.78
PACKAGE
OUTLINE
e/2
e
DETAIL A
7X
L
4
1
L2
2.30
0.88
1
8
5
8X
b
0.50
8X
0.30
PITCH
0.10
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
onsemi,
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and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
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