NB3L14SMNG [ONSEMI]
2.5 V 1:4 LVDS Fanout Buffer;
| 型号： | NB3L14SMNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V 1:4 LVDS Fanout Buffer |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3L14S
2.5 V 1:4 LVDS Fanout
Buffer
The NB3L14S is a differential 1:4 LVDS Clock fanout buffer. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the VT pin. The NB3L14S LVDS signals will be
buffered and replicated to identical LVDS copies of the Input
operating up to 300 MHz. As such, the NB3L14S is ideal for Clock
distribution applications that require low skew.
The NB3L14S is offered in a small 3 mm x 3 mm 16−QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
http://onsemi.com
MARKING
DIAGRAM*
16
1
NB3L
14S
QFN−16
MN SUFFIX
CASE 485G
Features
ALYW G
1
• Maximum Input Clock Frequency; 300 MHz
• Low Output−to−Output Skew; 20 ps
• 450 ps Typical Propagation Delay
• 250 ps Typical Rise and Fall Times
G
A
L
Y
= Assembly Location
= Wafer Lot
= Year
W = Work Week
• Single Power Supply; V = 2.5 $ 5%
CC
G
= Pb−Free Package
• These are Pb−Free Devices
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
V
CC
Q1
Q1
IN
VT
IN
W
50
50
W
Q2
Q2
V
CC
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
November, 2012 − Rev. 0
NB3L14S/D
NB3L14S
Q0
16
Q0
15
V
GND
13
Exposed Pad (EP)
CC
14
Table 1. TRUTH TABLE
Q1
1
2
3
4
12
11
10
9
IN
IN*
0
IN*
1
Q
Q
Q1
Q2
V
T
0
1
1
0
NB3L14S
1
0
NC
IN
x
x
0 (Note 1)
1 (Note 1)
Q2
1. Outputs will be at the known state in this table at initial power up.
The outputs will also be at the known state during normal operation
when inputs are left open.
5
6
7
8
*Defaults high when left open
Q3 Q3
V
V
CC CC
Figure 2. NB3L14S Pinout, 16−pin QFN (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
2
3
4
5
6
Q1
Q2
Q2
Q3
Q3
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
Inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
7
V
V
−
Positive Supply Voltage.
CC
8
−
Positive Supply Voltage.
CC
9
IN
LVDS
No Connect
Input Termination
LVDS
Inverted Differential Input; pin will default HIGH when left open
This is not connected.
10
11
12
13
14
15
NC
V
T
Internal 100 W Center−tapped Termination Pin for IN and IN, leave open for LVDS.
Non−inverted Differential Input; pin will default HIGH when left open.
Negative Supply Voltage.
IN
GND
−
V
CC
−
Positive Supply Voltage.
Q0
Q0
EP
LVDS Output
Non−inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
16
LVDS Output
Inverted IN output. Typically loaded with 100 W receiver termination resistor across
differential pair.
−
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and is required to be
electrically and thermally connected to GND on the PC board.
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2
NB3L14S
Table 3. ATTRIBUTES
Characteristics
Value
Level 1
Moisture Sensitivity (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
200 kW
Input Pull−up Resistors to V on Inputs
CC
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 200 V
Transistor Count
440
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Positive Input
Condition 1
GND = 0 V
Condition 2
Rating
4.6
Unit
V
V
CC
V
IN
GND = 0 V
V
IN
≤ V
4.6
V
CC
I
IN
Input Current Through R (50 W Resistor)
Static
Surge
35
70
mA
mA
T
I
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−GND (Q or Q to GND)
mA
OSC
Q or Q
Q to Q to GND
Continuous
Continuous
12
24
T
Operating Temperature Range
QFN−16
−40 to +85
°C
°C
A
T
stg
Storage Temperature Range
−65 to +150
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
q
JA
Thermal Resistance (Junction−to−Case)
1S2P (Note 3)
QFN−16
4.0
°C/W
°C
q
JC
T
sol
Wave Solder
Pb−Free
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB3L14S
Table 5. DC CHARACTERISTICS V = 2.375 V to 2.625 V, GND = 0 V, T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Note 4)
45
65
mA
CC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 4, 8, and 9) (Note 5)
V
V
V
V
Differential Input HIGH Voltage
1150
GND
75
1800
mV
mV
mV
mV
W
IHD
ILD
CMR
ID
Differential Input LOW Voltage
V
− 150
IHD
Input Common Mode Range (Differential Configuration) (Note 6)
1725
1800
60
Differential Input Voltage (V
− V )
ILD
150
40
IHD
R
Internal Input Termination Resistor
LVDS OUTPUTS (Note 7)
Differential Output Voltage (Single−Ended Measurement)
50
TIN
V
OD
250
0
350
1
450
25
mV
mV
mV
mV
mV
mV
DV
Change in Magnitude of V for Complementary Output States (Note 8)
OD
OD
V
OS
Offset Voltage (Figure 7)
1125
0
1250
1
1375
25
DV
Change in Magnitude of V for Complementary Output States (Note 8)
OS
OS
V
OH
V
OL
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 10)
1425
1075
1600
900
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input pins, IN = 300 mV, IN = 1 V. Output pins loaded with R = 100 W across the outputs.
L
5. V , V
V
and V
parameters must be complied with simultaneously.
IHD ILD, ID
CMR
6. V
min varies 1:1 with GND, V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
CMR
input signal.
CMR
CC
CMR
7. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 6.
8. Parameter guaranteed by design verification not tested in production.
9. V max = V max + ½ V max.
OH
OS
OS
OD
OD
10.V max = V min − ½ V max.
OL
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4
NB3L14S
Table 6. AC CHARACTERISTICS (V = 2.375 V to 2.625 V, GND = 0 V)
CC
−40°C to +85°C
Min
300
250
300
Typ
Max
Symbol
Characteristic
Maximum Input Clock Frequency
Output Voltage Amplitude (@ V
Unit
MHz
mV
f
inMax
V
)
f ≤ 300 MHz
in
350
450
450
600
OUTPP
INPPmin
t
t
,
Differential Input to Differential Output, IN to Q
Propagation Delay @ 50 MHz
ps
PLH
PHL
t
Within Device Output−to−Output Skew (Note 12)
Device−to−Device Skew (Note 12)
5
20
ps
mV
ps
SKEW
30
200
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 11)
150
1800
INPP
t
r
t
f
Output Rise/Fall Times @ 50 MHz
(20% − 80%)
Q, Q
250
350
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input voltage swing is a single−ended measurement operating in differential mode.
12.Skew is measured between outputs under identical transition @ 50 MHz.
400
350
300
250
200
150
100
50
0
0
100
200
300
400
INPUT CLOCK FREQUENCY (MHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
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5
NB3L14S
V
CC
= 3.3 V or 2.5 V
V
CC
= 2.5 V
NB3L14S
IN
Z = 50 W
o
50 W
LVDS
Driver
V = OPEN
T
50 W
Z = 50 W
o
IN
GND
GND
Figure 4. LVDS Interface
IN
V
INPP
= V (IN) − V (IN)
IH IL
IN
Q
V
= V (Q) − V (Q)
OH OL
OUTPP
Q
t
PHL
t
PLH
Figure 5. AC Reference Measurement
Z = 50 W
HI Z Probe
HI Z Probe
Q
D
D
o
LVDS
Driver
100 W
Z = 50 W
Oscilloscope
Device
Q
o
Figure 6. Typical LVDS Termination for Output Driver and Device Evaluation
Q
Q
V
N
N
OH
IN
V
OS
V
OD
V
OL
IN
Figure 7. LVDS Output
Figure 8. Differential Inputs Driven Differentially
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6
NB3L14S
V
CC
V
IHD(MAX)
V
CMRmax
V
ILD(MAX)
V
IHD
= V
V
CMR
V
ID
− V
IHD ILD
V
ILD
V
V
IHD(MIN)
V
CMRmin
ILD(MIN)
GND
Figure 9. VCMR Diagram
Figure 10. Tape and Reel Pin 1 Quadrant Orientation
ORDERING INFORMATION
Device
†
Package
Shipping
NB3L14SMNG
QFN−16, 3 X 3 mm
(Pb−Free)
123 Units / Rail
NB3L14SMNTXG
QFN−16, 3 X 3 mm
3000 / Tape & Reel
(Pin 1 Orientation in Quadrant B, Figure 10)
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NB3L14S
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G
ISSUE F
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
NOM MAX
A
0.90
0.03
1.00
0.05
2X
A3
0.10
C
EXPOSED Cu
MOLD CMPD
A3
b
D
0.20 REF
0.24
3.00 BSC
1.75
0.18
0.30
1.85
1.85
2X
0.10
C
TOP VIEW
D2 1.65
E
3.00 BSC
1.75
0.50 BSC
0.18 TYP
0.40
DETAIL B
A1
(A3)
E2 1.65
e
K
L
0.05
0.05
C
DETAIL B
ALTERNATE
A
C
0.30
0.50
0.15
CONSTRUCTIONS
L1 0.00
0.08
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
16X
0.10
C
A
B
0.58
DETAIL A
PACKAGE
OUTLINE
D2
16X
L
8
1
4
1
9
2X
2X
E2
1.84
3.30
16X
K
16X
0.30
16
16X b
e
e/2
0.50
0.10
0.05
C
C
A B
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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NB3L14S/D
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