NB3L202K_18 [ONSEMI]
Differential 1:2 HCSL Fanout Buffer;
| 型号： | NB3L202K_18 |
| 厂家： | 
ONSEMI |
| 描述： | Differential 1:2 HCSL Fanout Buffer |
| 文件： | 总14页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
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MARKING
DIAGRAM
1
QFN16
NB3L
202K
ALYWG
G
3x3
CASE 485FM
1
NB3L202K = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
• Maximum Input Clock Frequency > 350 MHz
• 2.5 V 5% / 3.3 V 10% Supply Voltage Operation
• 2 HCSL Outputs
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
• DB200H Compliant
• PCIe Gen 3, Gen 4 Compliant
• Individual OE Control Pin for Each Output
• 100 ps Max Output−to−Output Skew Performance
• 1 ns Typical Propagation Delay
• 500 ps Typical Rise and Fall Times
• 80 fs Maximum Additive RMS Phase Jitter
• −40°C to +85°C Ambient Operating Temperature
• QFN 16−pin Package, 3 mm x 3 mm
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• PCI Express
• FBDIMM
• Mobile Computing
• Networking
• Gigabit Ethernet
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
January, 2018 − Rev. 4
NB3L202K/D
NB3L202K
Figure 1. Simplified Block Diagram
Figure 2. 16−Pin QFN Pinout
(Top View)
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2
NB3L202K
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
GND
I/O
Description
1
2
Power
I, DIF
I, DIF
Power
Power
O, DIF
O, DIF
Power
Power
I
Ground
CLK_IN
CLK_IN#
VDD
Differential True input
Differential Complementary input
Core power supply
3
4
5
GND_O
DIF_1#
DIF_1
Ground for outputs
6
0.7 V Differential Complementary Output
0.7 V Differential True Output
7
8
VDD_O
GND
Power supply for outputs
9
Ground
10
IREF
A precision resistor is attached to this pin to set the differential output current.
Use R
Use R
= 475 W, 1% for 100 W trace, with 50 W termination.
= 412 W, 1% for 85 W trace, with 43 W termination.
REF
REF
11
12
OE0#
OE1#
I, SE
I, SE
LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs,
1 disables outputs. Internal pull down.
LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs,
1 disables outputs. Internal pull down.
13
14
15
16
EP
VDD_O
DIF_0
Power
O, DIF
O, DIF
Power
Power supply for outputs
0.7 V Differential True Output
0.7 V Differential Complementary Output
Ground for outputs
DIF_0#
GND_O
Exposed
Pad
Thermal
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electri-
cally and thermally connected to GND on the PC board.
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3
NB3L202K
Table 2. ATTRIBUTES
Characteristics
Value
> 2000 V
ESD Protection
Human Body Model
RPD − Pull−down Resistor
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
50 kW
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
1344
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−
Max
Unit
V
V
DD
Core Supply Voltage
4.6
V
DD_O
I/O Supply Voltage
−
4.6
V
V
Input High Voltage (Note 2)
Input Low Voltage
−
4.6
−
V
IH
V
−0.5
−
V
IL
I
Maximum Output Current
Operating Temperature Range
Storage Temperature Range
24
mA
°C
°C
°C/W
OUT
T
−40 to +85
−65 to +150
A
T
stg
q
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
42
35
JA
q
Thermal Resistance (Junction−to−Case) (Note 3)
Wave Solder
4
°C/W
°C
JC
T
sol
265
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum V is not to exceed maximum V
.
IH
DD
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB3L202K
Table 4. DC CHARACTERISTICS V = V
= 3.3 V 10% or 2.5 V 5%, T = −40°C to 85°C
DD
DD_O
A
Symbol
Characteristics
Min
Typ
Max
Unit
POWER SUPPLY CURRENT
V
Core Power Supply Voltage
V
V
= 3.3 V 10%
2.970
2.375
3.3
2.5
3.630
2.625
V
V
DD
DD
= 2.5 V 5%
DD
V
DD_O
Output Power Supply Voltage
V
= 3.3 V 10%
= 2.5 V 5%
2.970
2.375
3.3
2.5
3.630
2.625
DD_O
V
DD_O
I
+ I
DD_O
Total Power Supply Current (all outputs active @ 350 MHz, R = 412 W,
REF
80
110
mA
DD
R = 43 W)
L
I
Standby Current, all OE pins de−asserted with inputs @ 350 MHz
Incremental output current for additional output; One OE Enabled
50
15
65
65
23
88
mA
mA
mA
stdby
l
incr
I
+ l
Standby Current plus incremental current for one additional differential output;
One OE Enabled @ 350 MHz
stdby
incr
HCSL OUTPUTS (Notes 4, 5)
V
Output HIGH Voltage
Output LOW Voltage
660
850
mV
mV
mV
OH
V
−150
OL
V
OUT
Output Swing (Single−Ended)
Output Swing (Differential)
400
800
750
1500
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 4 and 6)
V
CLK_IN/CLK_IN# Single-ended Input HIGH Voltage
CLK_IN/CLK_IN# Single-ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 7)
Single-ended Input Voltage (VIH − VIL)
0.5
GND
0.25
0.5
V
V
V
V
V
IH
DD
V
V
− 0.3
IL
th
IH
V
V
− 1.0
DD
V
ISE
VDD
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 8) (Figures 5 and 7)
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
0.5
0
V
− 0.85
DD
V
V
IHD
V
V
IHD
−
ILD
0.25
V
Differential Input Voltage (V
− V )
ILD
0.25
0.5
−5
1.3
V
V
ID
IHD
V
Input Common Mode Range (Differential Configuration) (Note 9) (Figure 8)
Input Leakage Current 0 < V < V (Note 10)
V
− 0.85
DD
IHCMR
I
IL
5
mA
IN
DD
LVTTL / LVCMOS INPUTS (OEx#)
V
Input HIGH Voltage
Input LOW Voltage
2.0
−0.3
−10
V
DD
+ 0.3
V
V
IH
V
0.8
+10
100
IL
I
IL
Input LOW Current (V = GND)
mA
mA
IN
I
IH
Input HIGH Current (V = V
)
IN
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Test configuration is R = 33.2 W, R = 49.9, C = 2 pF, R = 475 W.
S
L
L
REF
5. Measurement taken from Single−Ended waveform unless specified otherwise.
6. V , V and V parameters must be complied with simultaneously.
V
IL, th
IH
ISE
7. V is applied to the complementary input when operating in single−ended mode.
th
8. V , V
V
and V
parameters must be complied with simultaneously.
IHD
ILD, ID
CMR
9. The common mode voltage is defined as V
.
IH
10.Does not include inputs with pulldown resistors.
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5
NB3L202K
Table 5. AC TIMING CHARACTERISTICS V = V
= 3.3 V 10% or 2.5 V 5%, T = −40°C to 85°C (Note 15)
DD
DD_O
A
Symbol
Characteristics
Min
350
175
0.5
Typ
Max
Unit
MHz
ps
F
max
Maximum Input Frequency
T /T
rise fall
Rise Time / Fall Time (Notes 13, 17 and 33) (Figure 13)
Output Slew Rate (Notes 13 and 17)
500
700
2.0
Output Slew Rate
DT /DT
V/ns
ps
Rise/Fall Time Variation (Notes 17 and 26)
125
20%
850
+150
rise
fall
Slew Rate Matching (Notes 18, 27 and 28)
V
high
Voltage High (Notes 17, and 20) (Figure 14)
Voltage Low (Notes 17, and 21) (Figure 14)
(Note 29 and 32)
660
−150
0.35
250
700
0
mV
mV
V
low
Input Slew Rate
absolute
V/ns
mV
V
Absolute Crossing Point Voltages (Notes 12, 17 and 24)
Relative Crossing Point Voltages can be calculated (Notes 16, 17
and 24) (Figure 16)
550
cross
Total DV
Total Variation of Vcross Over All Edges (Notes 17 and 25)
(Note 18) (Figure 15)
140
55
mV
%
cross
Duty Cycle
45
V
Maximum Voltage (Overshoot) (Notes 17 and 22) (Figure 14)
Maximum Voltage (Undershoot) (Notes 17 and 23) (Figure 14)
Ringback Voltage (Note 17) (Figure 14)
V
+ 0.3
V
ovs
high
V
uds
V
− 0.3
V
low
V
0.2
4
N/A
V
rb
T
oe_lat
OE Latency (Note 11)
6
12
1.4
20
80
Cycles
ns
t
pd
Input−to−Output Delay CLK_IN, DIF_[1:0] (Note 31)
0.6
0
1.0
5.0
46
t
Output−to−Output Skew across 2 outputs DIF_[1:0] (Notes 30 and 31)
ps
SKEW
t
Additive RMS Phase Jitter f = 156.25 MHz, 12 kHz − 20 MHz Inte-
carrier
fs
f
JITTER
grated Range
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Time from deassertion until outputs are >200 mV.
12.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
13.Measured from V = 0.175 V to V = 0.525 V. Only valid for Rising Clock and Falling Clock#.
OL
OH
14.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing
15.Test configuration is R = 33.2 W, R = 49.9, C = 2 pF, R = 475 W.
S
P
L
REF
16.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (V
− 0.700). Vcross(rel) Max = 0.550 − 0.5
high avg
(0.700 – V
), (see Figure 16 for further clarification).
high avg
17.Measurement taken from Single Ended waveform.
18.Measurement taken from differential waveform.
19.Unless otherwise noted, all specifications in this table apply to all frequencies.
20.V
21.V
is defined as the statistical average High value as obtained by using the Oscilloscope V
Math function.
high
high
is defined as the statistical average Low value as obtained by using the Oscilloscope V Math function.
low
low
22.Overshoot is defined as the absolute value of the maximum voltage.
23.Undershoot is defined as the absolute value of the minimum voltage.
24.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
25.DVcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK#. This is the maximum allowed vari-
ance in Vcross for any particular system.
26.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
27.Matching applies to rising edge rate for clock and falling edge rate for Clock#. It is measured using a 75 mV window centered on the average
crosspoint where clock rising meets Clock# falling. The median crosspoint is used to calculate the voltage threshold the oscilloscope is to
use for the edge rate calculations.
28.Slew Rate matching is derived using the following, 2 * (T
– T ) / (T
+ T ).
rise fall
rise
fall
29.Input slew rate is based on single ended measurement. This is the minimum input slew rate at which the NB3L202K devices are guaranteed
to meet all performance specifications.
30.Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
31.Measured from differential cross−point to differential cross−point with scope averaging on to find mean value.
32.The differential input clock is expected to be sourced from a high performance clock oscillator.
33.Measured at 3.3 V 10% with typical HCSL input levels.
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NB3L202K
Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 45.7 fs.
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is similar or greater than the device under test output,
the source noise will dominate the additive phase jitter
calculation and lead to an artificially low result for the
additive phase noise measurement within the integration
range.
The additive RMS phase jitter performance of the fanout
buffer is highly dependent on the phase noise of the input
source.
2
2
Additive RMS phase jitter + ǸRMS phase jitter of output * RMS phase jitter of input
2
2
45.7 fs + Ǹ73.7 fs * 57.8 fs
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NB3L202K
Table 6. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
(V = V
= 3.3 V 10% or 2.5 V 5%, T = −40°C to 85°C)
A
DD
DD_O
Symbol
Parameter
Conditions (Notes 34 and 39)
Min
Typ
Max
Unit
t
PCIe Gen 1 (Notes 35 and 36)
10
ps (p−p)
jphPCIeG1
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 35 and 38)
ps
(rms)
0.3
0.7
t
jphPCIeG2
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Notes 35 and 38)
ps
(rms)
PCIe Gen 3
(PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz)
(Notes 35 and 38)
t
t
0.07
0.07
0.4
0.4
0.3
ps
ps
jPCIeG3
Additive Phase Jitter
PCIe Gen 4
(PLL BW= 2−4 MHz or 2−5 MHz, CDR = 10 MHz)
(Notes 35 and 38)
jPCIeG4
QPI & SMI
(100.00 MHz or 133.33 MHz, 4.8 Gb/s,
6.4 Gb/s 12UI) (Notes 37 and 38)
ps
(rms)
QPI & SMI
ps
(rms)
t
jphQPI_SMI
0.1
0.1
(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 37 and 38)
QPI & SMI
ps
(rms)
(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 37 and 38)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
34.Applies to all outputs.
35.See http://www.pcisig.com for complete specs
36.Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
37.Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
38.For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) = (total jitter) - (input jitter)
2
2
2
39.Guaranteed by design and characterization, not tested in production
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NB3L202K
CLK_IN
V
IH
V
CLK_IN
th
IL
V
CLK_IN#
CLK_IN#
V
th
Figure 4. Differential Input Driven
Single−Ended
Figure 5. Differential Inputs
Driven Differentially
V
DD
thmax
V
V
IHmax
V
ILmax
V
ID
= |V
− V
IHD(IN) ILD(IN)|
V
IH
V
th
V
IL
CLK_IN#
CLK_IN
V
th
V
IHD
V
ILD
V
V
IHmin
V
thmin
ILmin
GND
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
V
DD
V
V
IHDmax
ILDmax
IHDtyp
V
IHCMR MAX
CLK_IN#
V
INPP
= V (CLK_IN) −
IH
V (CLK_IN)
IL
CLK_IN#
CLK_IN
CLK_IN
DIF_n#
V
IHCMR
V
V
ID
= V
− V
IHD ILD
V
V
= V (DIF_n) −
OH
(DIF_n)
V
ILDtyp
OUTPP
OL
DIF_n
V
V
IHDmin
V
IHCMR MIN
t
PHL
ILDmin
t
PLH
GND
Figure 8. VIHCMR Diagram
Figure 9. AC Reference Measurement
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NB3L202K
Z = 50 W
R
R
0
S1
DIF_n
Receiver
HCSL
Driver
Z = 50 W
0
S2
DIF_n#
REF
R
L1
50 W
R
50 W
C
2 pF
C
2 pF
L2
L1
L2
I
R
REF
A. Connect 475 W resistor R
from I
pin to GND.
REF
REF
B. R , R : 33 W for Test and Evaluation. Select to Minimizing Ringing.
S1
S2
C. C , C : Receiver Input Simulation (for test only not added to application circuit.
L1
L2
D. R , R Termination and Load Resistors Located at Received Inputs.
L1
L2
Figure 10. Typical Termination Configuration for Output Driver and Device Evaluation
3.3 V
I
REF
I
OUT
C1
V
Mirror
M
Iref
M
Mir
2R
R
M
OUTB
M
OUT
M
Dum
OUT
OUT
~1.1 V
Out_predrv
R
REF
Figure 11. HCSL Simplified Output Structure
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NB3L202K
NB3L202K
Z = 50 W
Qx
Qx
o
LVDS
Device
HCSL
Device
100 W
Z = 50 W
100 W
o
R = 150 W
L
R = 150 W
L
IREF
R
REF
GND
Figure 12. HCSL Interface Termination to LVDS
MEASUREMENT POINTS FOR DIFFERENTIAL
TRise (Clock)
V
OH
= 0.525 V
V
Cross
V
OL
= 0.175 V
TFall (Clock#)
Figure 13. Single−Ended Measurement Points for Trise, Tfall
V
ovs
V
high
V
rb
V
rb
V
low
V
uds
Figure 14. Single−Ended Measurement Points for Vovs, Vuds, Vrb
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NB3L202K
TPeriod
High Duty Cycle%
Low Duty Cycle%
Skew measurement point
0.000 V
Figure 15. Differential (CLOCK – CLOCK#) Measurement Points (Tperiod, Duty Cycle)
V
Max
cross(rel)
550
500
450
400
350
300
250
200
ForVhigh> 700mV
Use Equ. 2
ForVhigh < 700mV
Use Equ. 1
Crossing Point (mV)
V
Min
cross(rel)
625
650
675
700
725
750
775
800
825
850
V
high
Average (mV)
Equ 1: V
Equ 2: V
Max = 0.550 − 0.5(0.7 − V
)
cross(rel)
cross(rel)
high avg
− 0.7)
Min = 0.250 + 0.5(V
high avg
Figure 16. Vcross Range Clarification (Note 40)
40.The picture above illustrates the effect of V above and below 700 mV on the V range. The purpose of this is to prevent a 250 mV
high
cross
with a 660 mV V
V
cross
with an 850 mV V
. In addition, this prevents the case of a 550 mV V
. The actual specification for V
high cross
high
cross
is dependent upon the measured amplitude of V
.
high
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NB3L202K
Signal and Feature Operation
Table 7. OE# FUNCTIONALITY (Notes 41, 42 and 43)
CLK_IN / CLK_IN#
Running
OE# (Pin)
DIF
DIF #
Low
Notes
1
0
x
Low
Running
x
41
Running
Running
x
Not Running
41.The outputs are tri−stated, but the termination networks pull them low
42.OE# pins are asynchronous asserted−low signals.
43.Each OE# pin controls two pair of DIF outputs.
OE# Assertion (Transition from ‘1’ to ‘0’)
OE# De−Assertion (Transition from ‘0’ to ‘1’)
The maximum latency from the de−assertion to tristated
(low due to termination pull down) outputs is 12 DIF clock
periods.
All differential outputs that were tri−stated (low due to
termination pull down) will resume normal operation in a
glitch free manner. The latency from the assertion to active
outputs is 4 − 12 DIF clock periods.
Note: Input clock must remain running for a minimum of
12 clock cycles.
Table 8. NB3L202K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS
Board Target Trace/Term Z
Reference R, Iref = VDD/(3*R
)
Output Current
V
OH
@ Z
Rs
Rp
REF
100 W Differential
R
= 475 W 1%,
I
= 6 * I
0.7 V @ 50
33 W
50 W
REF
OH
REF
50 W Single−Ended
I
= 2.32 mA
5%
5%
REF
85 W Differential
R
= 412 W, 1%,
I
= 6 * I
0.7V @ 43.2
27 W
43 W
REF
OH
REF
43 W Single−Ended
I
= 2.67 mA
5%
5%
REF
ORDERING INFORMATION
Device
†
Package
Shipping
NB3L202KMNG
QFN16
(Pb−Free)
123 Units / Rail
NB3L202KMNTXG
QFN16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3L202K
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485FM
ISSUE A
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. OUTLINE MEETS JEDEC DIMENSIONS PER
MO−220, VARIATION VEED−6.
PIN 1
LOCATION
DETAIL A
E
MILLIMETERS
DIM MIN
MAX
1.00
0.05
A3
0.15
C
A
A1
A3
b
0.80
0.00
0.20 REF
0.15
C
TOP VIEW
0.18
0.30
D
3.00 BSC
D2
E
E2
e
K
L
1.25
3.00 BSC
1.25
0.50 BSC
0.20
0.30
1.55
A1
DETAIL B
(A3)
0.10
C
C
DETAIL B
1.55
A
−−−
0.50
0.08
A1
SIDE VIEW
SEATING
PLANE
NOTE 4
RECOMMENDED
SOLDERING FOOTPRINT*
C
D2
3.30
DETAIL A
16X
0.65
16X
L
PACKAGE
OUTLINE
5
1.55
8
9
1
4
E2
16X
K
1.55 3.30
1
12
16
13
16X
0.30
16X b
e
0.10
0.05
C
C
A B
e/2
0.50
NOTE 3
PITCH
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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