NB3L553DR2G [ONSEMI]
2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer; 2.5 V / 3.3 V / 5.0 V 1 ： 4时钟扇出缓冲器
| 型号： | NB3L553DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V / 3.3 V / 5.0 V 1:4 Clock Fanout Buffer |
| 文件： | 总6页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3L553
2.5 V / 3.3 V / 5.0 V
1:4 Clock Fanout Buffer
Description
The NB3L553 is a low skew 1−to 4 clock fanout buffer, designed for
clock distribution in mind. The NB3L553 specifically guarantees low
output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
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MARKING DIAGRAMS*
The output enable (OE) pin tri−states the outputs when low.
8
8
Features
1
3L553
ALYW
G
• Input/Output Clock Frequency up to 200 MHz
• Low Skew Outputs (35 ps)
SOIC−8
D SUFFIX
CASE 751
1
• Output Enable Mode Three−States Outputs
3N553 = Specific Device Code
• Operating Range: V = 2.375 V to 5.25 V
DD
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Ideal for Networking Clocks
• Packaged in 8−pin SOIC
• Industrial Temperature Range
• These are Pb−Free Devices
1
Q1
DFN8
MN SUFFIX
CASE 506AA
1
4
Q2
CLK
XX = Specific Device Code
= Date Code
Q3
M
(Note: Microdot may be in either location)
Q4
*For additional marking information, refer to
Application Note AND8002/D.
PINOUT
OE
1
2
3
4
8
7
6
5
Figure 1. Block Diagram
OE
Q3
Q2
V
DD
Q0
Q1
GND
I
CLK
ORDERING INFORMATION
†
Device
Package
Shipping
NB3L553DG
SOIC−8
98 Units/Rail
(Pb−Free)
NB3L553DR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
1000/Tape & Reel
NB3L553MNR4G* DFN−8
(Pb−Free)
*Contact Sales Representative
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 0
NB3L553/D
NB3L553
OE
0
Function
Disable
Enable
1
Table 1. OE, Output Enable Function
PIN DESCRIPTION
Pin #
Name
Type
Description
Positive supply voltage (2.375 V to 5.25 V)
1
2
3
4
5
6
7
8
V
Power
DD
Q0
Q1
(LV)CMOS/(LV)TTL Output Clock Output 0
(LV)CMOS/(LV)TTL Output Clock Output 1
GND
ICLK
Q2
Power
Negative supply voltage; Connect to ground, 0 V
Clock Input. 5.0 V tolerant
(LV)CMOS/(LV)TTL Input
(LV)CMOS/(LV)TTL Output Clock Output 2
(LV)CMOS/(LV)TTL Output Clock Output 3
Q3
OE
(LV)CMOS/(LV)TTL Input
Output Enable for the clock outputs. Outputs are enabled when HIGH: connect to
for normal operation; OE pin has internal pull−up resistor. Three−states out-
V
DD
puts when LOW.
MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
6.0
Units
V
V
Positive Power Supply
GND = 0 V
−
DD
V
Input Voltage
−
−
−
−
GND –0.5 ≤ V ≤ V + 0.5
V
I
I
DD
T
A
Operating Temperature Range, Industrial
Storage Temperature Range
−
−
≥ −40 to ≤ +85
_C
_C
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient)
0 LFPM
SOIC−8
190
130
_C/W
JA
500 LFPM
_C/W
q
Thermal Resistance (Junction−to−Case)
(Note 1)
SOIC−8
41 to 44
_C/W
JC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
ATTRIBUTES
Characteristic
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> TBD kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Level 1
UL−94 code V−0 @ 0.125 in
531 Devices
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
NB3L553
DC CHARACTERISTICS (V = 2.375 V to 2.625 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Power Supply Current @ 135 MHz, No Load
Output HIGH Voltage – I = −16 mA
Min
−
Typ
25
−
Max
TBD
−
Unit
mA
V
I
DD
V
2.0
−
OH
OH
V
Output LOW Voltage – I = 16 mA
−
0.4
3.8
V
OL
OL
V
I
Input HIGH Voltage, I
(V ÷2)+0.5
DD
−
V
IH, CLK
CLK
V
I
Input LOW Voltage, I
−
1.8
−
−
(V ÷2)−0.5
V
IL, CLK
CLK
DD
V
OE
OE
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
−
V
V
IH,
DD
V
−
0.7
−
V
IL,
ZO
−
20
5.0
28
W
CIN
IOS
Input Capacitance, I
, OE
−
−
pF
mA
CLK
Short Circuit Current
−
−
DC CHARACTERISTICS (V = 3.15 V to 3.45 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Power Supply Current @ 135 MHz, No Load
Output HIGH Voltage – I = −25 mA
Min
−
Typ
35
−
Max
TBD
−
Unit
mA
V
I
DD
V
2.4
−
OH
OH
V
Output LOW Voltage – I = 25 mA
−
0.4
−
V
OL
OL
V
Output HIGH Voltage – I
Input HIGH Voltage, I
= −12 mA (CMOS level)
V − 0.4
DD
−
V
OH
OH
V
I
(V ÷2)+0.7
DD
−
3.8
V
IH, CLK
CLK
CLK
V
I
Input LOW Voltage, I
−
2.0
0
−
(V ÷2)−0.7
DD
V
IL, CLK
V
OE
OE
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Capacitance, OE
Short Circuit Current
−
V
V
IH,
DD
V
−
0.8
−
V
IL,
ZO
−
20
5.0
50
W
CIN
IOS
−
−
pF
mA
−
−
DC CHARACTERISTICS (V = 4.75 V to 5.25 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Power Supply Current @ 135 MHz, − No Load
Output HIGH Voltage – I = −35 mA
Min
−
Typ
45
−
Max
TBD
−
Unit
mA
V
I
DD
V
2.4
−
OH
OH
V
Output LOW Voltage – I = 35 mA
−
0.4
−
V
OL
OL
V
Output HIGH Voltage – I
Input HIGH Voltage, I
= −12 mA (CMOS level)
V − 0.4
DD
−
V
OH
OH
V
I
(V ÷2) + 1
DD
−
5.5
V
IH, CLK
CLK
CLK
V
I
Input LOW Voltage, I
−
2.0
−
−
(V ÷2) − 1
DD
V
IL, CLK
V
OE
OE
Input HIGH Voltage, OE
Input LOW Voltage, OE
Nominal Output Impedance
Input Capacitance, OE
Short Circuit Current
−
V
V
IH,
DD
V
−
0.8
−
V
IL,
ZO
−
20
5.0
80
W
CIN
IOS
−
−
pF
mA
−
−
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3
NB3L553
AC CHARACTERISTICS; VDD = 2.5 V + 5% (V = 2.375 V to 2.625 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Min
Typ
−
Max
200
1.5
5.0
−
Unit
MHz
ns
f
Input Frequency
−
−
in
t /t
r
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Qn (Note 4)
Output−to−output skew; (Note 5)
1.0
3.0
35
−
f
t
2.2
−
ns
pd
t
t
ps
skew
skew
Device−to−device skew, (Note 5)
−
500
ps
AC CHARACTERISTICS; VDD = 3.3 V + 5% (V = 3.15 V to 3.45 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Min
−
Typ
−
Max
200
1.0
4.0
50
Unit
MHz
ns
f
Input Frequency
in
t /t
r
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Qn (Note 4)
Output−to−output skew; (Note 5)
−
0.6
2.4
35
−
f
t
2.0
−
ns
pd
t
t
ps
skew
skew
Device−to−device skew, (Note 5)
−
500
ps
AC CHARACTERISTICS; VDD = 5.0 V + 5% (V = 4.75 V to 5.25 V, GND = 0 V, T = −40°C to +85°C) (Note 3)
DD
A
Symbol
Characteristic
Min
−
Typ
−
Max
200
0.7
4.0
−
Unit
MHz
ns
f
Input Frequency
in
t /t
r
Output rise and fall times; 0.8 V to 2.0 V
Propagation Delay, CLK to Qn (Note 4)
Output−to−output skew; (Note 5)
−
0.3
2.5
35
−
f
t
1.8
−
ns
pd
t
t
ps
skew
skew
Device−to−device skew, (Note 5)
−
500
ps
3. Outputs loaded with external R = 33−W series resistor and C = 15 pF to GND for proper operation. Duty cycle out = duty in. A 0.01 mF
L
L
decoupling capacitor should be connected between V and GND.
DD
4. Measured with rail−to−rail input clock
5. Measured on rising edges at V ÷ 2 between any two outputs with equal loading.
DD
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4
NB3L553
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
NB3L553
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
2.00 BSC
0.10
C
D2
E
E2
e
K
L
1.10
2.00 BSC
0.70
0.50 BSC
0.20
0.25
1.30
2 X
0.90
0.10
C
TOP VIEW
−−−
0.35
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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NB3L553/D
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