NB3L8504S_16 [ONSEMI]
1:4 Differential Input to LVDS Fanout Buffer / Translator;
| 型号： | NB3L8504S_16 |
| 厂家： | 
ONSEMI |
| 描述： | 1:4 Differential Input to LVDS Fanout Buffer / Translator |
| 文件： | 总11页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3L8504S
2.5 V / 3.3 V 1:4 Differential
Input to LVDS Fanout Buffer
/ Translator
Description
www.onsemi.com
MARKING
The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator
with OE control for each differential output. The differential inputs
which can be driven by either a differential or single−ended input, can
accept various logic level standards such as LVPECL, LVDS, HSTL,
HCSL and SSTL. These signals are then translated to four identical
LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is
ideal for Clock distribution applications that require low skew.
The NB3L8504S is offered in the TSSOP−16 package.
DIAGRAM*
16
TSSOP−16
DT SUFFIX
CASE 948F
NB3L
8504
ALYWG
G
16
1
Features
1
• Four Differential LVDS Outputs
A
L
Y
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Each Differential Output has OE Control
• 700 MHz Maximum Output Frequency
• 660 ps Max Output Rise and Fall Times, LVCMOS
• Translates Differential Input to LVDS Levels
• Additive Phase Jitter RMS: < 100 fs Typical
• 50 ps Maximum Output Skew
W
G
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
• 350 ps Maximum Part−to−part Skew
• 1.3 ns Maximum Propagation Delay
• Operating Range: V = 2.5 V 5% or 3.3 V 10%
CC
• −40°C to +85°C Ambient Operating Temperature
• 16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm
• These are Pb−Free Devices
Applications
• Telecom
• Ethernet
• Networking
• SONET
CLK
CLK
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April, 2016 − Rev. 2
NB3L8504S/D
NB3L8504S
Table 1. PIN DESCRIPTIONS AND CHARACTERISTICS
Pin
Name
I/O
Description
1
OE0
LVTTL/LVCMOS Input
Output Enable pin for Q0, Q0 outputs. Defaults High when left open; internal pull−up
resistor.
2
3
OE1
OE2
LVTTL/LVCMOS Input
LVTTL/LVCMOS Input
Output Enable pin for Q1, Q1 outputs. Defaults High when left open; internal pull−up
resistor.
Output Enable pin for Q2, Q2 outputs. Defaults High when left open; internal pull−up
resistor.
4
5
6
VDD
GND
CLK
Power
Power
3.3 V / 2.5 V Positive Supply Voltage.
3.3 V / 2.5 V Negative Supply Voltage.
Multi−Level Input
Non−inverting differential Clock input. Defaults Low when left open; internal pull−down
resistor.
7
8
CLK
OE3
Multi−Level Input
Inverting differential Clock input. Defaults to VDD/2 when left open; internal pull−up and
pull−down resistors.
LVTTL/LVCMOS Input
Output Enable pin for Q3, Q3 outputs. Defaults High when left open; internal pull−up
resistor.
9
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVDS Output
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
Inverting differential Clock output.
Non−inverting differential Clock output.
10
11
12
13
14
15
16
1. All VDD and GND pins must be externally connected to a power supply for proper operation.
OE0
OE1
OE2
VDD
GND
CLK
1
2
3
4
5
6
7
8
16 Q0
Q0
15
14 Q1
13 Q1
Q2
Q2
Q3
Q3
12
11
10
9
CLK
OE3
Figure 2. NB3L8504S Pinout, 16−pin TSSOP (Top View)
Table 2. OUTPUT ENABLE FUNCTION TABLE
OE[3:0]
LOW
Outputs – Q[0:3], Q[0:3]
High Impedance
Active
HIGH (Default)
www.onsemi.com
2
NB3L8504S
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
R
R
− Input Pull−up Resistor
− Input Pull−down Resistor
50 kW
50 kW
PU
PD
C
R
− Input Capacitance
− Input Impedance
4 pF
10 kW
IN
IN
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
TSSOP−16
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
371
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition
GND = 0 V
Rating
Unit
V
V
DD
4.6
V
IN
GND = 0 V
−0.5 to V +0.5
V
DD
I
Continuous Current
Surge Current
LVDS Outputs
10
15
mA
mA
out
I
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−GND (Q or Q to GND)
OSC
Q or Q
Q to Q to GND
Continuous
Continuous
12
24
mA
mA
T
Operating Temperature Range
TSSOP−16
−40 to +85
_C
_C
A
T
stg
Storage Temperature Range
−65 to +150
θ
JA
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
TSSOP−16
TSSOP−16
138
108
_C/W
_C/W
_C/W
_C
θ
JC
Thermal Resistance (Junction−to−Case)
Wave Solder (Pb−Free)
(Note 3)
TSSOP−16
33 − 36
265
T
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
www.onsemi.com
3
NB3L8504S
Table 5. DC CHARACTERISTICS V = 2.5 V 5% or 3.3 V 10%; GND = 0 V; T = −40°C to 85°C
DD
A
Symbol
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY / CURRENT (Note 4)
V
DD
Power Supply Voltage
V
DD
V
DD
= 3.3 V
= 2.5 V
2.97
2.375
3.3
2.5
3.63
2.625
V
I
Power Supply Current for V
41
50
mA
DD
DD
LVDS OUTPUTS (Note 5)
Differential Output Voltage (Figure 12) (Notes 6 and 7)
Magnitude Change (Figure 12) (Notes 6 and 7)
V
250
350
450
50
mV
mV
mV
mV
mV
mV
OD
DV
V
OD
OD
V
Offset Voltage (Figure 13) (Notes 6 and 7)
V Magnitude Change (Figure 13) (Notes 6 and 7)
OS
1075
1250
1375
50
OS
DV
OS
V
Output HIGH Voltage
Output LOW Voltage
1425
1075
1600
OH
V
900
OL
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 5 & 6) (Note 11)
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
500
−300
VDD – 850
VIHD – 150
1300
mV
mV
mV
mV
IHD
V
ILD
V
Differential Input Voltage (V
V )
150
ID
IHCMR
IHD − ILD
V
Input Common Mode Voltage Range (Differential Configuration)
(Note 10) (Figure 7)
GND + 0.5
VDD – 850
I
Input HIGH Current, V = V = 3.63 V
CLK, CLK
150
mA
mA
IH
DD
IN
I
Input LOW Current, V = 3.63 V, V = 0 V
CLK
CLK
−5
−150
IL
DD
IN
LVCMOS – OE Control Inputs
V
Input HIGH Voltage
Input LOW Voltage
2.0
VDD + 0.3
V
V
IH
V
−0.3
0.8
5
IL
I
IH
Input HIGH Current, V = V = 3.63 V
mA
mA
DD
IN
I
IL
Input LOW Current, V = 3.63 V, V = 0 V
−150
DD
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input pins open and output pins loaded with R =100 W across differential.
L
5. LVDS outputs require 100 W receiver termination resistor between diff. pair. See Figure 14.
6. VOS max + ½ VOD max. Also see Figures 12 and 13.
7. VOS min − ½ VOD max. Also see Figures 12 and 13.
8. VIH, VIL, Vth, and VISE parameters must be complied with simultaneously.
9. Vth is applied to the complementary input when operating in single−ended mode.
10.V
max varies 1:1 with V , V
min varies 1:1 with GND.
IHCMR
DD
IHCMR
11. V , V
V
and V parameters must be complied with simultaneously.
IHD
ILD, ID
IHCMR
www.onsemi.com
4
NB3L8504S
Table 6. AC CHARACTERISTICS V = 2.5 V 5% or 3.3 V 10%; GND = 0 V; T = −40°C to 85°C (Note 12) (Figure 10)
DD
A
Symbol
Characteristic
Min
Typ
Max
Unit
MHz
mV
f
Input Clock Frequency
V
≥ 250 mV @ V
INPPmax
700
MAX
OUTPP
V
Output Voltage Amplitude (@ V ) f ≤ 700 MHz
INPPmin in
250
0.9
350
OUTPP
(See Figure 3)
tpd
Differential Input to Differential Output Propagation Delay at f
1.3
ns
ps
MAX
@ V = 3.3 V
DD
tjit(f)
Additive Phase Jitter RMS (Figure 4)
Integration Range:12 kHz − 20 MHz
f
= 156.25 MHz
0.07
0.10
0.08
0.105
out
f
= 100 MHz
out
t
Output−to−output Skew (Note 14) (Figure 8)
Part−to−part Skew (Note 14)
50
350
660
55
ps
ps
ps
%
SKEW(o−o)
T
SKEW(pp)
t / t
Output Rise/Fall Times @ 50 MHz, 20% − 80%
180
45
350
50
r
f
t
Output Clock Duty Cycle (Input Duty Cycle = 50%)
DC
V
INPP
Input Voltage Swing
(Differential Configuration) (Note 13)
150
1300
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12.Measured by forcing a 50% duty cycle clock source. All LVDS output loading with an external R = 100 W across Q & Q.
L
13.V
cannot exceed V . Input voltage swing is a single−ended measurement operating in differential mode.
INPP(max)
DD
14.Skew is measured between outputs under identical transition at 50 MHz.
Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Clock Frequency (fin) and Temperature (@ VDD = 2.5 V)
www.onsemi.com
5
NB3L8504S
Figure 4. Additive Phase Jitter
VDD
V
IHCMRmax
V
V
IHDmax
ILDmax
VID = VIHD - VILD
IN
IN
V
V
IHDtyp
ILDtyp
VIHCMR
V
IHCMRmin
V
V
IHDmin
ILDmin
Figure 5. Differential Inputs
Driven Differentially
GND
Figure 7. VIHCMR Diagram
Figure 6. Differential Inputs
Driven Differentially
Figure 8. Output−to−Output Skew
www.onsemi.com
6
NB3L8504S
Figure 9. LVDS Output
Figure 10. AC Reference Measurements
Figure 11. LVDS Output
Figure 12. VOD and DVOD
Figure 13. VOS and DVOS
Z = 50 W
Q
Q
D
o
LVDS
Driver
Device
LVDS
Receiver
Device
100 W
Z = 50 W
o
D
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
www.onsemi.com
7
NB3L8504S
2.05 0.165 V
SCOPE
Qx
Qx
V
DD
Z = 50 W
o
50 W
LVDS
Z = 50 W
o
GND
50 W
−1.25 V
Figure 15. Typical Test Setup and Termination for Evaluation. The VDD = 2.05 V + 0.165 V and GND of −1.25 Split
Supply Allows a Direct Connection to an Oscilloscope 50 W Input Module
V
= +3.3 V
LVPECL
V
= +3.3 V
LVDS
2.5 V
V
DD
= +3.3 V
LVDS
DD
DD
V
= +3.3 V
V
= +3.3 V
DD
DD
R1
127
R3
127
R1
120
R3
120
Q
Q
Q
Q
Z
Z
= 50 W
= 50 W
Z
Z
= 50 W
= 50 W
o
o
o
o
SSTL
R2
83
R4
83
R2
120
R4
120
SSTL to LVDS
LVPECL to LVDS
V
= +3.3 V
LVDS
V
= +3.3 V
LVDS
2.5 V
V
DD
= +3.3 V
LVDS
DD
DD
Q
Q
Q
Z
Z
= 50 W
= 50 W
Z
Z
= 50 W
= 50 W
o
o
o
o
R1
100
HSTL
Q
R2
50
R4
50
LVDS to LVDS
HSTL to LVDS
V
= +3.3 V
CML
V
= +3.3 V
LVDS
2.5 V
V
= +3.3 V
LVDS
DD
DD
DD
V
= +3.3 V
DD
R
33
R1
50
R3
50
S
Q
Q
Q
Q
Z
Z
= 50 W
= 50 W
Z
Z
= 50 W
= 50 W
o
o
o
o
HSTL
R
33
S
R2
50
R4
50
CML to LVDS
HCSL to LVDS
Figure 16. Differential Input Interface from LVPECL, CML, LVDS, HSTL, SSTL or HCSL
www.onsemi.com
8
NB3L8504S
V
DD
R1
1k
CLK
CLK
V
ref
C1
0.1 mF
R2
1k
GND
Figure 17. Differential Input Driven Single−ended
Differential Clock Input to Accept Single−ended Input
as a bypass capacitor. Locate these components close the
Figure 17 shows how the CLK input can be driven by a
device pins. R1 and R2 must be adjusted to position V to
ref
single−ended Clock signal. C1 is connected to the V node
the center of the input swing on CLK.
ref
Table 7. ORDERING INFORMATION
Device
Package
TSSOP−16
Shipping
NB3L8504SDTG
96 Units / Tube
(Pb−Free)
NB3L8504SDTR2G
TSSOP−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
9
NB3L8504S
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
16X KREF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
1.20
−−− 0.047
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
NB3L8504S
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NB3L8504S/D
相关型号：
©2020 ICPDF网 联系我们和版权申明