NB3N2302DR2G [ONSEMI]
Frequency Multiplier;
| 型号： | NB3N2302DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Frequency Multiplier 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3N2302
3.3V / 5V 5MHz to 133MHz
Frequency Multiplier and
Zero Delay Buffer
Description
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MARKING DIAGRAM
The NB3N2302 is a versatile Zero Delay Buffer that operates from
5 MHz to 133 MHz with a 3.3 V or 5 V power supply. It accepts a
reference input and drives a B1 and a B2 clock output. The
NB3N2302 has an on−chip PLL which locks to the input reference
clock presented on the REF_IN pin. The PLL feedback is required to
be driven to the FBIN pin and can be obtained by connecting either the
OUT1 or OUT2 pin to the FBIN pin.
8
8
1
3N2302
ALYWG
G
SOIC−8
D SUFFIX
CASE 751
1
The Function Select inputs control the various multiplier output
frequency combinations as shown in Table 1.
2302
= Specific Device Code
= Assembly Location
= Wafer Lot
A
L
Features
Y
W
G
= Year
= Work Week
= Pb−Free Package
• Output Frequency Range: 5 MHz to 133 MHz
• Two LVTTL/LVCMOS Outputs
• 65 ps Typical Jitter OUT2
• 115 ps Typical Jitter OUT1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• 25 ps Typical Output−to−Output Skew
• Operating Voltage Range: V = 3.3 V $5% or 5 V $10%
DD
• Clock Multiplication of the Reference Input Frequency, See Table 1
for Options
• Packaged in 8−Pin SOIC
• −40°C to +85°C Ambient Operating Temperature Range
• Ideal for PCI−X and Networking Clocks
• These are Pb−Free Devices
External feedback connection
to OUT1 or OUT2, not both
FBIN
FS0
Select Input
Decoding
FS1
OUT1
OUT2
PLL
REF_IN
÷2
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011 − Rev. 1
NB3N2302/D
NB3N2302
FBIN
1
OUT2
8
REF_IN
2
3
4
7
6
5
V
DD
GND
FS0
OUT1
FS1
Figure 2. NB3N2302 Package Pinout (Top View) 8−pin SOIC (150 mil)
Table 1. CLOCK MULTIPLIER SELECT TABLE
REF_IN Min
REF_IN Max
(MHz)
(MHz)
FBIN
OUT1
OUT1
OUT1
OUT1
OUT2
OUT2
OUT2
OUT2
FS0
0
FS1
0
OUT1
2 x REF
4 x REF
REF
OUT2
REF
5
5
66.5
33.25
133
1
0
2 x REF
REF / 2
4 x REF
2 x REF
4 x REF
REF
0
1
10
5
1
1
8 x REF
4 x REF
8 x REF
2 x REF
16 x REF
16.625
33.25
16.625
66.5
0
0
5
1
0
5
0
1
5
1
1
8 x REF
5
8.3125
Table 2. PIN DESCRIPTION
Pin
Name
Pin #
Type
Description
1
FBIN
LVCMOS/LVTTL
Input
Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure
proper functionality. If the trace between FBIN and the output pin being used for feedback
is equal in length to the traces between the outputs and the signal destinations, then the
signals received at the destinations are synchronized to the REF signal input (REF_IN).
2
REF_IN
LVCMOS/LVTTL
Input
Reference Input: The output signals are synchronized to this signal.
3
4
GND
FS0
Power
Negative supply voltage; Connect to ground, 0 V
LVCMOS/LVTTL
Input
Function Select Input: Tie to V (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
DD
5
6
7
8
FS1
OUT1
VDD
LVCMOS/LVTTL
Input
Function Select Input: Tie to V (HIGH, 1) or GND (LOW, 0) as desired per Table 1.
DD
LVCMOS/LVTTL
Output
Output 1: The frequency of the signal provided by this pin is determined by the feedback
signal connected to FBIN, and the FS0:1 inputs (see Table 1).
Power
Positive supply voltage This pin should be bypassed with a 0.1 mF decoupling capacitor.
Use ferrite beads to help reduce noise for optimal jitter performance.
OUT2
LVCMOS/LVTTL
Output
Output 2: The frequency of the signal provided by this pin is one−half of the frequency of
OUT1. See Table 1.
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2
NB3N2302
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index
UL 94 V−O @ 0.125 in
6910 Devices
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
V
Voltage on any pin
GND = 0 V
–0.5 to +7.0
DD, IN
T
A
Operating Temperature Range,
Commercial
Industrial
0 to +70
−40 to +85
°C
T
Storage Temperature Range
−65 to +150
°C
°C
stg
T
Ambient Temperature under Bias
Thermal Resistance (Junction−to−Ambient)
–55 to +125
B
q
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
JA
P
Power Dissipation
0.5
42
W
°C/W
°C
D
q
Thermal Resistance (Junction−to−Case)
Wave Solder Pb−Free
(Note 2)
SOIC−8
JC
T
SOL
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power
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3
NB3N2302
Table 5. DC CHARACTERISTICS V = 3.3 V 5% or 5 V 10%, GND = 0 V, T = −40°C to +85°C
DD
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current, 100 MHz, Unloaded Outputs V = 3.3 V $ 5%
20
25
35
50
mA
DD
DD
V
= 5 V $ 10%
DD
V
Output HIGH Voltage I = −12 mA
2.4
2.0
V
V
OH
OH
V
Output LOW Voltage I = 12 mA
0.4
OL
OL
V
Input HIGH Voltage
Input LOW Voltage
V
IH
V
0.8
5
V
IL
I
Input HIGH Current, V = V
DD
mA
mA
IH
IN
I
Input LOW Current, V = 0 V
V
DD
DD
= 3.3 V $ 5%
= 5 V $ 10%
−40
−80
5
5
IL
IN
V
Table 6. AC CHARACTERISTICS V = 3.3 V 5% or 5 V 10%, GND = 0 V, T = −40°C to +85°C (Note 5)
DD
A
Symbol
Characteristic
Min
5
Typ
Max
Unit
MHz
MHz
%
f
IN
Input Frequency (Note 3)
133
133
60
f
Output Frequency, OUT1 15 pF load
10
40
OUT
t
D
Output Duty Cycle @ 1.4 V, 120 MHz, 50% duty cycle in, 15 pF load
50
t /t
Output rise and fall times; 0.8 V to 2.0V, 15 pF load V = 3.3 V $ 5%
3.5 / 2.5
2.5 / 1.5
ns
r
f
DD
V
= 5 V $ 10%
DD
t
Input Clock rise and fall time (Note 4)
10
ns
INCLK
t /t
r
f
t
PLL Lock Time, power supply stable
1.0
ms
ps
LOCK
t
JC
Cycle−to−cycle Jitter
OUT1, f
> 30 MHz
> 30 MHz
115
65
300
300
OUT
OUT
OUT2, f
t
Die “Fave Away” Out Time. 33 MHz reference input suddenly stopped
(0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
100
Clock
Cycles
DC
t
Propagation Delay, (Note 10)
−350
350
250
ps
ps
pd
t
Output−to−output skew; (Note 6)
25
skew
3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit
configuration). See Table 1.
4. Longer input rise and fall time degrades skew and jitter performance.
5. All AC specifications are measured with a 50 W transmission line, load terminated with 50 W to 1.4 V.
6. Skew is measured at 1.4 V on rising edges, all outputs with equal loading.
7. Duty cycle is measured at 1.4 V.
8. 33 MHz reference input suddenly stopped (0 MHz). Number of cycles provided prior to output falling to < 16 MHz.
9. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.
10.While in lock, propagation delay is measured from REF_IN to OUT1 using < 1 in feedback trace, (See Figure 1).
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4
NB3N2302
Overview
Delay feature. This is explained further in the sections of this
datasheet titled “How to Implement Zero Delay,” and
“Inserting Other Devices in Feedback Path.”
The NB3N2302 is a two−output zero delay buffer and
frequency multiplier. It provides an external feedback path
allowing maximum flexibility when implementing the Zero
Figure 3. Schematic / Suggested Layout
How to Implement Zero Delay
Inserting Other Devices in Feedback Path
Typically, Zero Delay Buffers (ZDBs) are used because a
designer wants to provide multiple copies of a clock signal
in phase with each other. The whole concept behind ZDBs
is that the signals at the destination chips are all going HIGH
at the same time as the input to the ZDB. In order to achieve
this, layout must compensate for trace length between the
ZDB and the target devices. The method of compensation is
described as follows.
External feedback is the trait that allows for this
compensation. The PLL on the ZDB causes the feedback
signal to be in phase with the reference signal. When laying
out the board, match the trace lengths between the output
being used for feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly
precede the input signal, this may also be implemented by
either making the trace to the FBIN pin a little shorter or a
little longer than the traces to the devices being clocked.
Another nice feature available due to the external
feedback is the ability to synchronize signals to the signal
coming from some other device. This implementation can
be applied to any device (ASIC, multiple output clock
buffer/driver, etc.) that is put into the feedback path.
Referring to Figure 4, if the traces between the
ASIC/Buffer and the destination of the clock signal(s) are
equal in length to the trace between the buffer and the FBIN
pin, the signals at the destination(s) device is driven HIGH
at the same time when the Reference clock provided to the
ZDB goes HIGH. Synchronizing the other outputs of the
ZDB to the outputs from the ASIC/Buffer is more complex
however, as any propagation delay from the ZDB output to
the ASIC/Buffer output must be accounted for.
Reference
Input Signal
NB3N2302
Zero
Delay
Buffer
ASIC /
Buffer /
Fanout
Feedback
Signal
Figure 4. Output Buffer in the Feedback Path
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5
NB3N2302
Phase Alignment
supplied). If OUT2 is desired to be rising−edge aligned to
the IN input’s rising edge, then connect the OUT2 (i.e., the
lowest frequency output) to the FBIN pin. This set−up
provides a consistent input−output phase relationship.
In cases where OUT1 (i.e., the higher frequency output)
is connected to FBIN input pin the output OUT2 rising edges
may be either 0° or 180° phase aligned to the IN input
waveform (as set randomly when the input and/or power is
Figure 5. Switching Waveforms
ORDERING INFORMATION
Device
†
Package
Shipping
NB3N2302DG
SOIC−8
(Pb−Free)
98 Units / Rail
NB3N2302DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
NB3N2302
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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NB3N2302/D
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