NB4N11MDTR2G [ONSEMI]
多电平时钟/数据输入至 CML 接收器/缓冲器/转换器，2.5 Gbps，3.3 V;
| 型号： | NB4N11MDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 多电平时钟/数据输入至 CML 接收器/缓冲器/转换器，2.5 Gbps，3.3 V 时钟 光电二极管 接口集成电路 锁存器 转换器 |
| 文件： | 总12页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V, 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/Buffer/Translator
NB4N11M
Description
www.onsemi.com
The NB4N11M is a differential 1−to−2 clock/data
distribution/translation chip with CML output structure, targeted for
high−speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
8
1
TSSOP−8
DT SUFFIX
CASE 948R
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
(See Table 5). The CML outputs are 16 mA open collector
MARKING DIAGRAM*
(See Figure 18) which requires resistor (R ) load path to V
L
TT
8
termination voltage. The open collector CML outputs must be
terminated to V at power up. Differential outputs produces
E11M
TT
ALYWG
current–mode logic (CML) compatible levels when receiver loaded
with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
The device is offered in a small 8−pin TSSOP package.
Application notes, models, and support documentation are available
at www.onsemi.com.
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
(Note: Microdot may be in either location)
• Maximum Input Clock Frequency > 2.5 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• Typically 1 ps of RMS Clock Jitter
*For additional marking information, refer to
Application Note AND8002/D.
• Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R = 25 W
Q0
L
• 420 ps Typical Propagation Delay
Q0
• 150 ps Typical Rise and Fall Times
D
D
• Operating Range: V = 3.0 V to 3.6 V with V = 0 V and
CC
EE
V
TT
= 1.8 V to 3.6 V
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
Q1
Q1
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
May, 2021 − Rev. 3
NB4N11M/D
NB4N11M
Q0
Q0
1
2
8
7
V
CC
D
D
6
5
Q1
Q1
3
4
V
EE
Figure 2. Pinout (Top View) and Logic Diagram
Table 1. Pin Description
Pin
Name
I/O
Description
1
Q0
CML Output
Noninverted differential output. Typically receiver terminated with 50 W
resistor to V . Open collector CML outputs must be terminated to V at
TT
TT
powerup.
2
3
Q0
Q1
CML Output
CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to V . Open collector CML outputs must be terminated to V at powerup.
TT
TT
Noninverted differential output. Typically receiver terminated with 50 W
resistor to V . Open collector CML outputs must be terminated to V at
TT
TT
powerup.
4
Q1
CML Output
Inverted differential output. Typically receiver terminated with 50 W resistor
to V . Open collector CML outputs must be terminated to V at powerup.
TT
TT
5
6
V
−
Negative supply voltage.
Inverted differential input.
EE
D
LVPECL, CML, HSTL,
LVCMOS, LVDS, LVTTL Input
7
8
D
LVPECL, CML, HSTL,
Noninverted differential input.
Positive supply voltage.
LVCMOS, LVDS, LVTTL Input
V
CC
−
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2
NB4N11M
Table 2. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 1000 V
> 70 V
Moisture Sensitivity (Note 1)
8−TSSOP
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
197
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
= −0.5 V
Condition 2
Rating
Unit
V
CC
V
EE
V
CC
4
V
V
V
EE
Negative Power Supply
= +0.5 V
−4
V
I
Positive Input
Negative Input
V
EE
V
CC
= 0 V
= 0 V
V = V +0.4 V
4
−4
V
V
I
CC
V = V –0.4 V
I
EE
V
O
Output Voltage
Minimum
Maximum
V
+ 600
+ 400
mV
mV
EE
CC
V
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
190
130
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
1S2P (Note 2)
TSSOP−8
41 to 44
265
°C/W
°C
JC
T
sol
Wave Solder
< 3 Sec @ 260°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N11M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs V = 3.0 V to 3.6 V, V = 0 V, T = −40°C to +85°C
CC
EE
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Inputs and Outputs Open)
25
35
mA
CC
R = 50 W, V = 3.6 V to 2.5 V
L
TT
V
Output HIGH Voltage (Note 3)
V
− 60
V
− 10
V
TT
mV
mV
mV
OH
TT
TT
TT
TT
TT
V
Output LOW Voltage (Note 3)
V
TT
− 1100
V
− 800
V
V
V
V
− 640
OL
TT
TT
|V
|
Differential Output Voltage Magnitude
640
780
1000
OD
R = 25 W, V = 3.6 V to 2.5 V $5%
L
TT
V
OH
Output HIGH Voltage (Note 3)
V
TT
− 60
V
− 10
V
TT
mV
mV
mV
V
Output LOW Voltage (Note 3)
V
TT
− 550
V
TT
− 400
− 320
TT
OL
|V
|
Differential Output Voltage Magnitude
320
390
500
OD
R = 50 W, V = 1.8 V $5%
L
TT
V
OH
Output HIGH Voltage (Note 3)
V
TT
− 170
− 1100
570
V
− 10
V
TT
mV
mV
mV
V
Output LOW Voltage (Note 3)
V
TT
V
TT
− 800
− 640
TT
OL
|V
|
Differential Output Voltage Magnitude
780
1000
OD
R = 25 W, V = 1.8 V $5%
L
TT
V
OH
Output HIGH Voltage (Note 3)
V
TT
− 85
V
− 10
V
TT
mV
mV
mV
V
Output LOW Voltage (Note 3)
V
TT
− 500
V
TT
− 400
− 320
TT
OL
|V
|
Differential Output Voltage Magnitude
285
390
500
OD
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14 and 16)
V
Input Threshold Reference Voltage Range (Note 5)
Single−ended Input HIGH Voltage
V
V
mV
mV
mV
th
EE
CC
V
IH
V
+ 100
V
+ 400
th
CC
V
IL
Single−ended Input LOW Voltage
V
− 400
V
− 100
EE
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)
V
Differential Input HIGH Voltage
V
V
V
+ 400
mV
mV
mV
mV
pF
IHD
EE
CC
V
Differential Input LOW Voltage
V
− 400
− 100
ILD
EE
CC
V
CMR
Input Common Mode Range (Differential Configuration)
V
EE
V
CC
|V
|
Differential Input Voltage Magnitude (|V
Input Capacitance (Note 7)
− V |) (Note 7)
100
V
CC
− V
EE
ID
IHD
ILD
C
1.5
IN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. CML outputs require R receiver termination resistors to V for proper operation. Outputs must be connected through R to V at power
L
TT
L
TT
up. The output parameters vary 1:1 with V
.
TT
4. Input parameters vary 1:1 with V
.
CC
5. V is applied to the complementary input when operating in single−ended mode.
th
CMR
6. V
(MIN) varies 1:1 with V , V
max varies 1:1 with V
.
EE
CMR
CC
7. Parameter guaranteed by design and evaluation but not tested in production.
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4
NB4N11M
Table 5. AC CHARACTERISTICS V = 3.0 V to 3.6 V, V = 0 V; (Note 8)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (R = 50 W)
mV
OUTPP
OUTPP
L
f
in
f
in
f
in
≤ 1 GHz
550
400
150
660
640
400
550
400
150
660
640
400
550
400
150
660
640
400
(See Figure 12)
≤ 1.5 GHz
≤ 2.5GHz
V
Output Voltage Amplitude (R = 25 W)
mV
L
f
in
f
in
f
in
≤ 1 GHz
≤ 1.5 GHz
≤ 2.5GHz
280
280
100
370
360
300
280
280
100
370
360
400
280
280
100
370
360
400
(See Figure 12)
f
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
ps
DATA
t
t
,
Propagation Delay to Output Differential
@ 0.5 GHz
300
420
600
300
420
600
300
420
600
PLH
PHL
t
Duty Cycle Skew (Note 9)
Within Device Skew
2
5
20
25
2
5
20
25
2
5
20
25
ps
ps
SKEW
Device to Device Skew (Note 13)
20
100
20
100
20
100
t
RMS Random Clock Jitter R = 50 W and
L
R = 25 W (Note 11)
L
JITTER
1
1
1
3
3
3
1
1
1
3
3
3
1
1
1
3
3
3
f
in
f
in
f
in
= 750 MHz
= 1.5 GHz
= 2.5 GHz
Peak−to−Peak Data Dependent Jitter R = 50 W
L
15
20
55
85
15
20
55
85
15
20
55
85
f
f
= 1.5 Gb/s
= 2.5 Gb/s
DATA
DATA
(Note 12)
Peak−to−Peak Data Dependent Jitter R = 25 W
L
5
10
35
35
5
10
35
35
5
10
35
35
f
f
= 1.5 Gb/s
= 2.5 Gb/s
DATA
DATA
(Note 12)
V
Input Voltage Swing/Sensitivity
100
100
100
mV
ps
INPP
(Differential Configuration) (Note 10)
t
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
150
300
150
300
150
300
r
t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Measured by forcing V
(MIN) from a 50% duty cycle clock source. All output loaded with an external R = 50 W and R = 25 W to V
.
TT
INPP
L
L
Outputs must be connected through R to V at power up. Input edge rates 150 ps (20% − 80%).
L
TT
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
and T
@ 0.5 GHz.
pw−
pw+
10.V
(MAX) cannot exceed V − V . Input voltage swing is a single−ended measurement operating in differential mode.
INPP
CC EE
11. Additive RMS jitter with 50% duty cycle clock signal.
23
12.Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 2 −1).
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800
700
600
500
400
300
200
100
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
R = 50 W
L
R = 50 W
L
R = 25 W
R = 25 W
L
L
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
(V − V = 3.3 V V = 3.3 V @ 255C V = 100 mV)
(V − V = 3.0 V V = 1.71 V @255C V = 100 mV)
CC
EE
TT
in
CC
EE
TT
in
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
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5
NB4N11M
NB4N11M
35
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
85°C
25°C
−40°C
85°C
−40°C
25°C
0
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
INPUT CLOCK FREQUENCY (GHz)
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 50 W)
Figure 5. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 25 W)
600
550
500
450
400
350
300
600
550
500
450
400
350
t
t
PD
PD
300
V
− 0.5 V
VCC * VEE
V
CC
+ 0.5 V
−40
25
85
EE
2
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (V)
Figure 6. Typical Propagation Delay vs.
Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV; RL = 50 W)
Figure 7. Typical Propagation Delay vs. Input
Offset Voltage (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV RL = 50 W)
35
30
25
20
15
10
5
I
CC
0
−40
25
85
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
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6
NB4N11M
DDJ = 5 ps
DDJ = 3 ps
TIME (266.8 ps/div)
TIME (266.8 ps/div)
Figure 9. Typical Differential Output Waveform at 750 Mb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
DDJ = 5 ps
DDJ = 12 ps
TIME (133.2 ps/div)
TIME (133.2 ps/div)
Figure 10. Typical Differential Output Waveform 1.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 25 ps)
DDJ = 20 ps
DDJ = 7 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 11. Typical Differential Output Waveform 2.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
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7
NB4N11M
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 12. AC Reference Measurement
V
TT
50 W
50 W
Q
Q
D
D
DUT
Z = 50 W
Receiver
Device
Driver
Device
Z = 50 W
Figure 13. Typical Termination for Output Driver and Device Evaluation
D
D
D
D
V
th
V
th
Figure 14. Differential Input Driven
Figure 15. Differential Inputs Driven
Differentially
Single−Ended
V
V
CC
CC
V
IHCLKmax
V
V
IHmax
V
V
CMmax
thmax
V
ILCLKmax
ILmax
V
= V
− V
ID
V
IHD ILD
D
D
V
V
IH
th
IHDtyp
ILDtyp
IHDmin
V
CMR
V
th
D
V
V
IL
V
V
IHmin
V
ILmin
V
V
CMmax
thmin
GND
V
ILDmin
GND
Figure 16. Vth Diagram
Figure 17. VCMR Diagram
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8
NB4N11M
V
CC
Input
ESD
Input
ESD
Q
Q
1.25 kW
1.25 kW
1.25 kW
1.25 kW
R
R
C
C
IN
D
D
IN
Input
ESD
Input
ESD
Internal
Current Source
16 mA
Current Source
V
EE
V
EE
Input
Output
Figure 18. CML Input and Output Structure
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9
NB4N11M
V
TTA
= V
CCA
V
CCA
= 1.8 V 2.5 V or 3.3 V
V
CC
= 3.3 V
50 W
50 W
Z = 50 W
Z = 50 W
Receiver
A
NB4N11M
V
TTB
= V
CCB
V
TTB
= V
CCB
50 W
50 W
Z = 50 W
Z = 50 W
V
CCB
= 1.8 V 2.5 V or 3.3 V
50 W
50 W
Receiver
B
V
EE
= 0 V
V
TTC
= V
CCC
V
CCC
= 1.8 V 2.5 V or 3.3 V
V
CC
= 3.3 V
75 W
75 W
Z = 75 W
Z = 75 W
Receiver
C
NB4N11M
V
TTD
= V
CCD
Z = 100 W
Z = 100 W
V
CCD
= 1.8 V 2.5 V or 3.3 V
100 W
100 W
Receiver
D
V
EE
= 0 V
Figure 19. Typical Examples of the Application Interface
ORDERING INFORMATION
Device
†
Package
Shipping
NB4N11MDTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP 8
CASE 948R−02
ISSUE A
DATE 04/07/2000
SCALE 2:1
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40 0.010
0.016
4.90 BSC
_
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON00236D
TSSOP 8
PAGE 1 OF 1
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