NB4N316MDTR2G [ONSEMI]
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis; 3.3 V AnyLevel接收到CML驱动器/转换器与输入滞后
| 型号： | NB4N316MDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis |
| 文件： | 总12页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4N316M
3.3 V AnyLevelt Receiver
to CML Driver/Translator
with Input Hysteresis
2.0 GHz Clock / 2.5 Gb/s Data
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The NB4N316M is a differential Clock or Data receiver and will
accept AnyLevelt input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to CML, operating
up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is
ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or
Data distribution applications. The CML outputs are 16 mA open
MARKING
DIAGRAM*
8
8
1
E316
ALYWG
G
TSSOP−8
DT SUFFIX
CASE 948R
collector (see Figure 18) which requires resistor (R ) load path to V
L
TT
termination voltage (see Figure 19). The open collector CML outputs
1
must be terminated to V at power up. The differential outputs
TT
produce Current–Mode Logic (CML) compatible levels when the
receiver is loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V
or 3.3 V supplies. This simplifies device interface by eliminating a
need for coupling capacitors.
The NB4N316M features an input threshold hysteresis of
approximately 25 mV, providing increased noise immunity and stability.
The device is offered in a small 8−pin TSSOP package (MSOP−8
compatible). Application notes, models, and support documentation
are available at www.onsemi.com.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• Typically 1 ps of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 550 ps Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• Differential CML Outputs
Q
Q
D
D
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
• 25 mV of Receiver Input Threshold Hysteresis
• Operating Range: V = 3.0 V to 3.6 V with V = 0 V and
CC
EE
V
TT
= 1.8 V to 3.6 V
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL,
LVEP, EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 3
NB4N316M/D
NB4N316M
NC
D
1
2
8
7
V
CC
Q
Q
D
3
4
6
5
V
V
EE
BB
Figure 2. Pinout (Top View) and Logic Diagram
Table 1. Pin Description
Pin
1
Name
NC
I/O
Description
−
No Connect.
2
D
ECL, CML, LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. (Note 1)
3
D
ECL, CML, LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. (Note 1)
4
5
6
7
8
V
V
−
Internally Generated Reference Voltage Supply.
Negative Supply Voltage.
BB
EE
−
Q
Q
CML Output
CML Output
−
Inverted Differential Output. Typically Terminated with 50 W Resistor to V .
TT
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
.
TT
V
Positive Supply Voltage.
CC
1. In the differential configuration if no signal is applied on D/D input, then the device will be susceptible to self−oscillation.
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2
NB4N316M
Table 2. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 1000 V
> 70 V
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
8−TSSOP
Level 3
UL 94 V−0 @ 0.125 in
225
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
= −0.5 V
Condition 2
Rating
Unit
V
V
V
V
V
V
4
CC
EE
I
EE
CC
Negative Power Supply
= +0.5 V
−4
V
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V = V +0.4 V
4
−4
V
V
EE
CC
I
I
CC
V = V –0.4 V
EE
V
Output Voltage
Minimum
Maximum
V
+ 600
+ 400
mV
mV
O
EE
CC
V
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
190
130
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
1S2P (Note 2)
TSSOP−8
41 to 44
265
°C/W
°C
JC
T
sol
Wave Solder
< 3 Sec @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N316M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs V = 3.0 V to 3.6 V, V = 0 V, T = −40°C to +85°C
CC
EE
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Inputs and Outputs Open)
20
30
mA
CC
R = 50 W, V = 3.6 V to 2.5 V
L
TT
V
Output HIGH Voltage (Note 3)
V
− 60
V
− 10
V
TT
mV
mV
mV
OH
OL
TT
TT
TT
TT
TT
V
Output LOW Voltage (Note 3)
V
− 1100
V
− 800
V
V
V
V
− 640
TT
TT
TT
|V
|
Differential Output Voltage Magnitude
640
780
1000
OD
R = 25 W, V = 3.6 V to 2.5 V $5%
L
TT
V
Output HIGH Voltage (Note 3)
V
− 60
V
− 10
V
TT
mV
mV
mV
OH
TT
V
Output LOW Voltage (Note 3)
V
− 550
V
− 400
− 320
TT
OL
TT
TT
|V
|
Differential Output Voltage Magnitude
320
390
500
OD
R = 50 W, V = 1.8 V $5%
L
TT
V
Output HIGH Voltage (Note 3)
V
− 170
− 1100
570
V
− 10
V
TT
mV
mV
mV
OH
TT
V
Output LOW Voltage (Note 3)
V
V
− 800
− 640
TT
OL
TT
TT
|V
|
Differential Output Voltage Magnitude
780
1000
OD
R = 25 W, V = 1.8 V $5%
L
TT
V
Output HIGH Voltage (Note 3)
V
− 85
V
− 10
V
TT
mV
mV
mV
OH
TT
V
Output LOW Voltage (Note 3)
V
− 500
V
− 400
− 320
TT
OL
TT
TT
|V
|
Differential Output Voltage Magnitude
285
390
500
OD
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14 and 16)
V
V
V
V
Input Threshold Reference Voltage Range (Note 5)
Single−ended Input HIGH Voltage
V
V
mV
mV
mV
mV
th
EE
CC
V
+ 100
− 400
− 1500
V + 400
CC
IH
IL
th
Single−ended Input LOW Voltage
V
V
− 100
th
EE
Internally Generated Reference Voltage Supply (Loaded with −100 mA)
V
V
− 1400
V − 1300
CC
BB
CC
CC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)
V
V
V
V
Differential Input HIGH Voltage
V
V
+ 400
mV
mV
mV
mV
mV
pF
IHD
EE
CC
CC
Differential Input LOW Voltage
V
− 400
EE
V
− 100
ILD
Input Common Mode Range (Differential Configuration)
V
V
CC
CMR
ID(HYST)
EE
Differential Input Voltage Hysteresis (V
− V
)
25
IHD
ILD
|V
|
ID
Differential Input Voltage Magnitude (|V
Input Capacitance (Note 7)
− V |) (Note 7)
100
V
− V
EE
IHD
ILD
CC
C
1.5
IN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. CML outputs require R receiver termination resistors to V for proper operation. Outputs must be connected through R to V at power
L
TT
L
TT
up. The output parameters vary 1:1 with V . V = 1.71 V to 3.6 V.
TT TT
4. Input parameters vary 1:1 with V
.
CC
5. V is applied to the complementary input when operating in single−ended mode.
th
6. V
(MIN) varies 1:1 with V , V
max varies 1:1 with V
.
CMR
EE
CMR
CC
7. Parameter guaranteed by design and evaluation but not tested in production.
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4
NB4N316M
Table 5. AC CHARACTERISTICS V = 3.0 V to 3.6 V, V = 0 V; (Note 8)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (R = 50 W)
mV
OUTPP
OUTPP
DATA
L
f
f
f
≤ 1 GHz
550
400
200
660
640
400
550
400
200
660
640
400
550
400
200
660
640
400
in
in
in
(See Figure 12)
≤ 1.5 GHz
≤ 2.0 GHz
V
Output Voltage Amplitude (R = 25 W)
mV
L
f
f
f
≤ 1 GHz
≤ 1.5 GHz
≤ 2.0 GHz
280
280
200
370
360
300
280
280
200
370
360
400
280
280
200
370
360
400
in
in
in
(See Figure 12)
f
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
ps
t
t
,
Propagation Delay to Output Differential
@ 0.25 GHz
350
550
750
350
550
750
350
550
750
PLH
PHL
t
Duty Cycle Skew (Note 9)
2
20
2
20
2
20
ps
ps
SKEW
Device to Device Skew (Note 13)
20
100
20
100
20
100
t
RMS Random Clock Jitter R = 50 W and
R = 25 W (Note 11)
L
JITTER
L
1
1
1
3
3
3
1
1
1
3
3
3
1
1
1
3
3
3
f
f
f
= 750 MHz
= 1.5 GHz
= 2.0 GHz
in
in
in
Peak−to−Peak Data Dependent Jitter R = 50 W
L
15
20
55
85
15
20
55
85
15
20
55
85
f
f
= 1.5 Gb/s
= 2.5 Gb/s
DATA
DATA
(Note 12)
Peak−to−Peak Data Dependent Jitter R = 25 W
L
5
10
35
35
5
10
35
35
5
10
35
35
f
f
= 1.5 Gb/s
= 2.5 Gb/s
DATA
DATA
(Note 12)
V
Input Voltage Swing/Sensitivity
200
200
200
mV
ps
INPP
(Differential Configuration) (Note 10)
t
t
Output Rise/Fall Times @ 0.25 GHz
(20% − 80%)
Q, Q
150
300
150
300
150
300
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing V
(MIN) from a 50% duty cycle clock source. All output loaded with an external R = 50 W and R = 25 W to V
.
TT
INPP
L
L
Outputs must be connected through R to V at power up. Input edge rates 150 ps (20% − 80%).
L
TT
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
and T
@ 0.25 GHz.
pw−
pw+
10.V
(MAX) cannot exceed V − V . Input voltage swing is a single−ended measurement operating in differential mode.
INPP
CC EE
11. Additive RMS jitter with 50% duty cycle clock signal.
23
12.Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 2 −1).
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800
700
600
500
400
300
200
100
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
R = 50 W
L
R = 50 W
L
R = 25 W
L
R = 25 W
L
0.5
0.75
1
1.25
1.5
1.75
2
0.5
0.75
1
1.25
1.5
1.75
2
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
(V − V = 3.3 V V = 3.3 V @ 255C V = 100 mV)
(V − V = 3.0 V V = 1.71 V @255C V = 100 mV)
CC
EE
TT
in
CC
EE
TT
in
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
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5
NB4N316M
NB4N316M
35
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
85°C
−40°C
25°C
−40°C
25°C
85°C
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
0.25
0.5
0.75
1
1.25
1.5
1.75
2
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 50 W)
Figure 5. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 25 W)
600
550
500
450
400
350
300
600
550
500
450
400
350
t
PD
t
PD
300
V
− 0.5 V
VCC * VEE
V
+ 0.5 V
CC
−40
25
85
EE
2
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (V)
Figure 6. Typical Propagation Delay vs.
Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV; RL = 50 W)
Figure 7. Typical Propagation Delay vs. Input
Offset Voltage (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV RL = 50 W)
35
30
25
20
15
10
5
I
CC
0
−40
25
85
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
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NB4N316M
DDJ = 5 ps
DDJ = 3 ps
TIME (266.8 ps/div)
TIME (266.8 ps/div)
Figure 9. Typical Differential Output Waveform at 750 Mb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
DDJ = 5 ps
DDJ = 12 ps
TIME (133.2 ps/div)
TIME (133.2 ps/div)
Figure 10. Typical Differential Output Waveform 1.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 25 ps)
DDJ = 20 ps
DDJ = 7 ps
TIME (80 ps/div)
TIME (80 ps/div)
Figure 11. Typical Differential Output Waveform 2.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
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NB4N316M
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 12. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
D
D
D
D
V
th
V
th
Figure 14. Differential Input Driven
Figure 15. Differential Inputs Driven
Differentially
Single−Ended
V
V
CC
CC
V
IHCLKmax
V
V
IHmax
V
V
CMmax
thmax
V
ILCLKmax
ILmax
V
= V
− V
ID
IHD ILD
D
D
V
V
V
IH
th
IHDtyp
ILDtyp
IHDmin
V
CMR
V
D
th
V
V
IL
V
V
V
IHmin
ILmin
V
V
CMmax
thmin
GND
V
ILDmin
GND
Figure 16. Vth Diagram
Figure 17. VCMR Diagram
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NB4N316M
V
CC
Input
ESD
Input
ESD
Q
Q
1.25 kW
1.25 kW
1.25 kW
1.25 kW
R
C
R
C
IN
D
D
IN
Input
ESD
Input
ESD
Internal
Current Source
16 mA
Current Source
V
EE
V
Input
EE
Output
Figure 18. CML Input and Output Structure
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NB4N316M
V
= V
CCA
TTA
V
= 1.8 V 2.5 V or 3.3 V
CCA
V
= 3.3 V
50 W
50 W
CCA
Z = 50 W
Z = 50 W
Receiver
A
NB4N316M
V
= V
CCB
TTB
V
= 0 V
EE
V
= V
TTB CCB
V
= 3.3 V
CCB
50 W
50 W
Z = 50 W
Z = 50 W
V
= 1.8 V 2.5 V or 3.3 V
CCB
50 W
50 W
NB4N316M
Receiver
B
V
= 0 V
EE
V
= V
CCC
TTC
V
= 1.8 V 2.5 V or 3.3 V
CCC
V
= 3.3 V
75 W
75 W
CCC
Z = 75 W
Z = 75 W
Receiver
C
NB4N316M
V
= V
CCD
TTD
V
= 0 V
EE
V
= 3.3 V
CCD
Z = 100 W
Z = 100 W
V
= 1.8 V 2.5 V or 3.3 V
CCD
100 W
100 W
NB4N316M
Receiver
D
V
= 0 V
EE
Figure 19. Typical Examples of the Application Interface
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NB4N316M
ORDERING INFORMATION
Device
†
Package
Shipping
NB4N316MDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
NB4N316MDTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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NB4N316M
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
AnyLevel and ECLinPS are trademarks of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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