NB4N527S [ONSEMI]
3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination; 3.3V ， 2.5Gb / s的双AnyLevel⑩到LVDS接收器/驱动器/缓冲器/转换器具有内部输入终端
| 型号： | NB4N527S |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination |
| 文件： | 总10页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
http://onsemi.com
MARKING
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
TM
capable of translating AnyLevel
input signal (LVPECL, CML,
DIAGRAM*
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
16
1
NB4N
527S
ALYW G
G
1
The NB4N527S has a wide input common mode range of
QFN−16
MN SUFFIX
CASE 485G
GND + 50 mV to V − 50 mV combined with two 50 W internal
CC
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• Maximum Input Clock Frequency up to 1.5 GHz
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
• 470 ps Maximum Propagation Delay\
• 1 ps Maximum RMS Jitter
*For additional marking information, refer to
Application Note AND8002/D.
• 140 ps Maximum Rise/Fall Times
50 W*
• Single Power Supply; V = 3.3 V $10%
CC
VTD0
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• Internal 50 W Termination Resistor per Input Pin
D0
D0
Q0
Q0
• GND + 50 mV to V − 50 mV V
Range
CC
CMR
50 W*
50 W*
VTD0
• Pb−Free Packages are Available
VTD1
D1
D1
Q1
Q1
50 W*
VTD1
Device DDJ = 10 ps
Figure 1. Functional Block Diagram
*R
TIN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 3
NB4N527S/D
NB4N527S
Exposed Pad (EP)
VTD0 D0
16 15
D0 VTD0
14 13
V
V
1
2
3
4
12
11
10
9
Q0
TD1
D1
D1
Q0
Q1
Q1
NB4N527S
TD1
5
GND NC NC
Figure 3. Pin Configuration (Top View)
6
7
8
V
CC
Table 1. PIN DESCRIPTION
Pin
1
Name
VTD1
D1
I/O
Description
Internal 50 W termination pin for D1. (R
−
)
TIN
2
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D1 input (Note 1).
3
D1
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D1 input (Note 1).
4
5
VTD1
GND
NC
−
−
Internal 50 W termination pin for D1. (R
)
TIN
0 V. Ground.
6, 7
8
No connect.
V
Positive Supply Voltage.
CC
9
Q1
Q1
Q0
Q0
LVDS Output
LVDS Output
LVDS Output
LVDS Output
−
Inverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10
11
12
Noninverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Inverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Noninverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
13
14
VTD0
D0
Internal 50 W termination pin for D0.
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Noninverted differential clock/data D0 input (Note 1).
15
D0
LVPECL, CML, LVDS,
LVCMOS, LVTTL, HSTL
Inverted differential clock/data D0 input (Note 1).
16
VTD0
−
Internal 50 W termination pin for D0.
EP
Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
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2
NB4N527S
Table 2. ATTRIBUTES
Characteristics
Value
Level 1
Moisture Sensitivity (Note 2)
Flammability Rating
ESD Protection
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Transistor Count
281
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Positive Input
Condition 1
GND = 0 V
Condition 2
Rating
3.8
Unit
V
V
V
CC
I
GND = 0 V
V = V
3.8
V
I
CC
I
Input Current Through R (50 W Resistor)
Static
Surge
35
70
mA
mA
IN
T
I
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
OSC
Q or Q to GND
Q to Q
Continuous
Continuous
12
24
mA
T
Operating Temperature Range
QFN−16
−40 to +85
°C
°C
A
T
stg
Storage Temperature Range
−65 to +150
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
q
JA
Thermal Resistance (Junction−to−Case)
1S2P (Note 3)
QFN−16
4.0
°C/W
°C
q
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB4N527S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS V = 3.0 V to 3.6 V, GND = 0 V, T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Note 8)
40
53
mA
CC
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18)
V
V
V
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
GND +100
V
− 100
CC
mV
mV
mV
th
IH
IL
V
+ 100
V
CC
th
Single−ended Input LOW Voltage
GND
V
− 100
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
V
V
V
V
Differential Input HIGH Voltage
100
V
mV
mV
mV
mV
W
IHD
ILD
CMR
ID
CC
Differential Input LOW Voltage
GND
V
− 100
CC
Input Common Mode Range (Differential Configuration)
GND + 50
100
V
− 50
CC
Differential Input Voltage (V
− V )
ILD
V
IHD
CC
R
Internal Input Termination Resistor
LVDS OUTPUTS (Note 4)
Differential Output Voltage
40
50
1
60
TIN
V
250
0
450
25
mV
mV
mV
mV
mV
mV
OD
DV
Change in Magnitude of V
Offset Voltage (Figure 15)
for Complementary Output States (Note 9)
OD
OD
V
1125
0
1375
25
OS
DV
Change in Magnitude of V for Complementary Output States (Note 9)
1
OS
OS
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 6)
1425
1075
1600
OH
OL
900
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.
5. V max = V max + ½ V max.
OH
OS
OD
6. V max = V min − ½ V max.
OL
OS
OD
7. V is applied to the complementary input when operating in single−ended mode.
th
8. Input termination pins open, Dx/Dx at the DC level within V
and output pins loaded with R = 100 W across differential.
CMR
L
9. Parameter guaranteed by design verification not tested in production.
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4
NB4N527S
Table 5. AC CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V; (Note 10)
CC
−40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
(Figure 4)
) f ≤ 1.0 GHz 220 350
INPPmin in
220 350
200 300
220 350
200 300
mV
OUTPP
f = 1.5 GHz 200 300
in
f
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
ps
DATA
t
t
,
Differential Input to Differential Output
Propagation Delay
270 370
470
270 370
470
270 370
470
PLH
PHL
t
Duty Cycle Skew (Note 11)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
SKEW
t
RMS Random Clock Jitter (Note 13)
f
f
= 1.0 GHz
= 1.5 GHz
0.5
0.5
6
7
10
20
1
1
20
20
25
40
0.5
0.5
6
7
10
20
1
1
20
20
25
40
0.5
0.5
6
7
10
20
1
1
20
20
25
40
JITTER
in
in
ps
Deterministic Jitter (Note 14)
f
f
f
= 622 Mb/s
= 1.5 Gb/s
= 2.488 Gb/s
DATA
DATA
DATA
Crosstalk Induced Jitter (Note 16)
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100
V
GND
−
100
V
GND
−
100
V
GND
−
mV
ps
INPP
CC
CC
CC
t
t
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
Q, Q
60
100
140
60
100
140
60
100
140
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
with 50% duty cycle clock source and V − 1400 mV offset. All loading with an external R = 100 W across
INPPmin
C
C
L
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of t = |t − t | for a nominal 50% differential clock input waveform @ 250 MHz.
skew
PLH
PHL
12.Input voltage swing is a single−ended measurement operating in differential mode.
13.RMS jitter with 50% duty cycle input clock signal.
23
14.Deterministic jitter with input NRZ data at PRBS 2 −1 and K28.5.
15.Skew is measured between outputs under identical transition @ 250 MHz.
16.Crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 2 −1 as
an asynchronous signals.
23
17.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
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5
NB4N527S
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask
(VINPP = 100 mV; Input Signal DDJ = 14 ps)
R
C
R
C
1.25 kW
1.25 kW
Dx
1.25 kW
1.25 kW
50 W
50 W
I
V
V
TDx
TDx
D
x
Figure 6. Input Structure
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6
NB4N527S
V
V
V
V
CC
CC
CC
CC
NB4N527S
Dx
NB4N527S
Dx
Z = 50 W
o
Z = 50 W
o
50 W*
50 W*
V
V
V
V
TDx
TDx
TDx
TDx
LVPECL
Driver
LVDS
Driver
50 W*
50 W*
Z = 50 W
o
Z = 50 W
o
Dx
Dx
V
= V
TDx
TDx
V
= V
= V − 2.0 V
TDx CC
TDx
GND
GND
GND
GND
Figure 7. LVPECL Interface
Figure 8. LVDS Interface
V
V
V
V
CC
CC
CC
CC
NB4N527S
Dx
NB4N527S
Dx
Z = 50 W
o
Z = 50 W
o
V
CC
50 W*
50 W*
V
V
V
V
TDx
TDx
TDx
TDx
CML
Driver
HSTL
Driver
50 W*
50 W*
Z = 50 W
o
Z = 50 W
o
Dx
Dx
V
= V
= V
TDx CC
TDx
V
= V
= GND or V /2
TDx DD
TDx
Depending on Driver.
GND
GND
GND
GND
Figure 9. Standard 50 W Load CML Interface
Figure 10. HSTL Interface
V
V
V
V
CC
CC
CC
CC
NB4N527S
Dx
NB4N527S
Dx
Z = 50 W
o
Z = 50 W
o
50 W*
50 W*
V
V
V
V
TDx
TDx
TDx
TDx
LVCMOS
Driver
LVTTL
Driver
50 W*
50 W*
Dx
Dx
1.5 kW
2.5 kW
GND
GND
= OPEN
TDx
GND
GND
GND
V = OPEN
TDx
GND
V
= V
TDx
Dx = GND
Dx = GND
Figure 11. LVCMOS Interface
Figure 12. LVTTL Interface
*R , Internal Input Termination Resistor.
TIN
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7
NB4N527S
D
V
V
= V (D ) − V (D )
IH x IL x
INPP
D
Q
= V (Q ) − V (Q )
OUTPP
OH
x
OL
x
Q
t
PHL
t
PLH
Figure 13. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
LVDS
Driver
Device
LVDS
Receiver
Device
100 W
Z = 50 W
o
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
Q
Q
V
V
N
N
OH
OL
V
V
OS
OD
Figure 15. LVDS Output
D
D
D
D
V
V
IH
V
IL
th
V
th
Figure 16. Differential Input Driven
Single−Ended
Figure 17. Differential Inputs Driven
Differentially
V
CC
V
V
V
IH(MAX)
IL
V
CC
V
V
IHmax
ILmax
V
thmax
D
D
IH
V
V
= V
− V
IHD ILD
CMR
INPP
V
th
V
IL
V
V
IHmin
ILmin
V
V
V
IH
thmin
GND
IL(MIN)
V
EE
Figure 18. Vth Diagram
Figure 19. VCMR Diagram
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8
NB4N527S
ORDERING INFORMATION
Device
†
Package
Shipping
NB4N527SMN
QFN−16
123 Units / Rail
123 Units / Rail
NB4N527SMNG
QFN−16
(Pb−Free)
NB4N527SMNR2
NB4N527SMNR2G
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
QFN−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB4N527S
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
B
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
E2 1.65
1.85
0.10
0.08
C
C
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SOLDERING FOOTPRINT*
SIDE VIEW
D2
A1
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
0.012
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
1.50
0.059
E2
e
3.25
0.128
K
16X
12
1
16
13
0.30
16X b
0.012
0.50
0.02
0.10
0.05
C
C
A
B
BOTTOM VIEW
mm
inches
NOTE 3
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
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P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NB4N527S/D
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