NB4N7132 [ONSEMI]
Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA; 链接复制用于光纤通道，千兆以太网， HDTV和SATA
| 型号： | NB4N7132 |
| 厂家： | 
ONSEMI |
| 描述： | Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA |
| 文件： | 总6页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4N7132
Link Replicator for Fibre
Channel, Gigabit Ethernet,
HDTV and SATA
Up to 1.5 Gb/s
http://onsemi.com
Description
The NB4N7132 is a high performance 3.3 V Serial Link Replicator
which provides the function of serial loop replication and serial
loopback control commonly required in Fibre Channel, GbE, HDTV
and SATA applications. Other popular applications include Host Bus
Adaptors for routing between internal and external connectors, and
hot-pluggable links between redundant switch fabric cards.
IN is sent to both OUT0 and OUT1; each output is enabled by OE0
and OE1 when HIGH. OUT0 can select either IN or IN1 via the
MUX0 pin. Likewise, OUT1 can select between IN or IN0 via the
MUX1 pin. Out can select between IN0 and IN1.
28 Lead TSSOP
DT SUFFIX
CASE 948A
MARKING DIAGRAM*
In Link Replicator applications, such as the Line Card to Switch
Card links, IN is transmitted to both OUT0 and OUT1 which either
IN0 or IN1 is selected at OUT. In Host Adapter applications, IN goes
to OUT0 (an internal connector) which returns data on IN0. IN0 is
looped to OUT1 (an external connector) which returns data on IN1 and
then back to the SerDes on OUT.
NB4N
7132G
ALYW
The NB4N7132 is packaged in a 4.7 mm x 9.7 mm TSSOP-28.
A
L
= Assembly Location
= Wafer Lot
= Year
Features
•ꢀReplicates Fibre Channel, Gigabit Ethernet, HDTV, and
Serial ATA (SATA) Links
Y
W
G
= Work Week
= Pb-Free Package
•ꢀT11 Fibre Channel Complaint at 1.0625 Gb/s
•ꢀNo External Components Required
•ꢀIEEE802.3z Gigabit Ethernet Compliant at 1.25 Gb/s
•ꢀSMPTE-292M Compliant at 1.485 Gb/s
•ꢀ450 mW Maximum Power Dissipation
•ꢀOperating Range: V = 3.135 V to 3.465 V
•ꢀ28-pin, 4.4 mm x 9.7 mm TSSOP Package
•ꢀThese are Pb-Free Devices
*For additional marking information, refer to
Application Note AND8002/D.
NB4N7132
CC
LOOP0
LOOP1
TX
RX
Figure 1. Simplified Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©ꢀ Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 0
1
Publication Order Number:
NB4N7132/D
NB4N7132
TYPICAL APPLICATIONS CIRCUIT
VDDP0
OE0
1
2
28 OUT0+
27 OUT0-
26 VDDP0
MUX
IN0+
3
IN0-
GND
GND
25
4
IN0+
24
IN+
5
OE0
IN+
IN-
0
1
IN0-
23
IN-
6
OUT0+
OUT0-
GND
VDDP1
22
7
NB4N7132
0
1
OUT1+
21
OE1
8
OUT+
OUT-
MUX0
IN1+
VDD
IN1-
OUT1-
20
9
VDDP1
19
VDDP
OE1
10
11
12
13
14
MUX
0
1
IN1+
18
OUT+
OUT1+
OUT1-
OUT-
IN1-
17
MUX0
16
VDDP
MUX1
MUX1
15
GND
Figure 2. Simplified Block Diagram
Figure 3. Pin Diagram for TSSOP-28
Table 1. OE, OUTPUT ENABLE FUNCTION
OEx*
Function
Outputs Enabled
Outputs Disabled OUTn+ = H, OUTn- = H
1
0
*Defaults to HIGH when left open
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
5, 6
24, 23
18, 17
IN+, IN-
IN0+, IN0-
IN1+, IN1-
LVPECL Input
LVPECL Input
LVPECL Input
Non-inverted, Inverted, Differential Data Inputs internally biased to
Approximately 1.2 V.
11, 12
28, 27
21, 20
OUT+, OUT-
OUT0+, OUT0-
OUT1+, OUT1-
LVPECL Output Non-inverted, Inverted Differential Outputs.
LVPECL Output
LVPECL Output
2
8
OE0
OE1
LVTTL Input
LVTTL Input
OE0/OE1 enables OUT0/OUT1 when HIGH. When LOW, OUTx are
powered down and both OUT+ and OUT- float HIGH.
3
15
16
9
MUX
MUX1
MUX0
VDD
LVTTL Input
LVTTL Input
LVTTL Input
Selects Source for OUT, Selects Either IN0 (LOW) or IN1 (HIGH); defaults
HIGH when left open.
Selects Source for OUT1. Selects Either IN (HIGH) or IN0 (LOW); defaults
HIGH when left open.
Selects Source for OUT0. Selects either IN (LOW) or IN1 (HIGH); defaults
HIGH when left open.
Power Supply
Power Supply
3.3 V Positive Supply Voltage for Digital Logic.
10, 13
1, 26
19, 22
VDDP
VDDP0
VDDP1
3.3 V supply for LVPECL output drivers. VDDP is for OUT, VDDP0 is for
OUT0, and VDDP1 is for OUT1.
4, 7, 14, 25
GND
Power Supply
Negative Supply Voltage, Connected to Ground
All VDD, VDDPx and GND Pins must be externally connected to appropriate power supply to guarantee proper operation.
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2
NB4N7132
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pullup Resistor
ESD Protection
96 kꢀ
Human Body Model
Machine Model
> 1 kV
> 100 V
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Level 3
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
268 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Min
0.5
Max
Unit
V
V
DD
V
INP
V
INT
Positive Power Supply
Input Voltage, PECL
Input Voltage, TTL
4.0
-0.5
V
V
+ 0.5
V
DD
DD
-0.5
+ 0.5
V
I
Output HIGH current, PECL
-50
+50
mA
°C
°C
°C
OUT
T
Case temperature under bias
Operating Temperature Range
Storage Temperature Range
-55
+125
+85
C
TA
T
-40
-65
+150
stg
ꢁ
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
TSSOP-28
76
60
°C/W
°C/W
JA
ꢁ
Thermal Resistance (Junction-to-Case)
Wave Solder
(Note 2)
TSSOP-28
25
°C/W
°C
JC
T
sol
Pb-Free
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
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3
NB4N7132
Table 5. DC CHARACTERISTICS V = 3.30 V $5%, GND = 0 V; T = -40°C to +85°C
DD
A
Symbol
Characteristic
Min
Typ
Max
3.47
125
450
Unit
V
V
Power Supply Voltage, 3.30 V $5%
Power Supply Current (Outputs open)
3.14
DD
I
105
mA
mW
mV
DD
P
D
Power Dissipation; Outputs Open; V = V
DD DDmax
ꢂ V
Receiver Differential Voltage Amplitude; (IN, IN0, IN1), AC-Coupled,
Internally Biased to 1.2 V; Differential Measurement - (V - V
IN
)
)
)
300
2600
2200
INn+
INn-
ꢂ V
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 50 ꢀ to V – 2.0 V
mV
mV
OUT50
1000
DD
Differential Measurement - (V
- V
OUTn-
OUTn+
ꢂ V
Output Differential Voltage Swing, peak-peak; (OUT, OUT0, OUT1)
Outputs loaded / terminated with 75 ꢀ to V – 2.0 V
- V
OUT75
DD
Differential Measurement - (V
1200
2200
OUTn+
OUTn-
LVCMOS/LVTTL INPUTS
V
IH
V
IL
Input HIGH Voltage, TTL
Input LOW Voltage, TTL
2.0
0
V
DD
+ 0.5
V
V
0.8
I
Input HIGH Current, TTL; V = 2.4 V
IN
100
ꢃ A
ꢃ A
IH
IL
I
Input LOW Current, TTL; V = 0.5 V
IN
-100
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS V = 3.3 V $5%, GND = 0 V -40°C to +85°C
DD
Symbol
Characteristic
Min
Typ
Max
1.5
175
4.0
40
Unit
Gb/s
ps
f
Input / Output Frequency Range
1.0
IN / OUT
tr/tf
Output rise and Fall Times (Note 3)
Propagation Delay, IN to OUT
140
t
0.375
ns
PD
T
DJ
Deterministic Jitter Added to Serial Input Up to 1.5 Gb/s;
K28.5$ Pattern
ps pk-pk
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measured 20% to 80%
IN+/-
IN0+/-
IN1+/-
OUT+/-
OUT0+/-
OUT1+/-
t
pd
t
pd
t
J
Figure 4. Timing Waveforms
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4
NB4N7132
0.01ꢃ F
0.01ꢃ F
0.01ꢃ F
0.01ꢃ F
TX+
TX-
I+
I-
O1+
O1-
I1+
I1-
O+
O-
RX+
RX-
R
RT
RT
RT
0.01ꢃ F
0.01ꢃ F
R
SerDes
NB4N7132
NB4N7132
SerDes
0.01ꢃ F
0.01ꢃ F
0.01ꢃ F
0.01ꢃ F
RX+
RX-
O+
O-
I1+
I1-
O1+
O1-
I+
I-
TX+
TX-
R
R
RT
RT
RT
0.01ꢃ F
0.01ꢃ F
“R” is 150 ꢀ for both 100 ꢀ differential or 150 ꢀ differential traces.
“RT” matches the differential impedance of the link.
Figure 5. NB4N7132 Application Interface Example
OEx Output Enable
IN+/IN- Input Functionality
The differential inputs are internally biased to Y1.2 V. In
The NB4N7132 incorporates output enable pins, OE0 and
OE1, that work by powering down the output buffer and
associated driving circuitry. Using this approach results in
a
typical application, the differential inputs are
capacitor-coupled and will swing symmetrically above and
below 1.2 V, preserving a 50% duty cycle to the outputs.
With this technique, the NB4N7132 will accept any
differential input allowing for LVPECL, CML, LVDS, and
HSTL input levels.
both differential outputs going HIGH, and a reduction in I
current of approx. 29 mA for each disabled output pair.
DD
When OEx is LOW, outputs are disabled, OUTx+ and
OUTx- are set HIGH.
OUT+ / OUT- Outputs
Power Supply Bypass information
The OUT+ and OUT- outputs of the NB4N7132 are
designed to drive differential transmission lines with
nominally 50 ꢀ or 75 ꢀ characteristic impedance. These
differential output buffers utilize positive emitter coupled
logic (PECL) architecture, but they do not require DC output
load resistors, and will operate properly with or without the
resistors.
A clean power supply will optimize the performance of
the device. The NB4N7132 provides separate power supply
pins for the digital circuitry (V ) and LVPECL outputs
DD
(VDDPn). Placing a bypass capacitor of 0.01 ꢃ F to 0.1 ꢃ F
on each VDD pin will help ensure a noise free V power
DD
supply. The purpose of this design technique is to try and
isolate the high switching noise of the digital outputs from
the relatively sensitive digital core logic.
Resource Reference of Application Notes
AND8002
AND8009
-
-
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
ORDERING INFORMATION
Device
†
Package
Shipping
NB4N7132DTG
TSSOP-28
(Pb-Free)
50 Units / Rail
NB4N7132DTR2G
TSSOP-28
(Pb-Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NB4N7132
PACKAGE DIMENSIONS
28 LEAD TSSOP
DT SUFFIX
CASE 948AA-01
ISSUE O
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
e
B
28
15
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DETAIL A
E1 E
PIN ONE
LOCATION
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
2X
MILLIMETERS
1
14
DIM MIN
---
MAX
1.20
0.15
1.05
0.30
0.25
0.20
0.16
9.80
0.20 C B A
A
A1 0.05
A2 0.80
A
A
0.05
b
0.19
b1 0.19
A2
A
A
D
c
c1
D
0.09
0.09
9.60
0.10
C
SEATING
PLANE
E 6.40 BSC
E1 4.30
4.50
e
L
L1
R
0.65 BSC
A1
28X
b
0.45
0.75
C
1.00 REF
0.10 C B A
0.09
---
---
---
8
R1 0.09
S
01
02
03
02
0.20
0
S
_
_
H
12 REF
_
(b)
b1
R1
12 REF
_
R
c
c1
GAUGE PLANE
L
0.25
(L1)
SECTION A-A
01
03
DETAIL A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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PUBLICATION ORDERING INFORMATION
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NB4N7132/D
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