NB6L11SMNR2G [ONSEMI]
2.5 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer / Translator; 2.5 V 1 ： 2 AnyLevel TM输入到LVDS扇出缓冲器/翻译
| 型号： | NB6L11SMNR2G |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer / Translator |
| 文件： | 总10页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB6L11S
2.5 V 1:2 AnyLevelt Input
to LVDS Fanout Buffer /
Translator
The NB6L11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevelt input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to LVDS and two
identical copies of Clock or Data will be distributed, operating up to
2.0 GHz or 2.5 Gb/s, respectively. As such, the NB6L11S is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock or Data
distribution applications.
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MARKING
DIAGRAM*
16
1
The NB6L11S has a wide input common mode range from
NB6L
11S
1
GND + 50 mV to V − 50 mV. Combined with the 50 W internal
CC
termination resistors at the inputs, the NB6L11S is ideal for translating
a variety of differential or single−ended Clock or Data signals to
350 mV typical LVDS output levels.
ALYW G
QFN−16
MN SUFFIX
CASE 485G
G
The NB6L11S is the 2.5 V version of the NB6N11S and is offered in
a small 3 mm X 3 mm 16−QFN package. Application notes, models,
and support documentation are available at www.onsemi.com.
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
Features
• Maximum Input Clock Frequency > 2.0 GHz
• Maximum Input Data Rate > 2.5 Gb/s
• 1 ps Maximum of RMS Clock Jitter
• Typically 10 ps of Data Dependent Jitter
• 380 ps Typical Propagation Delay
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
• 120 ps Typical Rise and Fall Times
V
V
• Single Power Supply; V = 2.5 V " 5%
Q0
TD
CC
• These are Pb−Free Devices
D
D
TD
Q1
Q1
Figure 1. Logic Diagram
Device DDJ = 10 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
September, 2006 − Rev. 2
NB6L11S/D
NB6L11S
Exposed Pad (EP)
V
V
V
V
CC CC
CC
CC
16
15
14
13
Q0
1
2
3
4
12
11
10
9
V
TD
Q0
Q1
D
D
NB6L11S
Q1
V
TD
5
6
7
8
V
NC
V
V
EE
CC
EE
Figure 3. NB6L11S Pinout, 16−pin QFN (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q0
LVDS Output
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
3
4
Q0
Q1
Q1
LVDS Output
LVDS Output
LVDS Output
−
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
6
V
Positive Supply Voltage.
CC
NC
No Connect.
7
V
V
V
Negative Supply Voltage.
EE
EE
TD
8
Negative Supply Voltage.
9
−
Internal 50 W termination pin for D.
Inverted Differential Clock/Data Input (Note 1).
10
D
LVPECL, CML, LVDS,
LVCMOS, LVTTL
11
D
LVPECL, CML, LVDS,
LVCMOS, LVTTL
Non−inverted Differential Clock/Data Input (Note 1).
12
13
14
15
16
EP
V
−
−
−
−
−
Internal 50 W termination pin for D.
Positive Supply Voltage.
Positive Supply Voltage.
Positive Supply Voltage.
Positive Supply Voltage.
TD
CC
CC
CC
CC
V
V
V
V
Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to V
.
EE
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
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2
NB6L11S
Table 2. ATTRIBUTES
Characteristic
Value
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 1 kV
Moisture Sensitivity (Note 2)
Pb−Free Pkg
Level 1
QFN−16
Flammability RatingOxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
225
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Positive Input
Condition 1
GND = 0 V
Condition 2
Rating
3.8
Unit
V
V
V
CC
IN
GND = 0 V
V
≤ V
3.8
V
IN
CC
I
Input Current Through R (50 W Resistor)
Static
Surge
35
70
mA
mA
IN
T
I
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
mA
OSC
Q or Q to GND
Q to Q
Continuous
Continuous
12
24
T
Operating Temperature Range
QFN−16
−40 to +85
°C
°C
A
T
stg
Storage Temperature Range
−65 to +150
Thermal Resistance (Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
q
JA
Thermal Resistance (Junction−to−Case)
1S2P (Note 3)
QFN−16
4.0
°C/W
°C
q
JC
T
sol
Wave Solder
Pb−Free
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB6L11S
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS V = 2.375 V to 2.625 V, GND = 0 V,
CC
T = −40°C to +85°C
A
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Note 8)
30
45
mA
CC
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18)
V
V
V
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
GND +100
V
− 100
CC
mV
mV
mV
th
IH
IL
V
+ 100
V
CC
th
Single−ended Input LOW Voltage
GND
V
− 100
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
V
V
V
V
Differential Input HIGH Voltage
100
V
mV
mV
mV
mV
W
IHD
ILD
CMR
ID
CC
Differential Input LOW Voltage
GND
V
− 100
CC
Input Common Mode Range (Differential Configuration)
GND + 50
100
V
− 50
CC
Differential Input Voltage (V
− V )
ILD
V
IHD
CC
R
Internal Input Termination Resistor
LVDS OUTPUTS (Note 4)
Differential Output Voltage
40
50
1
60
TIN
V
250
0
450
25
mV
mV
mV
mV
mV
mV
OD
DV
Change in Magnitude of V
Offset Voltage (Figure 15)
for Complementary Output States (Note 9)
OD
OD
V
1125
0
1375
25
OS
DV
Change in Magnitude of V for Complementary Output States (Note 9)
1
OS
OS
V
V
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 6)
1425
1075
1600
OH
OL
900
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.
5. V max = V max + ½ V max.
OH
OS
OD
6. V max = V min − ½ V max.
OL
OS
OD
7. V is applied to the complementary input when operating in single−ended mode.
th
8. Input termination pins open, D/D at the DC level within V
and output pins loaded with R = 100 W across differential.
CMR
L
9. Parameter guaranteed by design verification not tested in production.
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4
NB6L11S
Table 5. AC CHARACTERISTICS V = 2.375 V to 2.625 V, GND = 0 V; (Note 10)
CC
−40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
(Figure 4)
) f ≤ 1.0 GHz 220 350
INPPmin in
220 350
200 300
170 270
220 350
200 300
170 270
mV
OUTPP
f = 1.5 GHz 200 300
in
f = 2.0 GHz 170 270
in
f
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
Gb/s
ps
DATA
t
t
,
Differential Input to Differential Output
Propagation Delay
250
450
250
450
250
450
PLH
PHL
t
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
SKEW
t
RMS Random Clock Jitter (Note 13)
f
f
= 1.0 GHz
= 1.5 GHz
0.5
0.5
6
7
10
0.5
0.5
6
7
10
0.5
0.5
6
7
10
JITTER
in
in
ps
Deterministic Jitter (Note 14)
f
f
f
= 622 Mb/s
= 1.5 Gb/s
= 2.488 Gb/s
DATA
DATA
DATA
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100
70
V
GND
−
100
70
V
GND
−
100
70
V
GND
−
mV
ps
INPP
CC
CC
CC
t
t
Output Rise/Fall Times @ 250 MHz
(20% − 80%)
Q, Q
120
170
120
170
120
170
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
with 50% duty cycle clock source and V − 1400 mV offset. All loading with an external R = 100 W across
INPPmin
C
C
L
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of t = |t − t | for a nominal 50% differential clock input waveform @ 250 MHz.
skew
PLH
PHL
12.Input voltage swing is a single−ended measurement operating in differential mode.
13.RMS jitter with 50% Duty Cycle input clock signal.
23
14.Deterministic jitter with input NRZ data at PRBS 2 −1 and K28.5.
15.Skew is measured between outputs under identical transition @ 250 MHz.
16.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
−40°C
250
85°C
200
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
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5
NB6L11S
Device DDJ = 10 ps
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 223−1 and OC48 mask
(VINPP = 100 mV; Input Signal DDJ = 14 ps)
R
C
R
C
1.25 kW
1.25 kW
Dx
1.25 kW
1.25 kW
50 W
50 W
I
V
V
TDx
TDx
D
x
Figure 6. Input Structure
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6
NB6L11S
V
= 3.3 V
V
= 3.3 V
CC
CC
or 2.5 V
or 2.5 V
V
= 2.5 V
V
= 2.5 V
CC
CC
NB6L11S
NB6L11S
D
D
Z = 50 W
o
Z = 50 W
o
50 W*
50 W*
50 W*
50 W*
V
V
V
V
TD
TD
TD
TD
LVPECL
Driver
LVDS
Driver
Z = 50 W
o
Z = 50 W
o
D
D
V
= V
TD
TD
V
= V = V − 2.0 V
TD CC
TD
GND
GND
GND
GND
Figure 7. LVPECL Interface
Figure 8. LVDS Interface
V
= 3.3 V
CC
V
= 2.5 V
V
= 2.5 V
CC
or 2.5 V
CC
V
= 2.5 V
CC
NB6L11S
NB6L11S
D
D
Z = 50 W
o
Z = 50 W
o
V
CC
50 W*
50 W*
V
V
V
V
TD
TD
TD
TD
CML
Driver
HSTL
Driver
50 W*
50 W*
Z = 50 W
o
Z = 50 W
o
D
D
V
= V = V
TD CC
TD
V
= V = GND or V /2
TD DD
TD
Depending on Driver.
GND
GND
GND
GND
Figure 9. Standard 50 W Load CML Interface
Figure 10. HSTL Interface
V
= 2.5 V
V
= 2.5 V
V
= 2.5 V
V
= 2.5 V
CC
CC
CC
CC
NB6L11S
D
NB6L11S
D
Z = 50 W
o
Z = 50 W
o
50 W*
50 W*
V
V
V
V
TD
TD
TD
TD
LVCMOS
Driver
LVTTL
Driver
50 W*
50 W*
D
D
2.5 kW*
1.5 kW*
GND
GND
GND
GND
GND
GND
V
= OPEN
V
= V = OPEN
TD
TD
TD
D = GND
D = GND
Figure 11. LVCMOS Interface
Figure 12. LVTTL Interface
*R , Internal Input Termination Resistor.
TIN
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7
NB6L11S
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 13. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
LVDS
Driver
Device
LVDS
Receiver
Device
100 W
Z = 50 W
o
Figure 14. Typical LVDS Termination for Output Driver and Device Evaluation
Q
Q
V
V
N
N
OH
OL
V
V
OS
OD
Figure 15. LVDS Output
D
D
D
D
V
V
IH
V
IL
th
V
th
Figure 16. Differential Input Driven
Single−Ended
Figure 17. Differential Inputs Driven
Differentially
V
CC
V
V
V
IH(MAX)
IL
V
CC
V
V
IHmax
ILmax
V
thmax
D
D
IH
V
V
= V
− V
IHD ILD
CMR
INPP
V
th
V
IL
V
V
IHmin
ILmin
V
V
V
IH
thmin
GND
IL(MIN)
GND
Figure 18. Vth Diagram
Figure 19. VCMR Diagram
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8
NB6L11S
ORDERING INFORMATION
Device
†
Package
Shipping
NB6L11SMNG
QFN−16, 3 X 3 mm
(Pb−Free)
123 Units / Rail
NB6L11SMNR2G
QFN−16, 3 X 3 mm
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB6L11S
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
E2 1.65
1.85
0.10
0.08
C
C
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
SOLDERING FOOTPRINT*
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
e
L
16X
0.012
EXPOSED PAD
5
8
NOTE 5
4
9
E2
e
1.50
0.059
K
16X
3.25
0.128
12
1
16
13
16X b
0.30
0.012
0.10
0.05
C
C
A
B
BOTTOM VIEW
0.50
0.02
NOTE 3
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
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USA/Canada
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Phone: 421 33 790 2910
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For additional information, please contact your local
Sales Representative
NB6L11S/D
相关型号：
NB6L11_06
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
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