NB7L32M [ONSEMI]
2.5V/3.3V, 14GHz ±2 Clock Divider w/CML Output and Internal Termination; 2.5V / 3.3V ， 14GHz ± 2时钟分频器W / CML输出和内部终端
| 型号： | NB7L32M |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V, 14GHz ±2 Clock Divider w/CML Output and Internal Termination |
| 文件： | 总11页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Descriptions
http://onsemi.com
MARKING
The NB7L32M is an integrated ÷2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50 W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power−up, the internal flip−flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
DIAGRAM*
16
1
NB7L
32M
ALYWG
QFN−16
MN SUFFIX
CASE 485G
externally receiver terminated 50 W to V (See Figure 16).
CC
The device is housed in a small 3x3 mm 16 pin QFN package.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• Maximum Input Clock Frequency 14 GHz Typical
• 200 ps Max Propagation Delay
• 30 ps Typical Rise and Fall Times
*For additional marking information, refer to
Application Note AND8002/D.
• < 0.5 ps Maximum (RMS) Random Clock Jitter
• Operating Range: V = 2.375 V to 3.465 V with V = 0 V
CC
EE
FUNCTIONAL BLOCK DIAGRAM
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
R
V
CC
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
V
R1
EE
EP, and SG Devices
• These are Pb−Free Devices
Reset
VTCLK
50 W
50 W
CLK
CLK
Q
Divide by 2
Q
VTCLK
TRUTH TABLE
CLK
CLK
R
H
L
Q
L
Q
x
x
H
Z
W
÷2
÷2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2005 − Rev. 0
NB7L32M/D
NB7L32M
Exposed Pad (EP)
V
R
V
V
CC
CC
CC
16
15
14
13
VTCLK
CLK
V
CC
1
2
3
4
12
11
10
9
Q
Q
V
NB7L32M
CLK
VTCLK
CC
5
6
7
8
NC
V
V
V
EE
EE
EE
Figure 1. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
−
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open, and if no signal is applied on CLK/CLK input then the device
will be susceptible to self−oscillation.
2
3
4
CLK
CLK
ECL, CML, LVDS Input
ECL, CML, LVDS Input
−
Noninverted differential input. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self−oscillation.
Inverted differential input. In the differential configuration when the input ter-
mination pin (VTCLK, VTCLK) are connected to a common termination voltage
or left open and if no signal is applied on CLK/CLK input, then the device will
be susceptible to self−oscillation.
VTCLK
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self−oscillation.
5
NC
−
−
−
No connect. NC pin must be left open.
Negative supply voltage.
6, 7, 8
V
EE
9, 12, 13,
14, 16
V
Positive supply voltage.
CC
10
11
15
−
Q
Q
CML Output
CML Output
LVTTL/LVCMOS
−
Inverted differential output. Typically terminated with 50 W resistor to V
.
CC
Noninverted differential output. Typically terminated with 50 W resistor to V
.
CC
R
Reset Input. Internal pulldown to 75 kW to V
.
EE
EP
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a heat−sinking conduit. EP is electrically isolated
from V and V
.
EE
CC
http://onsemi.com
2
NB7L32M
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
ESD Protection
R1
75 kW
Human Body Model
Machine Model
> 500 V
> 30 V
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
QFN−16
Level 1
UL 94 V−0 @ 0.125 in
349
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
V
V
3.6
CC
EE
I
EE
CC
Negative Power Supply
= 0 V
−3.6
V
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V ≤ V
3.6
−3.6
V
V
EE
CC
I
I
CC
EE
V ≥ V
V
Differential Input Voltage
2.8
V
INPP
I
Input Current Through R (50 W Resistor)
Static
Surge
45
80
mA
mA
IN
T
I
Output Current
Continuous
Surge
25
50
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
QFN−16
−40 to +85
°C
°C
A
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
QFN−16
QFN−16
41.6
35.2
°C/W
°C/W
JA
(Note 2)
500 lfpm
q
Thermal Resistance (Junction−to−Case)
1S2P
QFN−16
4.0
°C/W
°C
JC
T
sol
Wave Solder
Pb−Free <3 sec @ 260°C
265
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3
NB7L32M
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS V = 2.375 V to 3.465 V, V = 0 V,
CC
EE
T = −40°C to +85°C
A
Symbol
Characteristic
Min
Typ
Max
Unit
mA
I
Power Supply Current (Note 3)
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
50
65
80
CC
V
V
V
− 40
V
− 10
V
mV
OH
OL
CC
CC
CC
V
− 500
V
− 400
V
− 330
CC
mV
CC
CC
R
R
Internal Output Termination Resistor
45
50
55
W
TOUT
Internal I/O Termination Resistor Temperature Coefficient
6.38
mW/°C
Temp
Coef
DIFFERENTIAL CLK/CLK INPUT DRIVEN SINGLE−ENDED (see Figure 10 and 12)
V
V
V
Input Threshold Reference Voltage Range (Note 6)
Single−ended Input HIGH Voltage
1050
+ 150
V
mV
mV
mV
th
IH
IL
CC
V
V
V
+ 300
CC
th
Single−ended Input LOW Voltage
V
V
− 150
EE
th
DIFFERENTIAL CLK/CLK INPUTS DRIVEN DIFFERENTIALLY (see Figure 11 and 13)
V
V
V
V
Differential Input HIGH Voltage
1200
+ 300
mV
mV
mV
mV
IHD
ILD
CMR
ID
CC
Differential Input LOW Voltage
V
V
− 75
CC
EE
Input Common Mode Range (Differential Configuration, Note 7)
1125
150
V
CC
Differential Input Voltage (V
− V )
ILD
2500
IHD
I
I
Input HIGH Current
Input LOW Current
CLK/CLK (VTCLK/R/VTCLK/R Open)
CLK/CLK(VTCLK/R/VTCLK/R Open)
0
30
0
100
50
mA
mA
W
IH
IL
−50
45
R
Internal Input Termination Resistor
50
55
TIN
LVTTL/LVCMOS RESET INPUT
V
V
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Input HIGH Current
2000
V
mV
mV
mA
IH
IL
CC
V
800
100
100
EE
I
I
R
R
0
0
30
10
IH
IL
Input LOW Current
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input termination pins open and all outputs loaded with external R = 50 W receiver termination resistor.
L
4. CML outputs require R = 50 W receiver termination resistors to V for proper operation. (See Figure 9)
L
CC
5. Input and output parameters vary 1:1 with V
.
CC
6. V is applied to the complementary input when operating in single−ended mode.
th
7. V
varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential input
CMR(MIN)
signal.
EE CMR
CC
CMR
http://onsemi.com
4
NB7L32M
Table 6. AC CHARACTERISTICS V = 2.375 V to 3.465 V, V = 0 V (Note 8)
CC
EE
−40°C
255C
Max Min Typ
855C
Typ
Min Typ
Max Min
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
)
INPP(MIN)
mV
OUTPP
f
f
≤ 7 GHz
190 330
160 320
190 330
160 320
190
160
330
320
in
in
(See Figures 2, 3, 4, 5, 6, and 7)
≤ 12 GHz
f
Maximum Input Clock Frequency
(See Figures 2 and 3)
12
14
12
14
12
14
GHz
ps
IN
t
t
,
Propagation Delay to
Output Differential (See Figure 8)
CLK to Q 130 155
R to Q 200 240
200
300
130 155
200 240
200
300
130
200
155
260
200
300
PLH
PHL
t
Duty Cycle Skew (Note 9)
Device−to−Device Skew (Note 12)
2
6
20
50
2
6
20
50
2
6
20
50
skew
t
t
t
Reset Recovery (See Figure 8)
Minimum Pulse Width
300 135
300 135
500 210
300
500
135
210
ps
ps
ps
RR
R
500 210
PW
Random Clock Jitter (RMS)
(Note 11)
f
f
≤ 7 GHz
= 12 GHz
0.13
0.14
0.5
0.5
0.13
0.14
0.5
0.5
0.13
0.14
0.5
0.5
JITTER
in
in
V
Input Voltage Swing/Sensitivity
150
2500 150
2500 150
2500 mV
45 ps
INPP
(Differential Configuration) (Note 10)
t
t
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
30
45
30
45
30
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing V
from a 50% duty cycle clock source. All loading with an external R = 50 W to V . Input edge rates 40 ps
INPP(MIN)
L CC
(20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ 1 GHz.
10.V
cannot exceed V − V . Input voltage swing is a single−ended measurement operating in differential mode.
INPP(MAX)
CC EE
11. Additive RMS jitter with 50% duty cycle input clock signal.
12.Device−to−device skew is measured between outputs under identical transition @ 1 GHz.
http://onsemi.com
5
NB7L32M
450
400
350
300
250
200
150
100
50
V
= 3.3 V
CC
V
= 2.5 V
CC
0
0
2
4
6
8
10
12
14
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fOUT) at
Ambient Temperature (VINPP = 150 mV)
+223.61
+125.74
+70.71
+39.76
+22.36
+12.57
+7.07
0
−5
−10
−15
−20
−25
−30
−35
−40
−45
Safe Operating Area
Typical
+3.98
+2.24
+1.26
0
2
4
6
8
10
12
14
16
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Input Signal Amplitude vs Input Clock Frequency (All Temperatures and Power Supplies;
Guaranteed Output Amplitude of at Least VOUTPP = 160 mV)
http://onsemi.com
6
NB7L32M
TIME (190 ps/div)
TIME (190 ps/div)
Figure 4. Typical Output Waveform with
Figure 5. Typical Output Waveform with
IN = 7 GHz(VCC = 3.3 V, VINPP = 400 mV, Room
Temperature, VOUTPP = 387 mV, tr = 32 ps,
tf = 29.8 ps, fOUT = 3.499 GHz)
f
IN = 7 GHz( VCC = 2.5 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 357 mV,
tr = 33 ps, tf = 30 ps, fOUT = 3.499 GHz)
f
TIME (52 ps/div)
TIME (52 ps/div)
Figure 6. Typical Output Waveform with
Figure 7. Typical Output Waveform with
f
IN = 14 GHz(VCC = 2.5 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 292 mV,
tr = 25 ps, tf = 27 ps, fOUT = 7.01 GHz)
f
IN = 14 GHz(VCC = 3.3 V, VINPP = 400 mV,
Room Temperature, VOUTPP = 319 mV,
tr = 25 ps, tf = 26 ps, fOUT = 7.01 GHz)
50%
50%
V
V
= V (Q) − V (Q)
OH OL
OUTPP
Q
t
t
PHL
PLH
= V (CLK) − V (CLK)
INPP
IH
IL
50%
50%
CLK
t
RR(MIN)
R
50%
Figure 8. AC Reference Measurement (Timing Diagram)
http://onsemi.com
7
NB7L32M
V
CC
50 W
50 W
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8073/D − Termination of CML Logic Devices.)
CLK
CLK
CLK
CLK
V
th
V
th
Figure 10. Differential Input Driven
Figure 11. Differential Inputs Driven
Differentially
Single−Ended
V
V
CC
CC
V
IHDmax
V
V
IHmax
V
V
CMmax
thmax
V
ILDmax
ILmax
V
= V − V
IHD ILD
ID
D
D
V
V
V
V
IH
th
IHDtyp
ILDtyp
IHDmin
V
CMR
V
th
D
V
IL
V
V
V
IHmin
ILmin
V
V
CMmin
thmin
V
ILDmin
GND
GND
NOTE:
V
v V v V + 300 mV; V > V
EE
IN
CC
IH
IL
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
V
CC
50 W
50 W
Q
Q
16 mA
V
EE
Figure 14. CML Output Structure
http://onsemi.com
8
NB7L32M
APPLICATION INFORMATION
All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS,
PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions,
the input voltage can range from V to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).
CC
For output termination and interface, refer to application note AND8020/D.
Table 5. INTERFACING OPTIONS
Interfacing Options
CML
Connections
Connect VTD and VTD to V (See Figure 15)
CC
LVDS
Connect VTD and VTD Together (See Figure 17)
Bias VTD and VTD Inputs within Common Mode Range (V
Standard ECL Termination Techniques (See Figure 9)
AC−COUPLED
RSECL, PECL, NECL
) (See Figure 16)
CMR
V
V
CC
CC
50 W 50 W
Z = 50 W
Z = 50 W
Q
Q
D
50 W
50 W
VTD
NB7L32M
CML
Driver
V
V
CC
CC
VTD
D
V
V
EE
EE
CC
Figure 15. CML to NB7L32M Interface
V
V
CC
C
Z = 50 W
Z = 50 W
D
50 W
50 W
VTD
V
*
PECL
Driver
Bias
NB7L32M
V
*
Bias
VTD
D
Recommended R Values
C
T
V
R
T
CC
R
T
R
T
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
V
V
V
EE
EE
EE
*V
must be within common mode range limits (V
)
CMR
Bias
Figure 16. PECL to NB7L32M Interface
http://onsemi.com
9
NB7L32M
APPLICATION INFORMATION
V
V
CC
CC
Z = 50 W
D
50 W
50 W
VTD
LVDS
Driver
NB7L32M
VTD
Z = 50 W
D
V
V
EE
EE
Figure 17. LVDS to NB7L32M Interface
Package
ORDERING INFORMATION
Device
†
Shipping
NB7L32MMNG
QFN−16
(Pb−Free)
123 Units / Rail
NB7L32MMNR2G
QFN−16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
10
NB7L32M
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE B
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
E
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
TOP VIEW
A3
b
0.20 REF
0.18
0.15
C
0.30
D
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
1.85
0.50 BSC
(A3)
E2 1.65
0.10
0.08
C
C
e
K
L
0.20
0.30
−−−
0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
C
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
E2
e
16X K
12
1
16
13
16X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NB7L32M/D
相关型号：
NB7L572MNG
2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator
ONSEMI
NB7L572MNR4G
2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator
ONSEMI
NB7L585
2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator
ONSEMI
NB7L585MNG
2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator
ONSEMI
NB7L585MNR4G
2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator
ONSEMI
NB7L585MNTWG
2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer Translator
ONSEMI
NB7L585R
2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
ONSEMI
NB7L585RMNG
2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
ONSEMI
NB7L585RMNR4G
2.5V/3.3V, 7GHz/10Gbps Differential 2:1 Mux Input to 1:6 RSECL Clock/Data Fanout Buffer / Translator
ONSEMI
©2020 ICPDF网 联系我们和版权申明