NB7NPQ7041M [ONSEMI]
3.3V USB 3.1 Quad Channel / Dual Port Linear Redriver;
| 型号： | NB7NPQ7041M |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V USB 3.1 Quad Channel / Dual Port Linear Redriver |
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7NPQ7041M
3.3 V USB 3.1 Quad
Channel / Dual Port Linear
Redriver
Description
The NB7NPQ7041M is a 3.3 V quad channel / dual port linear
redriver suitable for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications
that supports both 5 Gbps and 10 Gbps data rates. Signal integrity
degrades from PCB traces, transmission cables, and inter−symbol
interference (ISI). The NB7NPQ7041M compensates for these losses
by engaging varying levels of equalization at the input receiver, and flat
gain amplification on the output transmitter. The Flat Gain and
Equalization are controlled by four level control pins. Each channel has
a set of independent control pins to make signal optimization possible.
After power up, the NB7NPQ7041M periodically checks both of the
TX output pairs of each port for a receiver connection. When the receiver
is detected on both channels, the RX termination becomes enabled of
that respective port and is set to perform the redriver function.
The port becomes active once both TX outputs have detected
50−ohm termination, and the NB7NPQ7041M is set to perform the
redriver function. Port AB (channels A & B) and port CD (channels C
& D) are independent of each other.
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MARKING
DIAGRAM
7NPQ
7041
ALYWG
G
1
X2QFN34
CASE 722AL
7NPQ7041 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
The NB7NPQ7041M comes in a small 3.1 x 4.3 mm X2QFN34
package and is specified to operate across the entire industrial
temperature range, –40°C to 85°C.
ORDERING INFORMATION
†
Device
Package Shipping
Features
• 3.3 V 5% Power Supply
NB7NPQ7041MMUTWG X2QFN34
3000 /
(Pb−Free) Tape & Reel
• Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Termination Detection
• Integrated Input and Output Termination
• Independent, Selectable Equalization and Flat Gain
• Hot−Plug Capable
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Flow−through Design for Ease of PCB Layout
• ESD Protection: 4 kV HBM
• Operating Temperature Range: −40°C to 85°C
• Small 3.1 x 4.3 x 0.35 mm X2QFN34 Package
• This is a Pb−Free Device
Typical Applications
• USB3.1 Type−C and Type−A Signal Routing
• Mobile Phone and Tablet
• Computer and Laptop
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V., Set−Top Boxes
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2018 − Rev. 1
NB7NPQ7041M/D
NB7NPQ7041M
CTRL_A1
CTRL_A0
A_RX−
A_RX+
B_TX−
1
2
34
A_TX−
A_TX+
33
32
31
30
29
28
27
A_TX -
A_TX+
A_RX
-
Receiver/
Equalizer
Driver
A_RX+
26 B_RX−
25 B_RX+
3
B_TX-
B_RX-
B_RX+
Receiver/
Equalizer
Driver
4
B_TX+
B_TX+
VCC
5
CTRL_B1
24
23
22
CTRL_B1
CTRL_B0
6
CTRL_C0
CTRL_C1
C_RX−
C_RX+
D_TX−
D_TX+
CTRL_B0
VCC
GND
CTRL_C0
CTRL_C1
7
8
21 C_TX−
C_TX+
19 D_RX−
18
-
C_TX-
C_TX+
C_RX
Receiver/
Equalizer
9
20
Driver
C_RX+
10
11
D_TX-
D_RX-
Receiver/
Equalizer
12
13
14
15
16
17
D_RX+
Driver
D_TX+
D_RX+
CTRL_D1
CTRL_D0
Figure 1. Logic Diagram of NB7NPQ7041M
Figure 2. X2QFN34 Package Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
1
2
3
4
5
A_RX−
A_RX+
B_TX−
B_TX+
VCC
DIFF IN
Channel A Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
DIFF OUT
Power
Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
3.3V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
6
7
CTRL_C0
CTRL_C1
LVCMOS IN Control pin “C0” for equalization and flat gain on Channel C. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
LVCMOS IN Control pin “C1” for equalization and flat gain on Channel C. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
8
C_RX−
C_RX+
D_TX−
D_TX+
NC
DIFF IN
Channel C Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
No Connect
9
10
11
12
13
DIFF OUT
VCC
Power
3.3V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
14
CTRL_D0
LVCMOS IN Control pin “D0” for equalization and flat gain on Channel D. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
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2
NB7NPQ7041M
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
15
CTRL_D1
LVCMOS IN Control pin “D1” for equalization and flat gain on Channel D. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
16
GND
GND
Reference Ground. GND pins must be externally connected to power supply to guarantee
proper operation.
17
18
19
20
21
22
NC
No Connect
D_ RX+
D_RX−
C_TX+
C_TX−
VCC
DIFF OUT
DIFF OUT
Power
Channel D Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
3.3V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
23
24
CTRL_B0
CTRL_B1
LVCMOS IN Control pin “B0” for equalization and flat gain on Channel B. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
LVCMOS IN Control pin “B1” for equalization and flat gain on Channel B. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
25
26
27
28
29
30
B_ RX+
B_RX−
A_TX+
A_TX−
NC
DIFF OUT
Channel B Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
No Connect
DIFF OUT
VCC
Power
3.3V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
31
32
33
CTRL_A0
CTRL_A1
GND
LVCMOS IN Control pin “A0” for equalization and flat gain on Channel A. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
LVCMOS IN Control pin “A1” for equalization and flat gain on Channel A. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
GND
Reference Ground. GND pins must be externally connected to power supply to guarantee
proper operation.
34
NC
No Connect
EP
GND
GND
Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved
heat transfer out of the package. The pad is not electrically connected to the die, but is recom-
mended to be soldered to GND on the PC Board.
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3
NB7NPQ7041M
DEVICE CONFIGURATION
Table 2. CONTROL PIN EFFECTS (Typical Values)
Channel A, Channel C
CTRL_A1 / C1 CTRL_A0 / C0
Channel B, Channel D
EQ
CTRL_B0 / D0 Equalization (dB)
FG
CTRL_B1 / D1
Flat Gain (dB)
Setting #
1
L
L
L
L
L
R
F
H
L
5
7
0
0
2
L
L
R
F
H
L
3
L
8
0
4
L
L
9
0
5
R
R
R
R
F
F
F
F
H
H
H
H
R
R
R
R
F
F
F
F
H
H
H
H
10
3
0
6
R
F
H
L
R
F
H
L
2
7
4
2
8
5
2
9
7
2
10
R
F
H
L
R
F
H
L
8
2
11 (Default)
8
−1
−1
−1
−1
−1
−1
12
13
14
15
16
5
7
R
F
H
R
F
H
9
11
7
NOTE: Equalization and DC Flat Gain may be set by adjusting the voltage to the control pins. There are 4 specific levels, High “H”, Low
“L”, Rexternal “R” and Float “F”. See Table 7 for voltage levels.
Table 3. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
≤ 4 kV
≤ 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
40,660
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. For additional information, see Application Note AND8003/D.
Table 4. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
−0.5
−0.5
−0.5
−65
Max
4.6
Unit
V
Supply Voltage (Note 2)
V
CC
Voltage range at any input or output terminal
Differential I/O
1.89
V
LVCMOS inputs
V
+ 0.5
V
CC
Storage Temperature Range, T
150
125
85
°C
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Operating Ambient Temperature Range, T
−40
A
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
34
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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4
NB7NPQ7041M
Table 5. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.135
−40
Nom
Max
3.465
+85
Unit
V
V
CC
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor (TX)
°C
nF
C
75
100
265
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. POWER SUPPLY CHARACTERISTICS
Typ
(Note 4)
Parameter
Test Conditions
Min
Max
Unit
mA
mA
mA
Active
Link in U0 with Super Speed Plus data transmission
Link in U2 or U3 power saving state
260
I
CC
U2/U3
2
No USB Connection
4. TYP values use V = 3.3 V, T = 25°C
No connection state, termination disabled
560
CC
A
Table 7. LVCMOS CONTROL PIN CHARACTERISTICS 4−State LVCMOS Inputs (CTRL_A0, CTRL_A1, CTRL_B0, CTRL_B1)
Parameter
Test Conditions
Min
Typ
Max
0.1*V
Unit
V
V
IL
DC Input Setting “L”
DC Input Setting “R”
Input pin connected to GND
GND
CC
V
A specified resistor must be applied 0.23*V 0.33*V 0.43*V
V
IR
CC
CC
CC
between pin and GND
Input pin is left floating
Input pin connected to V
V
DC Input Setting “F”
0.56*V 0.66*V 0.76*V
V
IF
CC
CC
CC
V
IH
DC Input Setting “H”
V
CC
V
CC
R
R
Internal pull−up resistance
Internal pull−down resistance
High−level input current
Low−level input current
100
200
kW
kW
mA
mA
kW
PU
PD
IH
I
V
V
= 3.465 V, V = 3.465 V
25
IN
CC
I
= GND, V = 3.465 V
−45
IL
IN
CC
R
External Resistor for input setting “R”
68
ext
5. Floating refers to a pin left in an open state, with no external connections.
Table 8. RECEIVER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Input differential voltage swing
AC−coupled, peak−to−peak
100
1200
mV
PP
RX−DIFF−pp
V
Common−mode voltage bias in the
receiver (DC)
V
CC
V
RX−CM
Z
Differential input resistance (DC)
Present after an USB device is
detected on TX+/TX−
80
20
100
25
120
30
W
RX−DIFF
Z
Common−mode input resistance (DC) Present after an USB device is
detected on TX+/TX−
W
RX−CM
Z
Common−mode input resistance
with termination disabled (DC)
Present when no USB device is
detected on TX+
25
190
200
kW
RX−HIGH−IMP
V
Low Frequency Periodic Signaling
(LFPS) Detect Threshold
Output voltage is considered
squelched below this threshold
voltage.
100
300
mV
PP
TH−LFPS−pp
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
NB7NPQ7041M
Table 9. TRANSMITTER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
−1 dB compression point Output
swing at 100 MHz
100 MHz Sinewave Input
1200
mV
sw_100M
PPd
V
−1 dB compression point Output
swing at 5 GHz
5 GHz Sinewave Input
At 2.5 GHz
900
mV
sw_5G
PPd
C
TX input capacitance to GND
1.25
100
pF
TX
Z
Differential output impedance (DC)
Present after an USB device is
detected on TX+/TX−
80
20
120
30
W
TX−DIFF
Z
Common−mode output impedance
(DC)
Present after an USB device is
detected on TX+/TX−
25
40
W
TX−CM
I
TX short circuit current
TX+ or TX− shorted to GND
100 mV, 50 MHz, 5 Gbps and
mA
V
TX−SC
V
Common−mode voltage bias in the
transmitter (DC)
V
−0.8
V
CC
TX−CM
CC
7
10 Gbps, PRBS 2
V
AC common−mode peak−to−peak
voltage swing in active mode
Within U0 and at 50 MHz (LFPS)
Tested with a high−pass filter
100
10
mV
TX−CM−ACpp
PP
V
Differential voltage swing during
electrical idle
0
mV
TX−IDLE−DIFF−ACpp
PP
V
Voltage change to allow receiver
detect
The change in voltage that triggers
detection of a receiver.
325
600
mV
TX−RXDET
t , t
Output rise, fall time
20% − 80% of differential
voltage measured 1 inch from
the output pin,
35
ps
ps
R
F
t
Output rise, Fall time mismatch
20% − 80% of differential
voltage measured 1 inch from
the output pin
10
RF−MM
t
, t
Differential propagation delay
Idle exit time
Propagation delay between
50% level at input and output
110
10
ps
ns
ps
diff−LH diff−HL
t
50 MHz clock signal, EQ an FG
setting “11 (Default)”
idleExit
t
Idle entry time
50 MHz clock signal, EQ an FG
setting “11 (Default)”
60
idleEntry
Table 10. TIMING AND JITTER CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Unit
TIMING
t
Time from power applied until RX
termination is enabled
Apply 0 V to V , connect USB ter-
mination to TX , apply 3.3 V to
110
ms
READY
CC
V
CC
, and measure when Z
RX−DIFF
is enabled
JITTER FOR 5 Gbps
T
Total jitter (Notes 6, 7)
Deterministic jitter (Note 7)
Random jitter (Note 7)
EQ = 5 dB, FG = 0 dB,
EQ and FG Setting “LL”
0.20
0.10
0.07
UI
UI
UI
JTX−EYE
D
R
JTX
JTX
JITTER FOR 10 Gbps
T
Total jitter (Notes 6, 7)
Deterministic jitter (Note 7)
Random jitter (Note 7)
EQ = 5 dB, FG = 0 dB,
EQ and FG Setting “LL”
0.22
0.08
0.06
UI
UI
UI
JTX−EYE
D
R
JTX
JTX
−12
6. Includes RJ at 10
.
7. Measured at the ends of reference channel with a K28.5 pattern, VID = 1000 mVpp, −3.5 dB de−emphasis from source.
8. 5 Gbps, UI = 200 ps for 10 Gbps, UI = 100 ps
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6
NB7NPQ7041M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
Rx+
V
OH
80%
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
APPLICATION GUIDELINES
LFPS Compliance Testing
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low Setting
“L” is set by pulling the control pin to ground. Likewise the
high setting “H” is set by pulling the pin high to VCC. The
Rexternal setting can be set by adding a 68−K resistor from the
control pin to ground. This will bias the Redriver internal
voltage to 33% of VCC.
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ7041M is tested as a part of a USB
compliant system to ensure that it maintains compliance
while increasing system performance.
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling.
Linear Equalization
The linear equalization that the NB7NPQ7041M provides
compensates for losses that occur naturally along board
traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 3 dB of flat gain.
Control Pin Settings
Control pins A1, A0, B1, and B0 control the Flat Gain and
the Equalization of channels A and B and control pins C1,
C0, D1, and D0 control the Flat Gain and the Equalization
of channels C and D of the NB7NPQ7041M Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
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7
NB7NPQ7041M
NB7NPQ7041M
Up to 11 inches of FR4
Up to 3 inches of FR4
A RX
A TX
100nF
100nF
100nF
100nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
ESD
Protection
100nF
100nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
B TX
B RX
C RX
C TX
100nF
100nF
100nF
100nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
ESD
Protection
100nF
100nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
D TX
D RX
Figure 5. Typical Application
Table 11. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.135 V to 3.465 V)
Operation Mode (Control Pin Selection)
AC Coupling Capacitors (TX)
Floating by Default, adjust for application losses See Table 2
100 nF nominal, 75 nF to 265 nF, see Figure 5
68 kW, 10%
R
external
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 KW to 220 KW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7021M
Trace loss of FR4 after NB7NPQ7021M
Linear Range at 5 GHz
Up to 11 inches
Up To 3 inches. Keep as short as possible for best performance.
900 mV differential
−1 dB, 0 dB, 2 dB
3 to 11 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W 10%
9. Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
Typical Layout Practices
• RX and TX differential pairs should always be placed
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
and routed on the same layer directly above a ground
plane. This will help reduce EMI and noise on the data
lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• Traces should be routed as straight and symmetric as
possible.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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8
NB7NPQ7041M
PACKAGE DIMENSIONS
X2QFN34 3.1x4.3, 0.4P
CASE 722AL
ISSUE O
NOTES:
B
E
A
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.20 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE PLATED TERMINALS.
L
PIN ONE
REFERENCE
L1
DETAIL A
MILLIMETERS
DIM MIN
NOM
0.35
−−−
0.17
3.10
1.90
4.30
3.10
MAX
0.40
0.05
0.22
3.20
2.00
4.40
3.20
A
A1
b
D
D1
E
E1
e
K
L
L1
0.30
−−−
0.12
3.00
1.80
4.20
3.00
MOLD
COMPOUND
0.40 BSC
0.35 REF
0.25
TOP VIEW
A
C
DETAIL B
0.20
0.30
0.10
C
C
DETAIL B
0.05 REF
0.08
A1
SEATING
PLANE
NOTE 4
RECOMMENDED
SOLDERING FOOTPRINT
3.16
SIDE VIEW
D1
34X L
DETAIL A
2.00
34X
0.31
11
18
34
1
E1
4.36
3.20
PACKAGE
OUTLINE
e
1
28
34
K
b
34X
0.22
34X
0.40
PITCH
e
0.10 C A
B
DIMENSIONS: MILLIMETERS
0.05 C
NOTE 3
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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