NBC12429_技术文档

NBC12429

3.3V/5VꢀProgrammable PLL

Synthesized Clock

Generator

25 MHz to 400 MHz

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MARKING

The NBC12429 is a general purpose, PLL based synthesized clock

source. The VCO will operate over a frequency range of 200 MHz to

400 MHz. The VCO frequency is sent to the N-output divider, where

it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO

and output frequency can be programmed using the parallel or serial

interfaces to the configuration logic. Output frequency steps of

1.0 MHz can be achieved using a 16 MHz crystal, depending on the

output dividers. The PLL loop filter is fully integrated and does not

require any external components.

DIAGRAMS

1 28

NBC12429

AWLYYWW

PLCC-28

FN SUFFIX

CASE 776

• Best-in-Class Output Jitter Performance, ±20 ps Peak-to-Peak

• 25 MHz to 400 MHz Programmable Differential PECL Outputs

• Fully Integrated Phase-Lock-Loop with Internal Loop Filter

• Parallel Interface for Programming Counter and Output Dividers

During Power-Up

• Minimal Frequency Overshoot

• Serial 3-Wire Programming Interface

• Crystal Oscillator Interface

NBC12429

AWLYYWW

LQFP-32

FA SUFFIX

CASE 873A

32

• Operating Range: V = 3.135 V to 5.25 V

CC

1

• CMOS and TTL Compatible Control Inputs

• Drop-in Replacement for Motorola MC12429

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

ORDERING INFORMATION

Device

Package

Shipping

NBC12429FN

PLCC-28

37 Units/Rail

NBC12429FNR2

NBC12429FA

PLCC-28

LQFP-32

500 Tape & Reel

250 Units/Tray

NBC12429FAR2

2000 Tape & Reel

Semiconductor Components Industries, LLC, 2003

1

Publication Order Number:

January, 2003 - Rev. 2

NBC12429/D

NBC12429

+3.3 or 5.0 V

1

PLL_V

CC

1 MHz

F

REF

PHASE

B 16

DETECTOR

+3.3 or 5.0 V

21, 25

VCO

V

CC

4

XTAL1

OSC

24

23

F

9-BIT B M

COUNTER

B N

(1, 2, 4, 8)

OUT

10-20 MHz

F

OUT

200-400

MHz

5

6

XTAL2

20

TEST

OE

LATCH

28

7

S_LOAD

P_LOAD

LATCH

0

1

0

1

27

26

S_DATA

2- BIT SR

3- BIT SR

22, 19

9- BIT SR

S_CLOCK

8 → 16

17, 18

9

2

M[8:0]

N[1:0]

Figure 1. NBC12429 Block Diagram (28-Lead PLCC)

25

24

23

22

21

20

19

18

17

16

15

14

13

12

26

27

28

1

S_CLOCK

S_DATA

N[1]

N[0]

M[8]

M[7]

M[6]

M[5]

M[4]

32 31 30 29 28 27 26 25

24

23

22

21

20

19

18

17

N/C

1

2

3

4

5

6

7

8

S_CLOCK

S_DATA

N[1]

N[0]

M[8]

S_LOAD

PLL_V

CC

PLL_V

M[7]

M[6]

M[5]

M[4]

CC

2

NC

N/C

3

XTAL1

4

XTAL1

9

10 11 12 13 14 15 16

5

6

7

8

9

10

11

Figure 2. 28-Lead PLCC (Top View)

Figure 3. 32-Lead LQFP (Top View)

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2

NBC12429

The following gives a brief description of the functionality of the NBC12429 Inputs and Outputs. Unless explicitly stated,

all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two

series terminated 50 W transmission lines on the incident edge.

PIN FUNCTION DESCRIPTION

Pin Name

INPUTS

XTAL1, XTAL2 Crystal Inputs

Function

Description

These pins form an oscillator when connected to an external series-resonant

crystal.

S_LOAD*

CMOS/TTL Serial Latch Input

(Internal Pulldown Resistor)

This pin loads the configuration latches with the contents of the shift registers. The

latches will be transparent when this signal is HIGH; thus, the data must be stable

on the HIGH-to-LOW transition of S_LOAD for proper operation.

S_DATA*

CMOS/TTL Serial Data Input

(Internal Pulldown Resistor)

This pin acts as the data input to the serial configuration shift registers.

S_CLOCK*

P_LOAD**

CMOS/TTL Serial Clock Input

(Internal Pulldown Resistor)

This pin serves to clock the serial configuration shift registers. Data from S_DATA

is sampled on the rising edge.

CMOS/TTL Parallel Latch Input

(Internal Pullup Resistor)

This pin loads the configuration latches with the contents of the parallel inputs

.The latches will be transparent when this signal is LOW; therefore, the parallel

data must be stable on the LOW-to-HIGH transition of P_LOAD for proper opera-

tion.

M[8:0]**

N[1:0]**

OE**

CMOS/TTL PLL Loop Divider

Inputs (Internal Pullup Resistor)

These pins are used to configure the PLL loop divider. They are sampled on the

LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.

CMOS/TTL Output Divider Inputs

(Internal Pullup Resistor)

These pins are used to configure the output divider modulus. They are sampled

on the LOW-to-HIGH transition of P_LOAD.

CMOS/TTL Output Enable Input

(Internal Pullup Resistor)

Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of

runt pulse generation on the FOUT output.

OUTPUTS

F

, F

PECL Differential Outputs

CMOS/TTL Output

These differential, positive-referenced ECL signals (PECL) are the outputs of the

synthesizer.

OUT OUT

TEST

The function of this output is determined by the serial configuration bits T[2:0].

POWER

V

CC

Positive Supply for the Logic

The positive supply for the internal logic and output buffer of the chip, and is con-

nected to +3.3 V or +5.0 V.

PLL_V

GND

Positive Supply for the PLL

Negative Power Supply

This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.

CC

These pins are the negative supply for the chip and are normally all connected to

ground.

*

When left Open, these inputs will default LOW.

** When left Open, these inputs will default HIGH.

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3

NBC12429

ATTRIBUTES

Characteristics

Value

75 kW

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

37.5 kW

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 1 kV

Moisture Sensitivity (Note 1)

PLCC

LQFP

Level 1

Level 2

Flammability Rating

Transistor Count

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

2035

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MAXIMUM RATINGS (Note 2)

Symbol Parameter

Condition 1

GND = 0 V

Condition 2

Rating

Unit

V

CC

V

I

Positive Supply

Input Voltage

-

6

GND = 0 V

V ꢀ V

V

I

CC

I

Output Current

Continuous

Surge

-

50

mA

out

100

TA

Operating Temperature Range

-

0 to +70

°C

T

stg

Storage Temperature Range

-65 to +150

q

Thermal Resistance (Junction-to-Ambient)

0 LFPM

28 PLCC

63.5

43.5

°C/W

JA

500 LFPM

q

Thermal Resistance (Junction-to-Case)

Thermal Resistance (Junction-to-Ambient)

std bd

28 PLCC

22 to 26

°C/W

JC

JA

0 LFPM

32 LQFP

80

55

°C/W

500 LFPM

q

Thermal Resistance (Junction-to-Case)

Wave Solder

std bd

32 LQFP

-

12 to 17

265

°C/W

°C

JC

T

sol

< 2 to 3 sec @ 248°C

2. Maximum Ratings are those values beyond which device damage may occur.

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4

NBC12429

DC CHARACTERISTICS (V = 3.3 V ± 5%)

CC

0°C

25°C

Typ

-

70°C

Typ

-

Min

Typ

Max

Min

Max

Min

Max

Symbol

Characteristic

Condition

Unit

V

Input HIGH Voltage

V

= 3.3 V

2.0

-

2.0

-

2.0

-

V

IH

CC

LVCMOS/

LVTTL

V

IL

Input LOW Voltage

= 3.3 V

-

0.8

-

0.8

-

0.8

V

CC

LVCMOS/

LVTTL

I

Input Current

-

1.0

-

1.0

-

1.0

-

mA

V

IN

V

Output HIGH Voltage

I

= -0.8 mA

2.5

OH

OL

OH

TEST

Output LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Power Supply Current

= 0.8 mA

-

0.4

-

0.4

-

0.4

V

OL

F

OUT

F

OUT

V

= 3.3 V

2.155

1.355

2.405 2.155

1.605 1.355

2.405 2.155

1.605 1.355

2.405

1.605

CC

PECL

(Notes 3, 4)

V = 3.3 V

CC

V

PECL

F

OUT

F

OUT

OL

(Notes 3, 4)

I

V

48

18

56

22

70

26

48

18

58

22

70

26

48

18

61

22

70

26

mA

CC

PLL_V

3. F

4. F

/F

output levels will vary 1:1 with V variation.

outputs are terminated through a 50 W resistor to V

OUT OUT

CC

/F

- 2.0 V.

OUT OUT

CC

DC CHARACTERISTICS (V = 5.0 V ± 5%)

CC

0°C

Typ

-

25°C

Typ

-

70°C

Typ

-

Min

Max

Min

Max

Min

Max

Symbol

Characteristic

Input HIGH Voltage

Condition

Unit

V

IH

V

= 5.0 V

2.0

-

2.0

-

2.0

-

V

CC

CMOS/

TTL

V

IL

Input LOW Voltage

= 5.0 V

-

0.8

-

0.8

-

0.8

V

CC

CMOS/

TTL

I

Input Current

-

2.5

-

1.0

-

2.5

-

1.0

-

2.5

-

1.0

-

mA

V

IN

V

Output HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

TEST

I

= -0.8 mA

OH

OL

OH

= 0.8 mA

= 5.0 V

0.4

V

OL

F

OUT

F

OUT

V

3.855

-

4.105 3.855

4.105

V

CC

PECL

(Notes 5, 6)

V

PECL

Output LOW Voltage

Power Supply Current

F

V

CC

(Notes 5, 6)

= 5.0 V

3.055

-

3.305 3.055

-

3.305 3.055

-

3.305

V

OL

OUT

I

V

50

19

58

23

75

27

50

19

60

23

75

27

50

19

65

23

75

27

mA

CC

PLL_V

5. F

6. F

/F

output levels will vary 1:1 with V variation.

outputs are terminated through a 50 W resistor to V

OUT OUT

CC

/F

- 2.0 volts.

OUT OUT

CC

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5

NBC12429

AC CHARACTERISTICS (V = 3.125 V to 5.25 V ± 5%; T = 0° to 70°C) (Note 8)

CC

A

Symbol

Characteristic

Condition

Min

Max

Unit

F

Maximum Input Frequency

S_CLOCK (Note 7)

Xtal Oscillator

-

10

20

MHz

MAXI

Maximum Output Frequency

VCO (Internal)

200

25

400

MHz

MAXO

F

OUT

t

Maximum PLL Lock Time

Cycle-to-Cycle Jitter (1 s)

Setup Time

-

10

ms

ps

ns

LOCK

jitter

s

See Applications Section

"20

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

M, N to P_LOAD

20

-

t

Hold Time

S_DATA to S_CLOCK

M, N to P_LOAD

20

-

ns

h

Minimum Pulse Width

S_LOAD

P_LOAD

50

-

pwMIN

DCO

t , t

Output Duty Cycle

Output Rise/Fall

47.5

175

52.5

425

%

F

OUT

20%-80%

ps

r

f

7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as

a test clock in TEST_MODE 6.

8. F

/F

outputs are terminated through a 50 W resistor to V

- 2.0 V.

OUT OUT

CC

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6

NBC12429

FUNCTIONAL DESCRIPTION

The internal oscillator uses the external quartz crystal as

for the output driver and the internal logic is separated from

the power supply for the phase-locked loop to minimize

noise induced jitter.

the basis of its frequency reference. The output of the

reference oscillator is divided by 16 before being sent to the

phase detector. With a 16 MHz crystal, this provides a

reference frequency of 1 MHz. Although this data sheet

illustrates functionality only for a 16 MHz crystal, Table 1,

any crystal in the 10-20 MHz range can be used, Table 3.

The VCO within the PLL operates over a range of 200 to

400 MHz. Its output is scaled by a divider that is configured

by either the serial or parallel interfaces. The output of this

loop divider is also applied to the phase detector.

The phase detector and the loop filter force the VCO

output frequency to be M times the reference frequency by

adjusting the VCO control voltage. Note that for some

values of M (either too high or too low), the PLL will not

achieve loop lock.

The output of the VCO is also passed through an output

divider before being sent to the PECL output driver. This

output divider (N divider) is configured through either the

serial or the parallel interfaces and can provide one of four

division ratios (1, 2, 4, or 8). This divider extends the

performance of the part while providing a 50% duty cycle.

The output driver is driven differentially from the output

divider and is capable of driving a pair of transmission lines

The configuration logic has two sections: serial and

parallel. The parallel interface uses the values at the M[8:0]

and N[1:0] inputs to configure the internal counters.

Normally upon system reset, the P_LOAD input is held

LOW until sometime after power becomes valid. On the

LOW-to-HIGH transition of P_LOAD, the parallel inputs

are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the

M[8:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial interface logic is implemented with a fourteen

bit shift register scheme. The register shifts once per rising

edge of the S_CLOCK input. The serial input S_DATA must

meet setup and hold timing as specified in the AC

Characteristics section of this document. With P_LOAD

held high, the configuration latches will capture the value of

the shift register on the HIGH-to-LOW edge of the

S_LOAD input. See the programming section for more

information.

The TEST output reflects various internal node values and

is controlled by the T[2:0] bits in the serial data stream. See

the programming section for more information.

terminated into 50 W to V -2.0 V. The positive reference

CC

Table 1. Programming VCO Frequency Function Table

VCO

Frequency

(MHz)

256

128

64

32

16

8

4

2

1

M8

0

•

M7

1

•

M6

1

•

M5

0

•

M4

0

•

M3

1

•

M2

0

•

M1

0

1

•

M0

0

1

0

1

•

M Count*

200

201

202

203

•

200

201

202

203

•

397

398

399

400

397

398

399

400

1

0

1

0

1

0

1

0

1

0

1

0

*With 16 MHz crystal.

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7

NBC12429

PROGRAMMING INTERFACE

Programming the NBC12429 is accomplished by

The input frequency and the selection of the feedback

divider M is limited by the VCO frequency range and

properly configuring the internal dividers to produce the

desired frequency at the outputs. The output frequency can

by represented by this formula:

F . M must be configured to match the VCO frequency

XTAL

range of 200 to 400 MHz in order to achieve stable PLL

operation.

FOUT + (F

B 16) M B N

(eq. 1)

XTAL

M

+ f

VCOmin

B (f

XTAL

B 16) and

B 16)

(eq. 3)

(eq. 4)

min

where F

is the crystal frequency, M is the loop divider

XTAL

+ f

VCOmax

B (f

XTAL

max

modulus, and N is the output divider modulus. Note that it

is possible to select values of M such that the PLL is unable

to achieve loop lock. To avoid this, always make sure that M

is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.

Assuming that a 16 MHz reference frequency is used the

above equation reduces to:

The value for M falls within the constraints set for PLL

stability. If the value for M fell outside of the valid range, a

different N value would be selected to move M in the

appropriate direction.

The M and N counters can be loaded either through a

parallel or serial interface. The parallel interface is

controlled via the P_LOAD signal such that a LOW to HIGH

transition will latch the information present on the M[8:0]

and N[1:0] inputs into the M and N counters. When the

P_LOAD signal is LOW, the input latches will be

transparent and any changes on the M[8:0] and N[1:0] inputs

FOUT + M B N

(eq. 2)

Substituting the four values for N (1, 2, 4, 8) yields:

Table 2. Programmable Output Divider Function Table

Output Frequency

Range (MHz)*

200-400

100-200

50-100

N1

N0

N Divider

F

OUT

will affect the F

output pair. To use the serial port, the

OUT

S_CLOCK signal samples the information on the S_DATA

line and loads it into a 14 bit shift register. Note that the

P_LOAD signal must be HIGH for the serial load operation

to function. The Test register is loaded with the first three

bits, the N register with the next two, and the M register with

the final nine bits of the data stream on the S_DATA input.

For each register, the most significant bit is loaded first (T2,

N1, and M8). A pulse on the S_LOAD pin after the shift

register is fully loaded will transfer the divide values into the

counters. The HIGH to LOW transition on the S_LOAD

input will latch the new divide values into the counters.

Figures 4 and 5 illustrate the timing diagram for both a

parallel and a serial load of the NBC12429 synthesizer.

M[8:0] and N[1:0] are normally specified once at

power-up through the parallel interface, and then possibly

again through the serial interface. This approach allows the

application to come up at one frequency and then change or

fine-tune the clock as the ability to control the serial

interface becomes available.

0

B1

M

0

1

B2

M

ꢀ

B

ꢀ

2

4

8

1

0

B4

Mꢀ

B

1

B8

Mꢀ

25-50

*For crystal frequency of 16 MHz.

The user can identify the proper M and N values for the

desired frequency from the above equations. The four output

frequency ranges established by N are 200-400 MHz,

100-200 MHz, 50-100 MHz and 25-50 MHz, respectively.

From these ranges, the user will establish the value of N

required. The value of M can then be calculated based on

equation 1. For example, if an output frequency of 131 MHz

was desired, the following steps would be taken to identify

the appropriate M and N values. 131 MHz falls within the

frequency range set by an N value of 2; thus, N [1:0] = 01.

For N = 2, F

= M ÷ 2 and M = 2 x F

. Therefore,

OUT

M = 131 x 2 = 262, so M[8:0] = 100000110. Following this

same procedure, a user can generate any whole frequency

desired between 25 and 400 MHz. Note that for N > 2,

fractional values of F

programmable frequency steps (and thus, the indicator of

the fractional output frequencies achievable) will be equal

The TEST output provides visibility for one of the several

internal nodes as determined by the T[2:0] bits in the serial

configuration stream. It is not configurable through the

parallel interface. The T2, T1, and T0 control bits are preset

can be realized. The size of the

OUT

to ‘000’ when P_LOAD is LOW so that the PECL F

OUT

outputs are as jitter-free as possible. Any active signal on the

TEST output pin will have detrimental affects on the jitter

of the PECL output pair. In normal operations, jitter

specifications are only guaranteed if the TEST output is

static. The serial configuration port can be used to select one

of the alternate functions for this pin.

to F

÷ 16 ÷ N.

XTAL

For input reference frequencies other than 16 MHz, see

Table 3, which shows the usable VCO frequency and M

divider range.

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8

NBC12429

Table 3. NBC12429 Frequency Operating Range

Output Frequency for F

=

XTAL

16 MHz and for N =

VCO Frequency Range for a Crystal Frequency of:

M

M[8:0]

10

12

14

16

18

20

1

2

4

8

160

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

360

370

380

390

400

410

420

430

440

450

460

470

480

490

500

510

010100000

010101010

010110100

010111110

011001000

011010010

011011100

011100110

011110000

011111010

100000100

100001110

100011000

100100010

100101100

100110110

101000000

101001010

101010100

101011110

101101000

101110010

101111100

110000110

110010000

110011010

110100100

110101110

110111000

111000010

111001100

111010110

111100000

111101010

111110100

111111110

200

212.5

225

202.5

213.75

225

237.5

250

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

360

370

380

390

400

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

360

370

380

390

400

100

105

110

115

120

125

130

135

140

145

150

155

160

165

170

175

180

185

190

195

200

50

52.5

55

25

236.25

247.5

258.75

270

262.5

275

26.25

27.5

28.75

30

201.25

210

287.5

300

57.5

60

218.75

227.5

236.25

245

281.25

292.5

303.75

315

312.5

325

62.5

65

31.25

32.5

33.75

35

202.5

210

337.5

350

67.5

70

217.5

225

253.75

262.5

271.25

280

326.25

337.5

348.75

360

362.5

375

72.5

75

36.25

37.5

38.75

40

232.5

240

387.5

400

77.5

80

200

206.25

212.5

218.75

225

247.5

255

288.75

297.5

306.25

315

371.25

382.5

393.75

82.5

85

41.25

42.5

43.75

45

262.5

270

87.5

90

231.25

237.5

243.75

250

277.5

285

323.75

332.5

341.25

350

92.5

95

46.25

47.5

48.75

50

292.5

300

97.5

100

256.25

262.5

268.75

275

307.5

315

358.75

367.5

376.25

385

322.5

330

281.25

287.5

293.75

300

337.5

345

393.75

352.5

360

306.25

312.5

318.75

367.5

375

382.5

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9

NBC12429

Most of the signals available on the TEST output pin are

T2

T1

T0

TEST (Pin 20)

useful only for performance verification of the NBC12429

itself. However, the PLL bypass mode may be of interest at

the board level for functional debug. When T[2:0] is set to

110, the NBC12429 is placed in PLL bypass mode. In this

mode the S_CLOCK input is fed directly into the M and N

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SHIFT REGISTER OUT

HIGH

F

REF

M COUNTER OUT

F

OUT

LOW

PLL BYPASS

dividers. The N divider drives the F

differential pair and

OUT

the M counter drives the TEST output pin. In this mode the

S_CLOCK input could be used for low speed board level

functional test or debug. Bypassing the PLL and driving

F

OUT

B 4

F

OUT

directly gives the user more control on the test clocks

sent through the clock tree. Figure 6 shows the functional

setup of the PLL bypass mode. Because the S_CLOCK is a

CMOS level the input frequency is limited to 250 MHz or

M[8:0]

N[1:0]

M, N

less. This means the fastest the F

pin can be toggled via

P_LOAD

OUT

the S_CLOCK is 250 MHz as the minimum divide ratio of

the N counter is 1. Note that the M counter output on the

TEST output will not be a 50% duty cycle due to the way the

divider is implemented.

Figure 4. Parallel Interface Timing Diagram

S_CLOCK

M0

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1

First

S_DATA

S_LOAD

Last

Bit

Figure 5. Serial Interface Timing Diagram

FREF

VCO_CLK

PLL 12429

MCNT

0

1

FOUT

(VIA ENABLE GATE)

N B

(1, 2, 4, 8)

SCLOCK

SEL_CLK

M COUNTER

FDIV4

7

MCNT

LOW

LATCH

Reset

TEST

MUX

FOUT

MCNT

FREF

HIGH

TEST

SHIFT

REG

14- BIT

SLOAD

SDATA

0

PLOAD

T0

T1

T2

DECODE

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK B N is on FOUT pin.

PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.

Figure 6. Serial Test Clock Block Diagram

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10

NBC12429

APPLICATIONS INFORMATION

Using the On-Board Crystal Oscillator

Power Supply Filtering

The NBC12429 features a fully integrated on-board

crystal oscillator to minimize system implementation costs.

The oscillator is a series resonant, multivibrator type design

as opposed to the more common parallel resonant oscillator

design. The series resonant design provides better stability

and eliminates the need for large on chip capacitors. The

oscillator is totally self contained so that the only external

component required is the crystal. As the oscillator is

somewhat sensitive to loading on its inputs, the user is

advised to mount the crystal as close to the NBC12429 as

possible to avoid any board level parasitics. To facilitate

co-location, surface mount crystals are recommended, but

not required. Because the series resonant design is affected

by capacitive loading on the crystal terminals, loading

variation introduced by crystals from different vendors

could be a potential issue. For crystals with a higher shunt

capacitance, it may be required to place a resistance across

the terminals to suppress the third harmonic. Although

typically not required, it is a good idea to layout the PCB

with the provision of adding this external resistor. The

resistor value will typically be between 500 W and 1 KW.

The oscillator circuit is a series resonant circuit and thus,

for optimum performance, a series resonant crystal should

be used. Unfortunately, most crystals are characterized in a

parallel resonant mode. Fortunately, there is no physical

difference between a series resonant and a parallel resonant

crystal. The difference is purely in the way the devices are

characterized. As a result, a parallel resonant crystal can be

used with the NBC12429 with only a minor error in the

desired frequency. A parallel resonant mode crystal used in

a series resonant circuit will exhibit a frequency of

oscillation a few hundred ppm lower than specified (a few

hundred ppm translates to kHz inaccuracies). In a general

computer application, this level of inaccuracy is immaterial.

Table 4 below specifies the performance requirements of the

crystals to be used with the NBC12429.

The NBC12429 is a mixed analog/digital product and as

such, it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is

naturally susceptible to random noise, especially if this noise

is seen on the power supply pins. The NBC12429 provides

separate power supplies for the digital circuitry (V ) and

CC

the internal PLL (PLL_V ) of the device. The purpose of

CC

this design technique is to try and isolate the high switching

noise of the digital outputs from the relatively sensitive

internal analog phase-locked loop. In a controlled

environment such as an evaluation board, this level of

isolation is sufficient. However, in a digital system

environment where it is more difficult to minimize noise on

the power supplies, a second level of isolation may be

required. The simplest form of isolation is a power supply

filter on the PLL_V pin for the NBC12429.

CC

Figure 7 illustrates a typical power supply filter scheme.

The NBC12429 is most susceptible to noise with spectral

content in the 1 KHz to 1 MHz range. Therefore, the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the V supply and the

CC

PLL_V pin of the NBC12429. From the data sheet, the

CC

PLL_V

current (the current sourced through the

pin) is typically 23 mA (27 mA maximum).

CC

Assuming that a minimum of 2.8 V must be maintained on

the PLL_V pin, very little DC voltage drop can be

CC

tolerated when a 3.3 V V supply is used. The resistor

CC

shown in Figure 7 must have a resistance of 10-15 W to meet

the voltage drop criteria. The RC filter pictured will provide

a broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20 KHz. As the noise

frequency crosses the series resonant point of an individual

capacitor, it’s overall impedance begins to look inductive

and thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL.

Table 4. Crystal Specifications

Parameter

Value

Fundamental AT Cut

Series Resonance*

±75 ppm at 25°C

±150 ppm 0 to 70°C

0 to 70°C

3.3 V or

5.0 V

3.3 V or

5.0 V

Crystal Cut

Resonance

L=1000 mH

R=15 W

R = 10-15 W

Frequency Tolerance

Frequency/Temperature Stability

Operating Range

S

PLL_V

CC

22 mF

NBC12429

0.01 mF

Shunt Capacitance

5-7 pF

Equivalent Series Resistance (ESR)

Correlation Drive Level

Aging

50 to 80 W

V

CC

100 mW

0.01 mF

5 ppm/Yr

(First 3 Years)

* See accompanying text for series versus parallel resonant

discussion.

Figure 7. Power Supply Filter

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11

NBC12429

A higher level of attenuation can be achieved by replacing

between V

and GND for the bypass capacitors.

CC

the resistor with an appropriate valued inductor. Figure 7

shows a 1000 mH choke. This value choke will show a

significant impedance at 10 KHz frequencies and above.

Because of the current draw and the voltage that must be

Combining good quality general purpose chip capacitors

with good PCB layout techniques will produce effective

capacitor resonances at frequencies adequate to supply the

instantaneous switching current for the NBC12429 outputs.

It is imperative that low inductance chip capacitors are used.

It is equally important that the board layout not introduce

any of the inductance saved by using the leadless capacitors.

Thin interconnect traces between the capacitor and the

power plane should be avoided and multiple large vias

should be used to tie the capacitors to the buried power

planes. Fat interconnect and large vias will help to minimize

layout induced inductance and thus maximize the series

resonant point of the bypass capacitors.

maintained on the PLL_V

pin, a low DC resistance

CC

inductor is required (less than 15 W). Generally, the

resistor/capacitor filter will be cheaper, easier to implement,

and provide an adequate level of supply filtering.

The NBC12429 provides sub-nanosecond output edge

rates and therefore a good power supply bypassing scheme

is a must. Figure 8 shows a representative board layout for

the NBC12429. There exists many different potential board

layouts and the one pictured is but one. The important aspect

of the layout in Figure 8 is the low impedance connections

C1

R1

1

C3

C2

R1 = 10-15 W

C1 = 0.01 mF

C2 = 22 mF

C3 = 0.1 mF

Xtal

= V

CC

= GND

= Via

Figure 8. PCB Board Layout for NBC12429 (28 PLCC)

Note the dotted lines circling the crystal oscillator

connection to the device. The oscillator is a series resonant

circuit and the voltage amplitude across the crystal is

relatively small. It is imperative that no actively switching

signals cross under the crystal as crosstalk energy coupled

to these lines could significantly impact the jitter of the

device. Special attention should be paid to the layout of the

crystal to ensure a stable, jitter free interface between the

crystal and the on-board oscillator. Note the provisions for

placing a resistor across the crystal oscillator terminals as

discussed in the crystal oscillator section of this data sheet.

Although the NBC12429 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL), there still

may be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter and bypass schemes discussed in this section

should be adequate to eliminate power supply noise-related

problems in most designs.

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12

NBC12429

Jitter Performance of the NBC12429

Care must be taken that the measured edge is the edge

immediately following the trigger edge. These scopes can

also store a finite number of period durations and

post-processing software can analyze the data to find the

maximum and minimum periods.

Jitter is a common parameter associated with clock

generation and distribution. Clock jitter can be defined as the

deviation in a clock’s output transition from its ideal

position.

Cycle-to-Cycle Jitter (short-term) is the period

variation between two adjacent cycles over a defined

number of observed cycles. The number of cycles observed

is application dependent but the JEDEC specification is

1000 cycles.

Recent hardware and software developments have

resulted in advanced jitter measurement techniques. The

Tektronix TDS-series oscilloscopes have superb jitter

analysis capabilities on non-contiguous clocks with their

histogram and statistics capabilities. The Tektronix

TDSJIT2/3 Jitter Analysis software provides many key

timing parameter measurements and will extend that

capability by making jitter measurements on contiguous

clock and data cycles from single-shot acquisitions.

M1 by Amherst was used as well and both test methods

correlated.

T

0

T

1

This test process can be correlated to earlier test methods

and is more accurate. All of the jitter data reported on the

NBC12429 was collected in this manner. Figure 11 shows

the jitter as a function of the output frequency. The graph

shows that for output frequencies from 25 to 400 MHz the

jitter falls within the "20 ps peak-to-peak specification.

The general trend is that as the output frequency is increased,

the output edge jitter will decrease.

T

= T - T

1 0

JITTER(cycle- cycle)

Figure 9. Cycle-to-Cycle Jitter

Peak-to-Peak Jitter is the difference between the

highest and lowest acquired value and is represented as the

width of the Gaussian base.

Figure 12 illustrates the RMS jitter performance of the

NBC12429 across its specified VCO frequency range. Note

that the jitter is a function of both the output frequency as

well as the VCO frequency. However, the VCO frequency

shows a much stronger dependence. The data presented has

not been compensated for trigger jitter.

RMS

or one

Sigma

Jitter

Long-Term Period Jitter is the maximum jitter

observed at the end of a period’s edge when compared to the

position of the perfect reference clock’s edge and is specified

by the number of cycles over which the jitter is measured.

The number of cycles used to look for the maximum jitter

varies by application but the JEDEC spec is 10,000 observed

cycles.

The NBC12429 exhibits long term and cycle-to-cycle

jitter, which rivals that of SAW based oscillators. This jitter

performance comes with the added flexibility associated

with a synthesizer over a fixed frequency oscillator. The

jitter data presented should provide users with enough

information to determine the effect on their overall timing

budget. The jitter performance meets the needs of most

system designs while adding the flexibility of frequency

margining and field upgrades. These features are not

available with a fixed frequency SAW oscillator.

Typical

Time

Gaussian

Distribution

Figure 10. Peak-to-Peak Jitter

There are different ways to measure jitter and often they

are confused with one another. The typical method of

measuring jitter is to look at the timing signal with an

oscilloscope and observe the variations in period-to-period

or cycle-to-cycle. If the scope is set up to trigger on every

rising or falling edge, set to infinite persistence mode and

allowed to trace sufficient cycles, it is possible to determine

the maximum and minimum periods of the timing signal.

Digital scopes can accumulate a large number of cycles,

create a histogram of the edge placements and record

peak-to-peak as well as standard deviations of the jitter.

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13

NBC12429

25

20

15

10

5

20

15

10

N = 8

N = 4

250

5

0

N = 1

N = 2

0

200

300

350

400

50

100

150

200

250

300

350 400

VCO FREQUENCY (MHz)

OUTPUT FREQUENCY (MHz)

Figure 12. RMS Jitter vs. Output Frequency

Figure 11. RMS Jitter vs. VCO Frequency

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14

NBC12429

S_DATA

S_CLOCK

t

HOLD

t

SET- UP

Figure 13. Set-Up and Hold

S_DATA

S_LOAD

t

HOLD

t

SET- UP

Figure 14. Set-Up and Hold

M[8:0]

N[1:0]

P_

LOAD

t

HOLD

t

SET- UP

Figure 15. Set-Up and Hold

F

OUT

Pulse Width

t

tpw

tPERIOD

PERIOD

DCO +

Figure 16. Output Duty Cycle

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15

NBC12429

F

OUT

D

Receiver

Device

Driver

Device

OUT

50

TT

50

W

V

TT

V

=

- 2.0 V

CC

Figure 17. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020 - Termination of ECL Logic Devices.)

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16

NBC12429

PACKAGE DIMENSIONS

PLCC-28

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 776-02

ISSUE E

M

S

0.007 (0.180)

T

L−M

N

B

Z

Y BRK

D

-N-

M

S

N

0.007 (0.180)

T

L−M

U

-M-

-L-

W

D

S

N

0.010 (0.250)

T

L−M

X

G1

V

28

1

VIEW D-D

M

S

A

0.007 (0.180)

T

L−M

N

M

S

N

0.007 (0.180)

T

L−M

H

Z

M

S

T

N

R

K1

C

E

0.004 (0.100)

G

K

SEATING

PLANE

-T-

J

M

S

N

0.007 (0.180)

T

L−M

F

VIEW S

G1

S

N

0.010 (0.250)

T

L−M

VIEW S

NOTES:

INCHES

MILLIMETERS

1. DATUMS −L−, −M−, AND −N− DETERMINED

WHERE TOP OF LEAD SHOULDER EXITS

PLASTIC BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE

MEASURED AT DATUM −T−, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE

MOLD FLASH. ALLOWABLE MOLD FLASH IS

0.010 (0.250) PER SIDE.

DIM MIN

MAX

0.495

0.180

0.110

0.019

MIN

12.32

4.20

MAX

12.57

4.57

A

B

C

E

F

0.485

0.165

0.090

0.013

2.29

0.33

2.79

0.48

G

H

J

0.050 BSC

1.27 BSC

4. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

0.026

0.020

0.025

0.450

0.042

−−−

0.032

−−−

0.66

0.51

0.64

11.43

1.07

−−−

0.81

−−−

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN

THE PACKAGE BOTTOM BY UP TO 0.012

(0.300). DIMENSIONS R AND U ARE

DETERMINED AT THE OUTERMOST

EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR

BURRS, GATE BURRS AND INTERLEAD

FLASH, BUT INCLUDING ANY MISMATCH

BETWEEN THE TOP AND BOTTOM OF THE

PLASTIC BODY.

K

R

U

V

W

X

Y

Z

−−−

0.456

0.048

0.056

0.020

10

11.58

1.21

1.42

0.50

10

2

_

G1 0.410

K1 0.040

0.430

−−−

10.42

1.02

10.92

−−−

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037

(0.940). THE DAMBAR INTRUSION(S) SHALL

NOT CAUSE THE H DIMENSION TO BE

SMALLER THAN 0.025 (0.635).

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17

NBC12429

PACKAGE DIMENSIONS

LQFP-32

FA SUFFIX

PLASTIC LQFP PACKAGE

CASE 873A-02

ISSUE A

4X

A

A1

0.20 (0.008) AB T−U

Z

32

25

1

AE

-U-

-T-

P

B

V

B1

DETAIL Y

-Z-

BASE

METAL

DETAIL Y

V1

17

8

N

9

4X

0.20 (0.008) AC T−U

Z

9

F

D

S1

S

_

8X M

J

R

DETAIL AD

G

SECTION AE-AE

-AB-

-AC-

E

C

SEATING

PLANE

0.10 (0.004) AC

W

_

Q

H

K

X

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED

AT DATUM PLANE −AB−.

MILLIMETERS

DIM MIN MAX

7.000 BSC

3.500 BSC

INCHES

MIN MAX

0.276 BSC

A

A1

B

0.138 BSC

0.276 BSC

0.138 BSC

7.000 BSC

3.500 BSC

B1

C

1.400

1.600

0.450

1.450

0.400

0.055

0.063

0.018

0.057

0.016

D

0.300

1.350

0.300

0.012

0.053

0.012

E

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE −AC−.

F

G

H

0.800 BSC

0.031 BSC

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE −AB−.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

0.050

0.090

0.500

0.150

0.200

0.700

0.002

0.004

0.020

0.006

0.008

0.028

J

K

_

12 REF

_

12 REF

M

N

0.090

0.160

0.004

0.006

P

0.400 BSC

1_

0.016 BSC

1_

Q

R

5_

0.150

0.250

0.006

0.010

S

9.000 BSC

0.354 BSC

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

S1

V

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

V1

W

X

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18

NBC12429

Notes

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19

NBC12429

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

JAPAN: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: 81-3-5773-3850

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada

Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

NBC12429/D

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20


型号：	NBC12429
厂家：	ONSEMI
描述：	3.3V/5V Programmable PLL Synthesized Clock Generator 3.3V / 5V可编程PLL合成时钟发生器时钟发生器
文件：	总20页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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