NBSG11MNG [ONSEMI]
2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL Outputs; 2.5V / 3.3V SiGe半导体1 ： 2差分时钟驱动器，带有RSECL输出
| 型号： | NBSG11MNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V SiGe 1:2 Differential Clock Driver with RSECL Outputs |
| 文件： | 总12页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG11
2.5V/3.3VꢀSiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
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MARKING DIAGRAMS*
Description
The NBSG11 is a 1−to−2 differential fanout buffer, optimized for
low skew and Ultra−Low JITTER.
SG
11
ALYW
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
FCBGA−16
BA SUFFIX
CASE 489
Features
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
16
1
SG11
ALYWG
G
QFN−16
MN SUFFIX
CASE 485G
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V
CC
with V = 0 V
EE
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V = 0 V with V = −2.375 V to −3.465 V
CC
EE
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
• Pb−Free Packages are Available
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 8
NBSG11/D
NBSG11
1
2
3
4
V
NC NC
15 14
V
CC
EE
Exposed Pad (EP)
16
13
VTCLK
A
B
NC
NC
Q1
VTCLK
CLK
Q0
11 Q0
1
2
3
4
12
CLK
CLK
V
Q1
Q0
V
CC
CC
EE
NBSG11
Q1
Q1
CLK
10
9
V
V
EE
C
D
VTCLK
VTCLK
NC
NC
Q0
5
6
7
8
V
EE
NC NC
V
CC
Figure 1. BGA−16 Pinout (Top View)
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
BGA
D1
QFN
Name
VTCLK
CLK
I/O
Description
1
2
−
Internal 50 W Termination Pin. See Table 2.
Inverted Differential Input. Internal 75 kW to V and 36.5 kW to V
C1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
.
CC
EE
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kW to V
.
EE
A1
4
VTCLK
−
−
−
Internal 50 W Termination Pin. See Table 2.
Negative Supply Voltage
No Connect
B2,C2
5,16
V
EE
A2,A3,D2,
D3
6,7,14,15
NC
B3,C3
A4
8,13
9
V
−
Positive Supply Voltage
CC
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to
= V − 2.0 V.
V
TT
CC
B4
C4
10
11
12
−
Q1
Q0
Q0
EP
RSECL Output
RSECL Output
RSECL Output
−
Noninverted Differential Output 1. Typically Terminated with 50 W to
= V − 2.0 V.
V
TT
CC
Inverted Differential output 0. Typically Terminated with 50 W to
= V − 2.0 V.
V
TT
CC
D4
Noninverted Differential Output 0. Typically Terminated with 50 W to
= V − 2 V.
V
TT
CC
N/A
Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
CC
EE
bottom (see case drawing) must be attached to a heat−sinking conduit.
3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self−oscillation.
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2
NBSG11
V
CC
VTCLK
Q1
Q1
36.5 KW
50 W
CLK
CLK
Q0
Q0
75 KW
75 KW
50 W
VTCLK
V
EE
Figure 3. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
Connect VTCLK and VTCLK to V
CML
LVDS
CC
Connect VTCLK and VTCLK together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL Termination Techniques
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V /2
CC
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
ESD Protection
36.5 kW
Human Body Model
> 2 kV
Machine Model
> 100 V
Moisture Sensitivity (Note 4)
Pb Pkg
Pb−Free Pkg
FCBGA−16
QFN−16
Level 3
Level 1
N/A
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
125
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
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NBSG11
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
3.6
Unit
V
V
CC
V
EE
V
I
Positive Power Supply
Negative Power Supply
V
V
EE
= 0 V
−3.6
V
CC
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V ≤ V
3.6
V
V
EE
I
CC
V ≥ V
−3.6
CC
I
EE
V
INPP
Differential Input Voltage
|D − D|
V
CC
V
CC
− V
− V
w
<
2.8 V
2.8 V
2.8
|V − V
CC
V
V
EE
EE
|
EE
I
Output Current
Continuous
Surge
25
50
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
16 FCBGA
16 QFN
−40 to +70
−40 to +85
°C
A
T
stg
−65 to +150
°C
q
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
16 FCBGA
16 FCBGA
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JA
(Note 5)
500 lfpm
0 lfpm
500 lfpm
16 QFN
Thermal Resistance (Junction−to−Case)
Wave Solder
1S2P (Note 5)
2S2P (Note 6)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
JC
T
sol
Pb
Pb−Free
225
225
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
6. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG11
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 2.5 V; V = 0 V (Note 7)
CC
EE
−40°C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
Max
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
60
60
75
V
V
V
1450
350
1530
410
1575
525
1525 1565 1600
350 410 525
1550
350
1590
410
1625
525
OH
OUTPP
IH
Input HIGH Voltage (Single−Ended)
(Note 10)
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
V
1435
mV
−
V
1000
mV*
−
V
CC
CC
CC
1435
mV
1000
mV*
1435 1000
mV mV*
V
V
Input LOW Voltage (Single−Ended)
(Note 11)
V
2.5 V
−
V
−
V
−
V
−
V
−
V
−
V
2.5 V
−
V
1400
mV*
−
V −
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
1400 150 mV 2.5 V 1400 150
mV*
mV*
mV
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 9)
1.2
2.5
1.2
45
2.5
1.2
2.5
IHCMR
R
Internal Input Termination Resistor
45
50
80
25
55
50
80
25
55
45
50
80
25
55
W
TIN
I
Input HIGH Current (@ V , V )
IHMAX
150
100
150
100
150
100
mA
mA
IH
IL
IH
I
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
7. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −0.965 V.
CC
EE
8. All loading with 50 W to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10.V cannot exceed V
.
CC
IH
11. V always ≥ V
.
IL
EE
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NBSG11
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 3.3 V; V = 0 V (Note 12)
CC
EE
−40°C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
60
Max
75
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 13)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
60
V
OH
2250
350
2330
410
2375
525
2325
350
2365
410
2400
525
2350
350
2390
410
2425
525
V
V
OUTPP
IH
Input HIGH Voltage (Single−Ended)
(Note 15)
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
V
1435
mV
−
V
1000
mV*
−
V
CC
CC
CC
1435
mV
1000
mV*
1435
mV
1000
mV*
V
V
Input LOW Voltage (Single−Ended)
(Note 16)
V
2.5 V
−
V
1400
mV*
−
V
150
mV
−
V
2.5 V
−
V
1400
mV*
−
V
150
mV
−
V
2.5 V
−
V
1400
mV*
−
V −
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
Input HIGH Voltage Common Mode
Range (Note 14)
1.2
3.3
1.2
3.3
1.2
3.3
IHCMR
(Differential Configuration)
R
Internal Input Termination Resistor
45
50
80
25
55
45
50
80
25
55
45
50
80
25
55
W
TIN
I
Input HIGH Current (@ V , V )
IHMAX
150
100
150
100
150
100
mA
mA
IH
IL
IH
I
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
12.Input and output parameters vary 1:1 with V . V can vary +0.925 V to −0.165 V.
CC
EE
13.All loading with 50 W to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
15.V cannot exceed V
.
CC
IH
16.V always ≥ V
.
IL
EE
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
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NBSG11
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = −3.465 V to −2.375 V (Note 17)
EE
−40°C
Typ
60
25°C
Typ
60
70°C(BGA)/85°C(QFN)**
Min
Max
Min
Max
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 18)
Output Amplitude Voltage
Unit
mA
mV
mV
V
I
EE
45
75
45
75
VOH
−1050 −970 −925
350 410 525
−975 −935 −900
350 410 525
−950
350
−910
410
−875
525
V
V
OUTPP
Input HIGH Voltage (Single−Ended)
(Note 20)
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
V
1435
mV
−
V
1000
mV*
−
V
CC
IH
CC
CC
1435 1000
mV mV*
1435 1000
mV mV*
V
Input LOW Voltage (Single−Ended) (Note 21)
V
−
V
−
V
150
mV
−
V
−
V
−
V
150
mV
−
V
2.5 V
−
V
1400
mV*
−
V −
IH
150
mV
V
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
2.5 V 1400
mV*
2.5 V 1400
mV*
V
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 19)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V +1.2
EE
0.0
IHCMR
R
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
80
25
55
W
TIN
I
Input HIGH Current (@ V , V )
IHMAX
80
25
150
100
80
25
150
100
150
100
mA
mA
IH
IL
IH
I
Input LOW Current (@ V , V
)
IL
ILMIN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
20.V cannot exceed V
.
CC
IH
21.V always ≥ V
.
IL
EE
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
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NBSG11
Table 8. AC CHARACTERISTICS for FCBGA−16
V
CC
= 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
−40°C
Typ
12
25°C
Typ
12
70°C
Typ
12
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.709
10.709
10.709
GHz
max
(See Figure 4. F /JITTER) (Note 22)
max
t
t
,
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 23)
Within−Device Skew (Note 24)
Device−to−Device Skew (Note 25)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
f
in
< 10 GHz
0.2
1
0.2
1
0.2
1
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75
20
2600
55
75
20
2600
55
75
20
2600
55
mV
ps
INPP
t
r
t
f
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
Q, Q
30
30
30
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V. For minimum f
value of 10.709 GHz,
CC
max
output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% − 80%).
23.See Figure 5. t
= |t
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
SKEW
PLH
24.Within−Device skew is defined as identical transitions on similar paths through a device.
25.Device−to−device skew for identical transitions at identical V levels.
CC
26.V
(MAX) cannot exceed V − V
.
INPP
CC
EE
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NBSG11
Table 9. AC CHARACTERISTICS for QFN−16 V = 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
CC
EE
CC
EE
−40°C
25°C
Typ
12
85°C
Typ
12
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.5
12
10.5
10.5
GHz
max
(See Figure 4. F /JITTER) (Note 27)
max
t
t
,
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 28)
Within−Device Skew (Note 29)
Device−to−Device Skew (Note 30)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
f
in
< 10 GHz
0.2
1
0.2
1
0.2
1
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 31)
75
15
2600
55
75
20
2600
55
75
20
2600
55
mV
ps
INPP
t
r
t
f
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
Q, Q
30
30
30
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
27.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V −2.0 V. For minimum f
value of 10.5 GHz,
CC
max
output amplitude is approximately 200 mV (as shown in Figure 4, where output P−P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% − 80%).
28.See Figure 5. t
= |t
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
SKEW
PLH
29.Within−Device skew is defined as identical transitions on similar paths through a device.
30.Device−to−device skew for identical transitions at identical V levels.
CC
31.V
(MAX) cannot exceed V − V
.
INPP
CC
EE
600
500
400
9.5
8.5
7.5
6.5
5.5
4.5
3.5
2.5
1.5
0.5
−0.5
OUTPUT AMP.
OUTPUT P−P SPEC
300
200
100
0
RMS JITTER
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
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NBSG11
CLK
V
V
= V (CLK) − V (CLK)
IH IL
INPP
CLK
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
t
PHL
PLH
Figure 5. AC Reference Measurement
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
FCBGA−16
FCBGA−16
QFN−16
Shipping
NBSG11BA
100 Units / Tray (Contact Sales Representative)
100 / Tape & Reel
NBSG11BAR2
NBSG11MN
NBSG11MNG
123 Units / Rail
QFN−16
(Pb−Free)
123 Units / Rail
NBSG11MNR2
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
NBSG11MNR2G
QFN−16
(Pb−Free)
Board
Description
NBSG11BA Evaluation Board
NBSG11BAEVB
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
10
NBSG11
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
−Y−
E
K
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M−M
5
0.15 Z
A2
A
−Z−
16 X
A1
0.10 Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
http://onsemi.com
11
NBSG11
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
E2 1.65
1.85
0.10
0.08
C
C
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SIDE VIEW
D2
A1
C
SOLDERING FOOTPRINT*
3.25
0.128
0.30
0.575
0.022
e
L
16X
EXPOSED PAD
EXPOSED PAD
5
8
NOTE 5
0.012
4
9
E2
e
K
16X
1.50
0.059
12
3.25
0.128
1
16
13
16X b
0.30
0.012
0.10 C A
B
BOTTOM VIEW
0.05
C
NOTE 3
0.50
0.02
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and solder
details, please download the ON Semiconductor Soldering a
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NBSG11/D
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