NCD57001 [ONSEMI]
Isolated High Current IGBT Gate Driver;
| 型号： | NCD57001 |
| 厂家： | 
ONSEMI |
| 描述： | Isolated High Current IGBT Gate Driver 栅 双极性晶体管 |
| 文件： | 总14页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCD57001
Isolated High Current IGBT
Gate Driver
NCD57001 is a high−current single channel IGBT driver with
internal galvanic isolation, designed for high system efficiency and
reliability in high power applications. Its features include
complementary inputs, open drain FAULT and Ready outputs, active
Miller clamp, accurate UVLOs, DESAT protection, and soft turn−off
at DESAT. NCD57001 accommodates both 5 V and 3.3 V signals on
the input side and wide bias voltage range on the driver side including
negative voltage capability. NCD57001 provides > 5 kVrms
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(UL1577 rating) galvanic isolation and > 1200 V
(working
iorm
1
voltage) capabilities. NCD57001 is available in the wide−body
SOIC−16 package with guaranteed 8 mm creepage distance between
input and output to fulfill reinforced safety insulation requirements.
SOIC−16 WB
CASE 751G−03
Features
MARKING DIAGRAM
• High Current Output (+4/−6 A) at IGBT Miller Plateau Voltages
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delays with Accurate Matching
• Active Miller Clamp to Prevent Spurious Gate Turn−on
• DESAT Protection with Programmable Delay
• Negative Voltage (Down to −9 V) Capability for DESAT
• Soft Turn Off During IGBT Short Circuit
16
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
1
XXXXX = Specific Device Code
• IGBT Gate Clamping During Short Circuit
• IGBT Gate Active Pull Down
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range including Negative VEE2
• 3.3 V to 5 V Input Supply Voltage
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
• Designed for AEC−Q100 Certification
• 5000 V Galvanic Isolation (to meet UL1577 Requirements)
• 1200 V Working Voltage (per VDE0884−10 Requirements)
• High Transient Immunity
PIN ASSIGNMENT
• High Electromagnetic Immunity
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
VEE2A
GND1
VDD1
RST
FLT
DESAT
GND2
N/C
Typical Applications
• Solar Inverters
• Motor Control
• Uninterruptible Power Supplies (UPS)
• Industrial Power Supplies
• Welding
VDD2
OUT
RDY
IN−
CLAMP
VEE2
IN+
GND1A
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
February, 2019 − Rev. 2
NCD57001/D
NCD57001
VDD1
VDD2
VDD1
UVLO1
UVLO2
VCLAMP−THR
+
−
CLAMP
IN−
IN+
VEE2
STO
VDD1
OUT
RDY
Logic
Logic
1
VDD2
IDESAT−CHG
VDD1
+
DESAT
RST
FLT
−
VDD1
VDESAT−THR
GND2
GND1
2
1
GND1A
VEE2
VEE2A
Figure 1. Simplified Block Diagram
+V2
V1
VDD1
VDD2
DESAT
IN+
IN−
OUT
RDY
FLT
CLAMP
VEE2
RST
GND1
−V3
GND2
GND1
GND2
Figure 2. Simplified Application Schematics
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2
NCD57001
PIN DESCRIPTION
Pin Name
No.
1
I/O
Description
V
EE2A
Power
Output side negative power supply. A good quality bypassing capacitor is required from these pins
to GND2 and should be placed close to the pins for best results. Connect it to GND2 for unipolar
supply application.
V
EE2
8
DESAT
2
I/O
Input for detecting the desaturation of IGBT due to a short circuit condition. An internal constant
current source I
charging an external capacitor connected to this pin allows a
DESAT−CHG
programmable blanking delay every ON cycle before DESAT fault is processed, thus preventing
false triggering. When the DESAT voltage goes up and reaches V
, the output is driven
DESAT−THR
low. Further, the /FLT output is activated, please refer to Figure 5 on page 9.
A 5 ms mute time apply to IN+ and IN− once DESAT occurs.
Output side gate drive reference connecting to IGBT emitter or FET source.
Not connected.
GND2
N/C
3
4
5
Power
−
V
DD2
Power
Output side positive power supply. The operating range for this pin is from UVLO2 to its maximum
allowed value. A good quality bypassing capacitor is required from this pin to GND2 and should be
placed close to the pins for best results.
OUT
6
7
O
Driver output that provides the appropriate drive voltage and source/sink current to the IGBT/FET
gate. OUT is actively pulled low during start−up and under Fault conditions.
CLAMP
I/O
Provides clamping for the IGBT/FET gate during the off period to protect it from parasitic turn−on.
Its internal N FET is turned on when the voltage of this pin falls below V
+ V
. It is to
EE2
CLAMP−THR
be tied directly to IGBT/FET gate with minimum trace length for best results.
GND1
IN+
9
Power
I
Input side ground reference.
16
10
Non inverted gate driver input. It is internally clamped to V
50 kW to ensure that output is low in the absence of an input signal. A minimum positive going
pulse−width is required at IN+ before OUT responds.
and has a pull−down resistor of
DD1
IN−
11
12
I
Inverted gate driver input. It is internally clamped to V
ensure that output is low in the absence of an input signal. A minimum negative going pulse−width
is required at IN− before OUT responds.
and has a pull−up resistor of 50 kW to
DD1
RDY
O
Power good indication output, active high when V
is good. There is an internal 50 kW pull−up
DD2
resistor connected to this pin. Multiple of them from different drivers can be ”OR”ed together.
If a low RDY event is triggered by UVLO2, the maximum low duration for RDY is 200 ns.
OUT remains low when RDY is low. Short time delay may apply. See Figure 4 on page 8 for
details.
/FLT
13
O
Fault output (active low) that allows communication to the main controller that the driver has
encountered a desaturation condition and has deactivated the output.
/RST
14
15
I
Reset input with an internal 50 kW pull−up resistor, active low to reset fault latch.
V
DD1
Power
Input side power supply (3.3 V to 5 V).
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3
NCD57001
ABSOLUTE MAXIMUM RATINGS (Over operating free−air temperature range unless otherwise noted) (Note 1)
Symbol
Parameter
Minimum Maximum
Unit
V
V
V
−GND1
Supply voltage, input side
−0.3
−0.3
−10
0
6
DD1
DD2
−GND2
−GND2
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
Gate−driver output voltage
25
0.3
25
V
V
V
EE2
V
−V
EE2
(V )
MAX2
V
DD2
V
OUT
V
EE2
− 0.3
V + 0.3
DD2
V
I
Gate−driver output sourcing current
−
−
−
7.8
7.1
2.5
10
A
PK−SRC
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, V
= 20 V)
= 20 V)
MAX2
MAX2
CLAMP
I
Gate−driver output sinking current
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, V
A
A
PK−SNK
I
Clamp sinking current
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%, V
PK−CLAMP
= 3 V)
t
Maximum Short Circuit Clamping Time (I
Voltage at IN+, IN−, /RST, /FLT, RDY
Output current of /FLT, RDY
Desat Voltage (Note 2)
= 500 mA)
−
−0.3
−
ms
V
CLP
OUT_CLAMP
V
−GND1
V
+ 0.3
LIM
DD1
I
−GND1
10
mA
V
LIM
V
−GND2
−GND2
−9
V
V
+ 0.3
DESAT
CLAMP
DD2
DD2
V
Clamp Voltage
V
− 0.3
+ 0.3
V
EE2
P
Power Dissipation (Note 3)
Input to Output Isolation Voltage
Maximum Junction Temperature
Storage Temperature Range
−
−1200
−40
−65
−
1400
mW
V
D
V
ISO
1200
150
150
2
T
°C
°C
kV
kV
−
J(max)
T
STG
ESD
ESD
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Moisture Sensitivity Level
HBM
−
2
CDM
MSL
−
2
T
SLD
Lead Temperature Soldering Reflow, Pb−Free Versions (Note 5)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. The minimum value is verified by characterization with a single pulse of 100 mA for 100 ms.
2
3. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm , 1 oz copper, 2 surface layers and 2 internal
power plane layers. Power dissipation is affected by the PCB design and ambient temperature.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 25°C
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Symbol
Parameter
Conditions
Value
150
84
Unit
2
R
Thermal Resistance, Junction−to−Air
100 mm , 1 oz Copper, 1 Surface Layer
°C/W
q
JA
2
650 mm , 1 oz Copper, 2 Surface Layers and
2 Internal Power Plane Layers
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4
NCD57001
OPERATING RANGES (Note 6)
Symbol
Parameter
Supply voltage, input side
Min
UVLO1
UVLO2
−10
Max
5.5
24
0
Unit
V
V
V
−GND1
−GND2
−GND2
DD1
Positive Power Supply, output side
Negative Power Supply, output side
Differential Power Supply, output side
Low level input voltage at IN+, IN−, /RST
High level input voltage at IN+, IN−, /RST
Common Mode Transient Immunity (1500 V)
Ambient Temperature
V
DD2
V
V
EE2
V
−V
EE2
(V )
MAX2
0
24
V
DD2
V
IL
0
0.3 X V
V
DD1
DD1
V
IH
0.7 X V
V
V
DD1
|dV /dt|
100
−
kV/ms
°C
ISO
T
A
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
ELECTRICAL CHARACTERISTICS (V
A
= 5 V, V
= 15 V, V
= −8 V. For typical values T = 25°C, for min/max values,
DD1
DD2
EE2 A
T is the operating ambient temperature range that applies, unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VOLTAGE SUPPLY
V
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
−
2.4
0.125
13.2
12.2
−
−
−
3
−
V
V
UVLO1−OUT−ON
V
UVLO1−OUT−OFF
V
−
−
V
UVLO1−HYST
V
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
13.5
12.5
1
13.8
12.8
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
V
V
V
UVLO2−HYST
I
Input Supply Quiescent Current
Output Low
IN+ = Low, IN− = Low
−
1
2
6
4
6
mA
DD1−0
RDY = High, /FLT = High
IN+ = High, IN− = Low
I
Input Supply Quiescent Current
Output High
−
−
−
4.8
3.3
3.6
mA
mA
mA
DD1−100
RDY = High, /FLT = High
IN+ = Low, IN− = Low
I
Output Positive Supply Quiescent
Current, Output Low
DD2−0
RDY = High, /FLT = High, no load
IN+ = High, IN− = Low
I
I
Output Positive Supply Quiescent
Current, Output High
DD2−100
RDY = High, /FLT = High, no load
IN+ = High, IN− = Low, no load
I
Output Negative Supply
Quiescent Current, Output Low
−
−
0.4
0.2
2
2
mA
mA
EE2−0
Output Negative Supply
Quiescent Current, Output High
IN+ = High, IN− = Low, no load
EE2−100
LOGIC INPUT AND OUTPUT
V
IN+, IN−, /RST Low Input Voltage
IN+, IN−, /RST High Input Voltage
Input Hysteresis Voltage
−
−
−
0.3 x
DD1
V
V
IL
V
V
IH
0.7 x
DD1
−
V
V
−
0.15 x
DD1
−
−
−
V
IN−HYST
V
I
, I
IN−, /RST Input Current
(50 kW pull−up resistor)
V
/V = 0 V
IN− RST
−
−
−100
mA
mA
IN−L RST−L
I
IN+ Input Current
(50 kW pull−down resistor)
V = 5 V
IN+
100
IN+H
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NCD57001
ELECTRICAL CHARACTERISTICS (V
A
= 5 V, V
= 15 V, V
= −8 V. For typical values T = 25°C, for min/max values,
DD1
DD2
EE2 A
T is the operating ambient temperature range that applies, unless otherwise noted) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
LOGIC INPUT AND OUTPUT
I
, I
RDY, /FLT Pull−up Current
(50 kW pull−up resistor)
V /V = Low
RDY FLT
−
100
−
mA
RDY−L FLT−L
V
, V
RDY, /FLT Low Level Output Voltage
I /I = 5 mA
RDY FLT
−
−
−
−
0.3
10
V
RDY−L
FLT−L
t
Input Pulse Width of IN+, IN− for
No Response at Output
ns
MIN1
t
Input Pulse Width of IN+, IN− for
40
−
−
−
−
ns
ns
MIN2
Guaranteed Response at Output
t
Pulse Width of /RST for Resetting
/FLT
800
RST−MIN
DRIVER OUTPUT
V
V
Output Low State
I
I
I
I
= 200 mA
−
−
−
−
−
−
0.1
0.5
0.3
0.8
7.1
7.8
0.2
0.8
0.5
1
V
V
OUTL1
OUTL3
OUTH1
OUTH3
SINK
SINK
SRC
SRC
(V
– V
)
OUT
EE2
= 1.0 A, T = 25°C
A
V
V
Output High State
(V – V
= 200 mA
)
OUT
DD2
= 1.0 A, T = 25°C
A
I
Peak Driver Current, Sink (Note 7)
Peak Driver Current, Source (Note 7)
V
V
= 7.9 V
−
A
A
PK−SNK1
PK−SRC1
OUT
OUT
I
= −5 V
−
MILLER CLAMP
V
Clamp Voltage
I
I
= 2.5 A, T = 25°C
−
−
1.3
−
1.7
3
V
V
CLAMP
CLAMP
A
(V
– V
)
CLAMP
EE2
= 2.5 A, T = −40°C to 125°C
CLAMP
A
V
Clamp Activation Threshold
(V – V
1.5
2
2.5
CLAMP−THR
)
EE2
CLAMP
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage, (V
V
− V )
DD2
IN+ = Low, IN− = High,
= 500 mA
−
−
0.9
1.4
1.1
1.6
V
V
CLAMP−OUT
OUT
I
OUT
(pulse test, t
= 10 ms)
CLPmax
V
Clamping Voltage, Clamp
(V − V
IN+ = High, IN− = Low,
I = 500 mA
CLAMP−CLAMP
CLAMP−CLAMP
)
CLAMP
DD2
(pulse test, t
= 10 ms)
CLPmax
DESAT PROTECTION
V
DESAT Threshold Voltage
DESAT Negative Voltage
Blanking Charge Current
Blanking Discharge Current
8.5
−
9
9.5
−
V
V
DESAT−THR
DESAT−NEG
DESAT−CHG
V
I
= 1.5 mA
−8
0.5
50
DESAT
I
V
= 7 V
0.45
−
0.6
−
mA
mA
DESAT
I
DESAT−DIS
DYNAMIC CHARACTERISTICS
t
IN+, IN− to Output High Propagation
C
IH
= 10 nF
LOAD
40
40
60
66
90
90
ns
ns
PD−ON
Delay
V
to 10% of output change for
PW > 150 ns. OUT and CLAMP pins
are connected together
t
IN+, IN− to Output Low Propagation
Delay
C
= 10 nF
LOAD
PD−OFF
V to 90% of output change for
IL
PW > 150 ns. OUT and CLAMP pins
are connected together
t
Propagation Delay Distortion
T = 25°C, PW > 150 ns
−15
−25
−30
−6
−
15
25
30
ns
ns
DISTORT
A
(= t
− t
)
PD−ON
PD−OFF
T = −40°C to 125°C, PW > 150 ns
A
t
Prop Delay Distortion between Parts
PW > 150 ns
0
DISTORT_TOT
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NCD57001
ELECTRICAL CHARACTERISTICS (V
A
= 5 V, V
= 15 V, V
= −8 V. For typical values T = 25°C, for min/max values,
DD1
DD2
EE2 A
T is the operating ambient temperature range that applies, unless otherwise noted) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
t
Rise Time (see Fig. 3) (Note 7)
C
= 1 nF, 10% to 90% of
LOAD
−
−
−
−
10
15
−
−
−
−
ns
ns
ns
ns
ms
RISE
Output Change
t
Fall Time (see Fig. 3) (Note 7)
C
= 1 nF, 90% to 10% of
FALL
LOAD
Output Change
t
DESAT Leading Edge Blanking Time
(See Fig. 5)
450
320
LEB
t
DESAT Threshold Filtering Time
(see Fig. 5)
FILTER
t
Soft Turn Off Time (see Fig. 5)
−
−
−
−
−
1.8
2.6
450
23
−
−
−
−
−
C
C
= 10 nF, R = 10 W. V
= 0 V
STO
LOAD
LOAD
G
EE2
= 10 nF, R = 10 W
G
t
Delay after t
to /FLT
ns
ns
ns
FLT
FILTER
t
/RST Rise to /FLT Rise Delay
RST
t
t
RDY High to Output High Delays
(see Fig. 4)
55
RDY1O
RDY2O
t
V
to RDY Low
−
8
−
ms
RDY1F
UVLO2−OUT−OFF
Delays (see Fig. 4)
t
RDY2F
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Values based on design and/or characterization.
ORDERING INFORMATION
†
Device
Package Type
Shipping
NCD57001DWR2G
SOIC−16 Wide Body
(Pb−Free)
1,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCD57001
V
IH
V
IL
IN+
t
t
FALL
t
MIN1
RISE
90%
t
PD−ON
t
MIN1
t
PD−OFF
OUT
10%
t
t
MIN2
MIN2
Figure 3. Propagation Delay, Rise and Fall Time
RDY
RDY
IN+
t
t
RDY1F
RDY2F
IN+
V
UVLO2−OUT−ON
V
UVLO2−OUT−OFF
V
V
DD1
UVLO1−OUT−ON
V
UVLO1−OUT−OFF
V
DD2
t
t
V
OUT
RDY2O
RDY1O
UVLO2−OUT−ON
V
UVLO2−OUT−OFF
OUT
Figure 4. UVLO Waveform
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NCD57001
IN+
t
PD−ON
t
MUTE
t
FILTER
V
EE2
+ 2 V
V
OUT
t
STO
V
DESAT−THR
t
LEB
DESAT
FLT
t
FLT
t
RST
RST
t
RST−MIN
Figure 5. DESAT Response Waveform
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NCD57001
TYPICAL CHARACTERISTICS
(Conditions for the following figures are the same as stated for ELECTRICAL CHARACTERISTICS Table unless otherwise noted.
Typical and/or average values are used.)
6.0
5.0
4.0
3.0
2.0
1.0
0.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
DD1
V
DD1
V
DD1
V
DD1
= 5 V, IN+ = Low, IN− = LOW
= 5 V, IN+ = High, IN− = LOW
= 3.3 V, IN+ = Low, IN− = LOW
= 3.3 V, IN+ = High, IN− = LOW
V
DD2
V
DD2
V
DD2
= 15 V, IN+ = Low, IN− = LOW
= 15 V, IN+ = 1 MHz, IN− = LOW
= 15 V, IN+ = High, IN− = LOW
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Figure 6. VDD1 Supply Current
Temperature (5C)
Figure 7. VDD2 Supply Current
0.5
0.4
0.3
0.2
0.1
0.0
5.0
4.0
3.0
V
V
= −8 V, IN+ = Low, IN− = LOW
= −8 V, IN+ = High, IN− = LOW
EE2
EE2
2.0
I
I
I
, V
, V
, V
= 5 V
= 15 V
= −8 V
DD1
DD1
DD2
EE2
DD2
1.0
EE2
0.0
−1.0
−40 −20
0
20
40
60
80
100 120
0
100
200
300
400
500
Temperature (5C)
Input Frequency (kHz)
Figure 8. VEE2 Supply Current
Figure 9. Supply Current vs Frequency
14.0
13.5
13.0
12.5
12.0
3.0
2.9
2.8
2.7
2.6
2.5
V
V
UVLO1−OUT−ON
UVLO1−OUT−OFF
V
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 10. UVLO1 Threshold Voltage
Figure 11. UVLO2 Threshold Voltage
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NCD57001
TYPICAL CHARACTERISTICS
(Conditions for the following figures are the same as stated for ELECTRICAL CHARACTERISTICS Table unless otherwise noted.
Typical and/or average values are used.) (continued)
2.0
2.0
1.5
1.0
0.5
0.0
V
V
(0.2 A) V
= −8 V
EE2
= −8 V
V
V
(0.2 A) V
= −8 V
EE2
= −8 V
OUTH
OUTL
1.5
1.0
0.5
0.0
(1 A) V
(1 A) V
OUTH
EE2
OUTL
EE2
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 12. Output Voltage Drop, Sourcing
Figure 13. Output Voltage Drop, Sinking
2.0
1.5
1.0
0.5
0.0
2.5
2.0
1.5
1.0
0.5
0.0
V
(2.5 A) V
= −8 V
CLAMP
EE2
V
V
(0.5 A) V
= −8 V
CLAMP−OUT
EE2
(0.5 A) V
= −8 V
CLAMP−CLAMP
EE2
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 14. CLAMP Voltage Drop
Figure 15. IGBT Short Circuit Clamp Voltage Drop
90
80
70
60
50
40
40
35
30
25
20
15
10
5
t
t
t
t
,V
= −8 V
= −8 V
= 0 V
RISE EE2
t
t
PD−ON
,V
FALL EE2
PD−OFF
,V
RISE EE2
,V
= 0 V
FALL EE2
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
Figure 16. Propagation Delay
Figure 17. Rise and Fall Time
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11
NCD57001
4.0
3.0
2.0
1.0
0.0
t
t
,V
= −8 V
= 0 V
STO EE2
,V
STO EE2
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Figure 18. Soft Turn Off Time
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB
CASE 751G−03
ISSUE D
DATE 12 FEB 2013
1
SCALE 1:1
NOTES:
A
D
q
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T
A
0.25
0.50
0
0.75
0.90
7
_
_
GENERIC
MARKING DIAGRAM*
14X
e
C
SEATING
PLANE
T
16
SOLDERING FOOTPRINT
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
16X
0.58
1
XXXXX = Specific Device Code
11.00
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
1
= Work Week
= Pb−Free Package
16X
1.62
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
1.27
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42567B
SOIC−16 WB
PAGE 1 OF 1
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