NCD57084DR2G [ONSEMI]
Isolated Compact IGBT Gate Driver with DESAT;
| 型号： | NCD57084DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Isolated Compact IGBT Gate Driver with DESAT 栅 双极性晶体管 |
| 文件： | 总22页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Isolated Compact IGBT
Gate Driver with DESAT
NCD57084, NCV57084
NCx57084 is a high current single channel IGBT gate driver with
2.5 kVrms internal galvanic isolation designed for high system
efficiency and reliability in high power applications. The driver
includes DESAT short circuit protection with soft turn off and fault
reporting in a narrow body SOIC−8 package. NCx57084
accommodates wide range of input bias voltage and signal levels from
3.3 V to 20 V, and wide range of output bias voltage up to 30 V.
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8
1
Features
SOIC−8 NB
CASE 751−07
• High Peak Output Current (+7A/−7 A)
• Low Output Impedance for Enhanced IGBT Driving
• Short Propagation Delays with Accurate Matching
• DESAT Protection with Programmable Delay
• Negative Voltage (Down to −9 V) Capability for DESAT
• IGBT Gate Clamping during Short Circuit
• IGBT Gate Active Pull Down
MARKING DIAGRAM
8
57084
ALYW
G
• Soft Turn Off During IGBT Short Circuit
• Tight UVLO Thresholds for Bias Flexibility
• Output Partial Pulse Avoidance During UVLO/DESAT (Restart)
• 3.3 V, 5 V, and 15 V Logic Input
1
57084
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• 2.5 kVrms Galvanic Isolation
• High Transient Immunity
• High Electromagnetic Immunity
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements;
AEC−Q100 Qualified and PPAP Capable
PIN CONNECTIONS
1
2
8
7
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
VDD
IN
V
B
Compliant
HO
Typical Applications
• Motor Control
3
4
6
5
FLT
DESAT
GND
V
S
• Automotive Applications
• Uninterruptible Power Supplies (UPS)
• Industrial Power Supplies
• HVAC
NCx57084
x = D or V
• Industrial Pumps and Fans
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2021 − Rev. 1
NCD57084/D
NCD57084, NCV57084
VDD
VB
UVLO1
UVLO2
IN
VS
STO
HO
Logic
Logic
VB
VDD
IDESAT*CHG
DESAT
+
−
FLT
VDESAT*THR
VS
GND
Figure 1. Simplified Block Diagram
V2
V1
V
VDD
IN
B
HO
FLT
GND
DESAT
V
S
GND
GND2
Figure 2. Simplified Application Schematics
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2
NCD57084, NCV57084
FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
V
DD
1
Power
Input side power supply. A good quality bypassing capacitor is required from this pin to
GND and should be placed close to the pins for best results.
The under voltage lockout (UVLO1) circuit enables the device to operate at power on when
a typical supply voltage higher than V
more details.
is present. Please see Figure 4 for
UVLO1−OUT−ON
IN
2
3
I
Non−inverted gate driver input. It is internally clamped to GND and has an equivalent
pull−down resistor of 100 kW to ensure that output is low in the absence of an input signal.
FLT
O
Fault output (active low) that allows communication to the main controller that the driver
has encountered a desaturation, or UVLO1, or UVLO2 condition and has deactivated the
output. There is an internal 50 kW pull−up resistor connected to this pin. Multiple of them
from different drivers can be “OR”ed together.
FLT and HO will go high automatically after t
expires along with a rising edge of IN to
MUTE
avoid partial output pulse on HO. This is a feature called “Re−start”.
GND
4
5
6
Power
Power
I/O
Input side ground reference.
V
S
Output side ground reference.
DESAT
Input for detecting the desaturation of IGBT due to a short circuit condition. An internal
constant current source I
charging an external capacitor connected to this pin
DESAT−CHG
allows a programmable blanking delay every ON cycle before DESAT fault is processed,
thus preventing false triggering.
When the DESAT voltage goes up and reaches V
, the output is driven low.
DESAT−THR
Further, the FLT output is activated, please refer to Figure 6.
FLT and HO will be kept low (including soft turn off time) at least for a period defined by
t
.
MUTE
HO
7
8
O
Driver output that provides the appropriate drive voltage and source/sink current to the
IGBT/FET gate. HO is actively pulled low during start−up.
V
B
Power
Output side positive power supply. The operating range for this pin is from UVLO2 to its
maximum allowed value. A good quality bypassing capacitor is required from this pin to V
and should be placed close to the pins for best results.
S
The under voltage lockout (UVLO2) circuit enables the device to operate at power on when
a typical supply voltage higher than V
more details.
is present. Please see Figure 5 for
UVLO2−OUT−ON
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3
NCD57084, NCV57084
SAFETY AND INSULATION RATINGS
Symbol
Parameter
Value
I−IV
Unit
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
I−IV
I−IV
I−IV
< 1000 V
I−III
RMS
Climatic Classification
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
600
V
Input−to−Output Test Voltage, Method b, V
× 1.875 = V
,
2250
V
V
PR
IORM
PR
PK
100% Production Test with t = 1 s, Partial Discharge < 5 pC
m
V
IORM
Maximum Repetitive Peak Voltage
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1200
870
4200
4.0
PK
V
IOWM
V
RMS
V
IOTM
V
PK
E
CR
mm
mm
mm
°C
E
External Clearance
4.0
CL
DTI
Insulation Thickness
8.65
150
132
1128
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
T
Case
P
mW
mW
W
S,INPUT
P
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
10
IO
IO
ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
T = 25°C, Relative Humidity < 50%, t = 1.0 minute,
Value
Unit
V
Input−Output Isolation Voltage
2500
V
RMS
ISO,
INPUT− OUTPUT
A
I
< 30 mA, 50 Hz
I−O
(Notes 1, 2, 3)
11
R
Isolation Resistance
V
I−O
= 500 V (Note 1)
10
W
ISO
1. Device is considered a two−terminal device: pins 1 to 4 are shorted together and pins 5 to 8 are shorted together.
2. 2,500 VRMS for 1−minute duration is equivalent to 3,000 VRMS for 1−second duration.
3. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table.
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4
NCD57084, NCV57084
ABSOLUTE MAXIMUM RATINGS (Note 4) Over operating free−air temperature range unless otherwise noted.
Symbol
− GND
Parameter
Supply Voltage, Input Side
Minimum
−0.3
Maximum
Unit
V
V
22
32
DD
V
B
− V
Supply Voltage, Output Side
−0.3
V
S
V
HO
− V
Gate−driver Output Voltage
−0.3
V + 0.3
BS
V
S
I
Gate−driver Output Sourcing Peak Current
−
7
A
PK−SRC
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
D
− V = 15 V)
S
I
Gate−driver Output Sinking Peak Current
−
7.5
A
PK−SNK
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
D
− V = 15 V)
S
V
− GND
Voltage at IN, FLT
−0.3
−
V
+ 0.3
DD
V
mA
V
IN
I
Output current of FLT
10
+ 0.3
FLT
V
DESAT
− V
Voltage at DESAT (Note 5)
−9
−
V
S
BS
PD
Power Dissipation (Note 6)
1123
2
mW
kV
kV
−
ESD
ESD
ESD Capability, Human Body Model (Note 7)
ESD Capability, Charged Device Model (Note 7)
Moisture Sensitivity Level
−
HBM
CDM
−
2
MSL
T (max)
−
1
Maximum Junction Temperature
Storage Temperature Range
−40
−65
−
150
150
260
°C
°C
°C
J
T
STG
T
SLD
Lead Temperature Soldering Reflow, Pb−Free (Note 8)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. The minimum value is verified by characterization with a single pulse of 1.5 mA for 300 ms.
6. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm2, 1 oz copper, 2 surface layers and 2 internal
power plane layers. Power dissipation is affected by the PCB design and ambient temperature.
7. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78, 125°C.
8. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS (Note 9, 10)
Symbol
Parameter
Conditions
Value
179
Unit
R
Thermal Resistance, Junction−to−Air
100 mm2, 1 oz Copper, 1 Surface Layer
°C/W
θ
JA
100 mm2, 1 oz Copper, 2 Surface Layers and 2
Internal Power Plane Layers
110
9. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
10.Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 11)
Symbol
−GND
Parameter
Supply Voltage, Input Side
Min
UVLO1
UVLO2
GND
Max
20
Unit
V
V
DD
V −V
Supply Voltage, Output Side
Logic Input Voltage at IN
30
V
B
S
V
IN
V
DD
V
|dV /dt|
Common Mode Transient Immunity
Ambient Temperature
100
−
kV/ms
°C
ISO
T
A
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
11. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCD57084, NCV57084
ELECTRICAL CHARACTERISTICS
V
DD
= 5 V, V = 15 V.
BS
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
V
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
−
2.4
0.1
12.4
11.5
0.7
−
−
−
3.1
−
V
V
UVLO1−OUT−ON
V
UVLO1−OUT−OFF
V
−
−
V
UVLO1−HYST
V
UVLO2 Output Enabled
UVLO2 Output Disabled
UVLO2 Hysteresis
12.9
12
1
13.4
12.5
−
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
V
V
V
UVLO2−HYST
I
Input Supply Quiescent Current
Output Supply Quiescent Current
IN = Low, V = 3.3 V, FLT = Hig
−
2
mA
mA
mA
mA
mA
mA
DD−0−3.3
DD
I
IN = Low, V = 5 V, FLT = High
−
−
2
DD−0−5
DD
I
IN = Low, V = 15 V, FLT = High
−
−
2
DD−0−15
DD
I
IN = High, V = 5 V, FLT = High
−
−
6
DD−100−5
DD
I
IN = Low, no load
IN = High, no load
−
−
4
BS−0
I
−
−
6
BS−100
LOGIC INPUT AND OUTPUT
V
Low Input Voltage (Note 12)
High Input Voltage (Note 12)
Input Hysteresis Voltage (Note 12)
Input Current
0.3 × V
V
V
IL
DD
V
IH
0.7 × V
DD
V
0.15 × V
50
V
IN−HYST
DD
I
IN
V
V
= V
DD
mA
mA
IN
I
FLT Pull−up Current
(50 kW pull−up resistor)
= Low
−
100
−
FLT−L
FLT
V
t
FLT Low Level Output Voltage
I
= 5 mA
−
−
−
−
0.3
10
V
FLT−L
FLT
Input Pulse Width of IN for No
Response at Output
ns
MIN1
t
Input Pulse Width of IN for
Guaranteed Response at Output
40
−
−
ns
MIN2
DRIVER OUTPUT
V
V
Output Low State
I
I
I
I
= 200 mA
−
−
−
−
−
0.1
0.4
0.2
0.6
7.5
0.22
1
V
V
HOL1
HOL2
HOH1
HOH2
SNK
SNK
SRC
SRC
(V – V )
HO
S
= 1.0 A, T = 25°C
A
V
V
Output High State
(V – V
= 200 mA
0.35
1.7
−
)
HO
B
= 1.0 A, T = 25°C
A
I
I
Peak Driver Current, Sink
(Note 13)
A
A
A
A
PK−SNK1
PK−SNK2
PK−SRC1
PK−SRC2
Peak Driver Current, Sink
(Note 13)
V
= 9 V
−
−
−
7
7
5
−
−
−
HO
(near IGBT Miller Plateau)
I
I
Peak Driver Current, Source
(Note 13)
Peak Driver Current, Source
(Note 13)
V
= 9 V
HO
(near IGBT Miller Plateau)
DESAT PROTECTION
V
DESAT Threshold Voltage
DESAT Negative Voltage
Blanking Charge Current
Blanking Discharge Current
8.4
−
9
9.5
−
V
V
DESAT−THR
DESAT−NEG
DESAT−CHG
V
I
= 1.5 mA
= 7 V
−8
0.5
50
DESAT
I
V
0.45
−
0.55
−
mA
mA
DESAT
I
DESAT−DIS
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NCD57084, NCV57084
ELECTRICAL CHARACTERISTICS (continued) V = 5 V, V = 15 V.
DD
BS
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
IGBT SHORT CIRCUIT CLAMPING
IGBT Short Circuit Clamping
Parameter
Test Conditions
Min
Typ
Max
Unit
V
IN = High, I = 500 mA,
−
0.7
1.5
V
CLP−HO
HO
(V − V )
t
= 10 ms
HO
B
CLP
DYNAMIC CHARACTERISTICS
t
IN to HO High Propagation
Delay
C
= 10 nF
LOAD
to 10% of HO Change
40
40
60
60
90
90
ns
ns
ns
PD−ON
V
IH
for PW > 150 ns
C = 10 nF
LOAD
t
IN to HO Low Propagation Delay
PD−OFF
V
IL
to 90% of HO Change
for PW > 150 ns
t
Propagation Delay Distortion
T = 25°C, PW > 150 ns
A
−
0
−
0
−
DISTORT
(= t
− t
PD−OFF
)
PD−ON
T = −40°C to 125°C, PW > 150 ns
A
−25
−30
25
30
t
Prop Delay Distortion between
Parts
PW > 150 ns
ns
ns
ns
ns
ns
ms
DISTORT_TOT
t
t
Rise Time (see Figure 3)
(Note 13)
C
= 1 nF, 10% to 90%
LOAD
−
−
10
15
−
−
RISE
FALL
of HO Change
C = 1 nF, 90% to 10%
LOAD
Fall Time (see Figure 3)
(Note 13)
of HO Change
t
DESAT Leading Edge Blanking
Time (See Figure 6)
200
−
450
320
1.8
700
600
3
LEB
t
DESAT Threshold Filtering Time
(see Figure 6)
FILTER
t
Soft Turn Off Time
(see Figure 6)
C
= 10 nF, R = 10 W
1.2
STO
LOAD
G
t
Delay after t
to FLT Low
100
450
1.5
700
ns
FLT
FILTER
t
Delay from V
Triggered to FLT Low
−
−
ms
FLT1
UVLO1−OUT−OFF
t
Delay from t
to FLT Low
−
2.4
−
−
ms
ms
FLT2
UVF2
t
IN Mute Time after t
or UVLO1, UVLO2 Triggered
,
20
−
MUTE
FILTER
t
Delay from V
(Note 13)
(Note 13)
(Note 13)
(Note 13)
−
−
−
−
770
−
−
−
−
ns
ns
ns
ns
UVR1
UVLO1−OUT−ON
Triggered to HO High
t
Delay from V
1500
1000
1000
UVF1
UVLO1−OUT−OFF
Triggered to HO Low
t
Delay from V
UVR2
UVLO2−OUT−ON
Triggered to HO High
t
Delay from V
UVF2
UVLO2−OUT−OFF
Triggered to HO Low
(see Figure 5)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12.Table values are valid for 3.3 V and 5 V V , for higher V voltages, the threshold values are maintained at the 5 V V levels.
DD
DD
DD
13.Values based on design and/or characterization.
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NCD57084, NCV57084
VIH
VIL
IN
tRISE
tFALL
tMIN1
tMIN2
90%
tPD−ON
tMIN1
tPD−OFF
10%
HO
Figure 3. Propagation Delay, Rise and Fall Time
VBS
VUVLO1−OUT−ON
VUVLO1−OUT−OFF
tMUTE
tUVF1
tMUTE
tUVF1
VDD
tUVR1
tUVR1
tUVR1
IN
HO
tFLT1
tFLT1
FLT
Figure 4. UVLO1 Waveform
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NCD57084, NCV57084
VDD
VUVLO2−OUT−ON
VUVLO2−OUT−OFF
tMUTE
tUVF2
tMUTE
VBS
tUVR2
tUVF2
tUVR2
tUVR2
IN
HO
tFLT2
tFLT2
FLT
Figure 5. UVLO2 Waveform
IN
tMUTE
tMUTE
tPD−ON
tPD−ON
tPD−ON
90% HO
10% HO
HO
tSTO
tSTO
tFILTER
tFILTER
tLEB
VDESAT−THR
tLEB
DESAT
tFLT
tFLT
FLT
Figure 6. DESAT Response Waveform
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NCD57084, NCV57084
TRUTH TABLE
IN
L
UVLO1
UVLO2
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Active
DESAT
HO
L
FLT
L
Notes
Inactive
Inactive
Inactive
Inactive
Inactive
Active
L
L
L
L
L
X
L
X
L
Initial condition after power up V and V
DD
BS
↗
H
↘
L
↗
H
↘
L
↗
H
Initial condition − IN First Rising edge
Normal Operation − Output High
Normal Operation − Turn off Output
Normal Operation − Output Low
H
H
X
L
L
UVLO1 Activated − FLT Low (t
), Output Low
FLT1
↗
X
Inactive
Inactive
Inactive
Inactive
Inactive
↗
L
↗
L
FLT reset, UVLO1 conditions disappear
UVLO2 Activated − FLT Low (t ), Output Low
FLT1
↗
H
↗
Inactive
Inactive
Inactive
↗
L
↗
L
FLT reset, UVLO2 conditions disappear
H (>t
)
DESAT Activated − FLT Low (t ), Output Low
FILTER
FLT
L
↗
↗
FLT reset, DESAT conditions disappear
ORDERING INFORMATION
Device
†
Package
Shipping
NCD57084DR2G
NCV57084DR2G
2500 / Tape & Reel
SOIC−8 Narrow Body, (Pb−Free)
SOIC−8 Narrow Body, (Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
VDD
Clamping
Circuit
IN
Figure 7. Input Pin Structure
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10
NCD57084, NCV57084
TYPICAL CHARACTERISTICS
5
4
3
2
1
5
(3)
4
(3)
3
2
(2)
(2)
1
(1)
(1)
0
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
, I = 0 V
DD−0−5 N
(1) I
, I = 0 V
(1) I
DD−0−3.3
N
(2) I
(3) I
, I = 3.3 V/1 MHz/50%,
, I = 3.3 V
N
(2) I
(3) I
, I = 5 V/1 MHz/50%,
N
, I = 5 V
N
DD−50−3.3
DD−100−3.3
N
DD−50−5
DD−1000−5
(Note: V = 3.3 V, V = 15 V
(Note: V = 5 V, V = 15 V)
DD B
DD
B
Figure 8. IDD Supply Current, VDD = 3.3 V
Figure 9. IDD Supply Current, VBS = 5 V
5
4
3
2
1
0
5
4
3
2
1
0
(3)
(3)
(2)
(1)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
, I = 0 V
DD−0−20 N
(1) I
, I = 0 V
(1) I
DD−0−15
N
(2) I
(3) I
, I = 5 V/1 MHz/50%,
, I = 5 V
N
(2) I
(3) I
, I = 5 V/1 MHz/50%,
N
, I = 5 V
N
DD−50−15
DD−100−15
N
DD−50−20
DD−100−20
(Note: V = 15 V, V = 15 V)
(Note: V = 20 V, V = 15 V)
DD B
DD
B
Figure 10. IDD Supply Current, VDD = 15 V
Figure 11. IDD Supply Current, VDD = 20 V
3.0
2.8
2.6
2.4
7
6
5
4
3
(4)
(4)
(3)
(2)
(3)
(2)
(1)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) I
(4) I
, V = 20 V
, V = 30 V
B
(2) I
(4) I
, V = 20 V
, V = 30 V
B
(1) I
(3) I
, V = 15 V
(1) I
(3) I
, V = 15 V
B
BS−0−20
B
BS−100−20
BS−100−30
B
BS−0−15
BS−0−25
B
BS−100−15
BS−100−25
, V = 25 V
B
, V = 25 V
B
BS−0−30
(Note: V = 5 V, I = LOW, FLT = HIGH)
(Note: V = 5 V, I = HIGH, FLT = HIGH)
DD N
DD
N
Figure 12. IBS Supply Current, VDD = 5 V
Figure 13. IBS Supply Current, VDD = 5 V
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11
NCD57084, NCV57084
55
50
40
30
20
(4)
(1)
45
(2)
(3)
35
(1)
25
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) I
(4) I
(1) I
IN−15
IN−20
IN−5
(3) I
(1) I
IN−3.3
FLT−L
(Note: V = V , V = 15 V)
(Note: FLT = LOW, V = 5 V)
DD
IN
DD BS
Figure 14. Input Current − Logic “1”
Figure 15. FLT = Pull−up Current
2.2
2.0
1.8
1.6
1.4
1.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
(4)
(4)
(3)
(3)
(1)
(2)
(1)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(4) V
(2) V
(4) V
(1) V
(1) V
IH−5
(3) V
IH−15
IL−15
IL−20
IH−3.3
IH−20
IL−5
(3) V
IL−3.3
(Note: V = 15 V)
(Note: V = 15 V)
BS
BS
Figure 16. Low Input Voltage
Figure 17. High Input Voltage
1.0
0.8
0.6
0.4
0.26
0.24
0.22
0.20
0.18
(4)
(3)
(1)
(1)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(4) V
(1) V
(3) V
IN−HYST−3.3
IN−HYST−20
IN−HYST−5
(1) V
IN−HYST−15
FLT−L
(Note: V = 15 V)
(Note: I
= 5 mA)
BS
FLT
Figure 18. Input Hysteresis Voltage
Figure 19. FLT Low Level Output Voltage
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12
NCD57084, NCV57084
20
1.4
1.2
1
(4)
(3)
(2)
(1)
15
0.8
0.6
0.4
0.2
0
(2)
10
(3)
5
0
(1)
−40 −20
0
20
40
60
80
100 120
1
10
100
1000
Temperature (5C)
Frequency (kHz)
(2) V
(4) V
(2) CG = 10 nF
(1) V
(3) V
(1) CG = 1 nF
HOL2
HOH2
HOL1
HOH1
(3) CG = 100 nF
(Note: V = 5 V, V = 15 V)
DD
BS
Figure 20. Output Voltage
Figure 21. IBS vs Switching Frequency
3.0
2.9
2.8
2.7
2.6
2.5
13.0
12.8
12.6
12.4
12.2
12.0
11.8
(1)
(1)
(2)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(2) V
(1) V
(1) V
UVLO2−OUT−ON
UVLO1−OUT−OFF
UVLO2−OUT−OFF
UVLO1−OUT−ON
Figure 22. UVLO1 Threshold Voltage
Figure 23. UVLO2 Threshold Voltage
8.90
8.85
8.80
−7.5
−8.0
−8.5
(1)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) V
(1) V
DESAT−NEG
DESAT−THR
Figure 24. DESAT Threshold Voltage
Figure 25. DESAT Negative Voltage
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13
NCD57084, NCV57084
−0.45
−0.46
−0.47
−0.48
−0.49
−0.50
58
56
54
(1)
(1)
52
50
48
46
44
42
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) I
(1) I
DESAT−DIS
DESAT−CHG
Figure 26. DESAT Blanking Charge Current
Figure 27. DESAT Blanking Discharge Current
1
0.95
0.9
(1)
0.85
0.8
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
(1) V
CLP−HO
Figure 28. IGBT Short Circuit Clamping Voltage
70
68
66
64
62
70
(2)
(1)
(1)
(4)
68
66
64
62
60
(3)
(4)
(3)
(2)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t
(4) t
(2) t
(4) t
(1) t
(3) t
(1) t
(3) t
PD−ON−5
PD−OFF−5
PD−OFF−20
PD−ON−3.3
PD−ON−15
PD−OFF−3.3
PD−OFF−15
PD−ON−20
(Note: C
= 10 nF, V = 15 V)
BS
(Note: C
= 10 nF, V = 15 V)
BS
LOAD
LOAD
Figure 29. High Propagation Delay
Figure 30. Low Propagation Delay
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14
NCD57084, NCV57084
2
1
16
(2)
15.5
(3) (4)
0
(1)
(2)
15
14.5
14
−1
−2
−3
−4
−5
(1)
13.5
13
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
100 120
100 120
Temperature (5C)
Temperature (5C)
(2) t
(4) t
(1) t
(3) t
DISTORT−5
DISTORT−20
DISTORT−3.3
DISTORT−15
(2) t
(1) t
FALL
RISE
(Note: V = 15 V)
(Note: C
1 nF, V = 15 V)
LOAD = BS
BS
Figure 31. Propagation Delay Distortion
Figure 32. Rise / Fall Time
540
520
500
480
460
440
420
400
380
360
340
2.4
2.2
2.0
1.8
1.6
(2)
(1)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
Temperature (5C)
Temperature (5C)
(2) t
(1) t
FILTER
LEB
(1) t
STO
(Note: V = 5 V, V = 15 V)
DD
BS
(Note: V = 5 V, V = 15 V)
DD
BS
Figure 33. DESAT Threshold Filtering Time,
DESAT Leading Edge Blanking Time
Figure 34. Soft Turn Off Time
460
440
420
400
380
1.6
1.5
1.4
1.3
(1)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
Temperature (5C)
Temperature (5C)
(1) t
FLT
(1) t
UV2F
(Note: V = 5 V, V = 15 V)
(Note: V = 5 V, V falls from HI to LOW)
DD BS
DD
BS
Figure 35. FLT Delay Time
Figure 36. UVLO2 Fall Delay
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15
NCD57084, NCV57084
Under Voltage Lockout (UVLO)
UVLO ensures correct switching of IGBT connected to the driver output.
• The IGBT is turned−off and the output is disabled, if the supply V drops below V
or V drops
DD
UVLO1−OUT−OFF
BS
below V
.
UVLO2−OUT−OFF
• The driver output does not follow the input signal on V until the V / V rises above the V
and
IN
DD
BS
UVLOX−OUT−ON
the input signal rising edge is applied to the V .
IN
With high loading gate capacitances over 10 nF it is important to follow the decoupling capacitor routing guidelines as shown
on Figure 37. The decoupling capacitor value should be at least 10 mF. Also gate resistor of minimal value of 2 W has to be
used in order to avoid interference of the high di/dt with internal circuitry (e.g. UVLO2).
After the power-on of the driver there has to be a rising edge applied to the IN in order for the output to start following the
inputs. This serves as a protection against producing partial pulses at the output if the V or V is applied in the middle of
the input PWM pulse.
DD
B
Power Supply (VDD, VBS
)
NCx57084 is designed to support unipolar power supply.
For reliable high output current the suitable external power capacitors required. Parallel combination of 100 nF + 4,7 µF
ceramic capacitors is optimal for a wide range of applications using IGBT. For reliable driving IGBT modules (containing
several parallel IGBT´s) a higher capacity required (typically 100 nF + 10 µF). Capacitors should be as close as possible to
the driver’s power pins.
VDD
IN
VB
HO
10 mF
100 nF
V
DD
V
BS
+
−
+
−
DESAT
VS
FLT
GND
10 mF
100 nF
Figure 37. Power Supply
Desaturation Protection (DESAT)
Desaturation protection ensures the protection of IGBT at short circuit. When the V
voltage goes up and reaches the
CESAT
set limit, the output is driven low and FLT output is activated. Blanking time can be set by internal current source and an external
capacitor. To avoid false DESAT triggering and minimize blanking time, fast switching diodes with low internal capacitance
are recommended. All DESAT protective diodes internal capacitances builds voltage divider with the blanking capacitor.
Warning: Both external protective diodes are recommended for the protection against voltage spikes caused by IGBT transients
passing through parasitic capacitances.
VDESAT*THR
tBLANK + CBLANK
@
IDESAT*CHG
VDESAT*THR u RS*DESAT @ IDESAT*CHG ) VF HV diode ) VCESAT_IGBT
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16
NCD57084, NCV57084
VDC−LINK
HS−IGBT
VDD
VB
UVLO2
V
B
UVLO1
V
DESAT
IN
VS
C
BLANK
R
S−DESAT
HV diode
STO
I
C−LS
LS−IGBT
HO
V
CESAT
R
G
Logic
Logic
VB
VDD
I
DESAT−CHG
+
DESAT
−
FLT
V
DESAT−THR
V
S
VS
GND
Figure 38. DESAT Circuit Parameters Specification
FLOATING
10 μF
+
VB
OUT
DESAT
VS
VDD
IN
5V
+
−
S1
−
OUT must remain stable
FLT
GND
15 V
+
−
10 μF
HV PULSE
(Test Conditions: HV Pulse 1500 V, dV/dt = 1−100 V/ns, VDD = 5 V, VBS = 15 V)
Figure 39. CMTI Test Setup
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17
NCD57084, NCV57084
Figure 40. Recommended Layout
High−speed signals
10 mil s
0.25 mm
10 mil s
0.25 mm
Ground plane
Keep this space free
from traces, pads
40 mil s
1 mm
40 mil s
1 mm
and vias
Power plane
10 mil s
0.25 mm
10 mil s
0.25 mm
Low−speed signals
157 mils
(4 mm)
Figure 41. Recommended Layer Stack
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18
NCD57084, NCV57084
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
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19
NCD57084, NCV57084
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
6. EMITTER, #2
7. BASE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
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