NCD57090D [ONSEMI]
Isolated High Current IGBT/MOSFET Gate Driver;
| 型号： | NCD57090D |
| 厂家： | 
ONSEMI |
| 描述： | Isolated High Current IGBT/MOSFET Gate Driver 栅 双极性晶体管 |
| 文件： | 总25页 (文件大小：1979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated High Current
IGBT/MOSFET Gate Driver
NCx57090y, NCx57091y
(x = D or V, y = A, B, C, D, E or F)
NCx57090y, NCx57091y are high−current single channel
IGBT/MOSFET gate drivers with 5 kVrms internal galvanic isolation,
designed for high system efficiency and reliability in high power
applications. The devices accept complementary inputs and depending
on the pin configuration, offer options such as Active Miller Clamp
(version A/D/F), negative power supply (version B) and separate high
and low (OUTH and OUTL) driver outputs (version C/E) for system
design convenience. The driver accommodate wide range of input
bias voltage and signal levels from 3.3 V to 20 V and they are
available in wide−body SOIC−8 package.
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SOIC8 WB
CASE 751EW
Features
MARKING DIAGRAM
• High Peak Output Current (+6.5 A/−6.5 A)
• Low Clamp Voltage Drop Eliminates the Need of Negative Power
Supply to Prevent Spurious Gate Turn−on (Version A/D/F)
• Short Propagation Delays with Accurate Matching
• IGBT/MOSFET Gate Clamping during Short Circuit
• IGBT/MOSFET Gate Active Pull Down
• Tight UVLO Thresholds for Bias Flexibility
• Wide Bias Voltage Range including Negative V
• 3.3 V, 5 V, and 15 V Logic Input
• 5 kVrms Galvanic Isolation
• High Transient Immunity
• High Electromagnetic Immunity
8
5709zy
ALYW
G
(Version B)
EE2
1
5709zy
= Specific Device Code
z = 0/1
y = A/B/C/D/E/F
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
A
L
Y
W
G
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN CONNECTIONS
See detailed pin connection information on page 2 of this
data sheet.
Typical Applications
• Motor Control
• Uninterruptible Power Supplies (UPS)
• Automotive Applications
• Industrial Power Supplies
• Solar Inverters
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
April, 2021 − Rev. 0
NCD57090A/D
NCx57090y, NCx57091y
PIN CONNECTIONS
V
V
V
IN+
IN−
GND1
GND2
CLAMP
OUT
V
IN+
IN−
DD1
IN+
IN−
GND2
OUTL
OUTH
EE2
DD1
DD1
GND2
OUT
V
GND1
V
DD2
GND1
DD2
V
DD2
NCx57090A, NCx57091A
NCx57090B, NCx57091B
NCx57090C, NCx57091C
V
IN+
IN−
CLAMP
OUT
V
IN+
IN−
V
DD1
IN+
IN−
OUTL
OUTH
DD1
V
OUT
CLAMP
GND2
DD1
DD2
V
DD2
V
DD2
GND1
GND2
GND2
GND1
GND1
NCx57090D
NCx57090E
NCx57090F
NOTE: x = D or V
Figure 1. Pin Connections
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − VERSION A/D/F
V
DD1
V
DD2
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUT
IN+
Logic
Logic
2
GND1
VCLAMP−THR
1
+
−
CLAMP
GND2
2
Figure 2. Simplified Block Diagram, NCD57090A/D/F
V
DD2
V
DD1
V
DD2
V
DD1
IN+
OUT
IN−
CLAMP
GND2
GND1
Figure 3. Simplified Application Schematics, Version A/D/F
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NCx57090y, NCx57091y
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − NCx57090B, NCx57091B
V
DD1
V
DD2
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUT
IN+
V
EE2
Logic
Logic
GND1
1
GND2
2
Figure 4. Simplified Block Diagram, NCx57090B, NCx57091B
V
DD2
V
DD1
V
DD2
V
DD1
IN+
OUT
IN−
GND2
GND1
V
EE2
Figure 5. Simplified Application Schematics, NCx57090B, NCx57091B
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NCx57090y, NCx57091y
BLOCK DIAGRAM AND APPLICATION SCHEMATIC − VERSION C/E
V
DD1
V
DD2
UVLO1
UVLO2
V
DD2
V
DD1
IN−
OUTH
OUTL
IN+
Logic
Logic
GND2
GND1
2
1
Figure 6. Simplified Block Diagram, Version C/E
V
DD1
V
DD2
V
DD2
V
DD1
IN+
OUTH
OUTL
GND2
IN−
GND1
Figure 7. Simplified Application Schematics, Version C/E
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NCx57090y, NCx57091y
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
V
DD1
1
Power
Input side power supply. A good quality bypassing capacitor is required from this pin to GND1
and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power on when
a typical supply voltage higher than V
is present.
UVLO1−OUT−ON
Please see Figures 9A and 9B for more details.
IN+
2
3
I
I
Non inverted gate driver input. It is internally clamped to V
and has an equivalent
DD1
pull−down resistor of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative pulse−width is required at IN+ before OUT or OUTH/OUTL
responds.
IN−
Inverted gate driver input. It is internally clamped to V
and has an equivalent pull−up
DD1
resistor of 50 kW to ensure that output is low in the absence of an input signal. A minimum
positive or negative pulse−width is required at IN− before OUT or OUTH/OUTL responds.
GND1
4
5
Power
Power
Input side ground reference.
V
DD2
Output side positive power supply. The operating range for this pin is from UVLO2 to its
maximum allowed value. A good quality bypassing capacitor is required from this pin to GND2
and should be placed close to the pins for best results.
The under voltage lockout (UVLO) circuit enables the device to operate at power on when
a typical supply voltage higher than V
for more details.
is present. Please see Figure 9C and 9D
UVLO2−OUT−ON
GND2
(NCD57090A,
NCD57090C)
8
Power
Output side gate drive reference connecting to IGBT emitter or MOSFET source.
GND2
7
5
(NCD57090B)
GND2
(NCD57090D,
NCD57090E,
NCD57090F)
OUT
(NCD57090A,
NCD57090B)
6
7
O
Driver output that provides the appropriate drive voltage and source/sink current to the IGBT/
MOSFET gate. OUT is actively pulled low during start−up.
OUT
(NCD57090D,
NCD57090F)
OUTH
6
7
7
8
7
8
6
8
O
O
O
Driver high output that provides the appropriate drive voltage and source current to the IGBT/
MOSFET gate.
(NCD57090C)
OUTH
(NCD57090E)
OUTL
(NCD57090C)
Driver low output that provides the appropriate drive voltage and sink current to the IGBT/
MOSFET gate. OUTL is actively pulled low during start−up.
OUTL
(NCD57090E)
CLAMP
(NCD57090A)
Provides clamping for the IGBT/MOSFET gate during the off period to protect it from parasitic
turn−on. Its internal N FET is turned on when the voltage of this pin falls below V
.
CLAMP−THR
It is to be tied directly to IGBT/MOSFET gate with minimum trace length for best results.
CLAMP
(NCD57090D)
CLAMP
(NCD57090F)
V
EE2
Power
Output side negative power supply. A good quality bypassing capacitor is required from this pin
to GND2 and should be placed close to the pins for best results.
(NCD57090B)
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NCx57090y, NCx57091y
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Value
I − IV
I − IV
I − IV
I − IV
I − III
600
Unit
Installation Classifications per DIN VDE 0110/1.89
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
Table 1 Rated Mains
Voltage
< 1000 V
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
V
Input−to−Output Test Voltage, Method b, V
× 1.875 = V
,
2250
V
V
PR
IORM
PR
pk
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
Maximum Repetitive Peak Voltage
Maximum Working Voltage
V
IORM
1200
870
8400
8.0
pk
V
IOWM
V
RMS
V
IOTM
Highest Allowable Over Voltage
External Creepage
V
pk
E
CR
mm
mm
mm
°C
E
External Clearance
8.0
CL
DTI
Insulation Thickness
17.3
150
121
1349
T
Case
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
P
mW
mW
W
S,INPUT
P
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
10
IO
IO
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1)
Over operating free−air temperature range unless otherwise noted.
Symbol
Parameter
Minimum
−0.3
−0.3
−18
Maximum
Unit
V
V
V
−GND1
Supply Voltage, Input Side
22
32
0.3
36
DD1
DD2
−GND2
−GND2
Positive Power Supply, Output Side
V
V
Negative Power Supply, Output Side
V
EE2
V
−V
MAX2
Differential Power Supply, Output Side (NCD57090B)
0
V
DD2
EE2
(V
)
Gate−driver Output High Voltage
NCD57090A/B/D/F
V
V
A
A
A
V
OUTH
−GND2
−
−
V
+ 0.3
OUT
DD2
V
−GND2
NCD57090C/E
−
Gate−driver Output Low Voltage
NCD57090A/B/D/F
NCD57090C/E
V
OUTL
−GND2
−GND2
−0.3
−
−
−
OUT
V
I
Gate−driver Output Sourcing Current
−
−
−
6.5
6.5
2.5
10
PK−SRC
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
DD2
= 15 V, V
= 0 V)
EE2
I
Gate−driver Output Sinking Current
PK−SNK
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
DD2
= 15 V, V
= 0 V)
EE2
I
Clamp Sinking Current
PK−CLAMP
(maximum pulse width = 10 ms, maximum duty cycle = 0.2%,
V
= 2.5 V)
CLAMP
t
Maximum Short Circuit Clamping Time (I
= 500 mA)
OUT_CLAMP
−
−0.3
−0.3
−
ms
V
CLP
V
−GND1
Voltage at IN+, IN−
V
DD1
V
DD2
+ 0.3
LIM
V
−GND2
Clamp Voltage
+ 0.3
V
CLAMP
P
D
Power Dissipation (SOIC−8 Wide Package)
1470
mW
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NCx57090y, NCx57091y
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) (continued)
Over operating free−air temperature range unless otherwise noted.
Symbol Parameter
T (max) Maximum Junction Temperature
Minimum
Maximum
Unit
°C
°C
kV
kV
−
−40
−65
−
150
150
2
J
T
STG
Storage Temperature Range
ESDHBM
ESDCDM
MSL
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Moisture Sensitivity Level
−
2
−
1
T
SLD
Lead Temperature Soldering Reflow, Pb−Free (Note 3)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Unit
RqJA
Thermal Characteristics, SOIC−8 wide body (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
156 (1−Layer)
85 (4−Layer)
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 5. OPERATING RANGES (Note 6)
Symbol
Parameter
Supply Voltage, Input Side
Min
UVLO1
UVLO2
−15
Max
20
30
0
Unit
V
V
V
−GND1
DD1
DD2
−GND2
−GND2
Positive Power Supply, Output Side
V
V
Negative Power Supply, Output Side (NCD57090B)
Differential Power Supply, Output Side (NCD57090B)
Low Level Input Voltage at IN+, IN− (Note 7)
High Level Input Voltage at IN+, IN− (Note 7)
Common Mode Transient Immunity (Note 8)
Ambient Temperature
V
EE2
V
−VEE2 (V
)
0
32
V
DD2
MAX2
V
IL
0
0.3 × V
V
DD1
DD1
V
IH
0.7 × V
V
V
DD1
|dV /dt|
100
125
kV/ms
°C
ISO
TA
−40
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
7. Table values are valid for 3.3 V and 5 V VDD1, for higher VDD1 voltages, the threshold values are maintained at the 5 V VDD1 levels.
8. Was tested by 1500 V pulses up to 100 kV/ms.
Table 6. ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
Value
Unit
V
Input−Output Isolation
Voltage
T = 25°C, Relative Humidity < 50%,
5000
V
RMS
ISO, input−output
A
t = 1.0 minute, I
< 30 mA, 50 Hz
I−O
(Note 9, 10, 11)
11
R
Isolation Resistance
V
I−O
= 500 V (Note 9)
10
W
ISO
9. Device is considered a two−terminal device: pins 1 to 4 are shorted together and pins 5 to 9 are shorted together.
10.5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
11. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table.
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NCx57090y, NCx57091y
ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57090B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
V
UVLO1 Output Enabled
UVLO1 Output Disabled
UVLO1 Hysteresis
−
2.4
0.1
12.4
8.7
11.5
7.7
0.7
−
−
−
3.1
−
V
V
UVLO1−OUT−ON
V
UVLO1−OUT−OFF
V
−
−
V
UVLO1−HYST
V
UVLO2 Output Enabled
NCx57090y
12.9
9
13.4
9.3
12.5
8.3
−
V
UVLO2−OUT−ON
NCx57091y
NCx57090y
NCx57091y
V
V
UVLO2 Output Disabled
12
8
V
UVLO2−OUT−OFF
V
V
UVLO2 Hysteresis
1
V
UVLO2−HYST
I
Input Supply Quiescent Current
IN+ = Low, IN− = Low, V
IN+ = Low, IN− = Low
IN+ = Low, IN− = Low, V
IN+ = High, IN− = Low
= 3.3 V
= 15 V
−
2
mA
mA
mA
mA
mA
mA
mA
DD1−0−3.3
DD1
I
−
−
2
DD1−0−5
I
−
−
2
DD1−0−15
DD1
I
−
−
5.5
2
DD1−100−5
I
Output Positive Supply
Quiescent Current
IN+ = Low, IN− = Low, no load
IN+ = High, IN− = Low, no load
IN+ = Low, IN− = Low, no load,
−
−
DD2−0
I
−
−
2
DD2−100
I
Output Negative Supply
Quiescent Current (NCD57090B)
−
−
2
EE2−0
V
EE2
= −8 V
I
IN+ = High, IN− = Low, no load, V
= −8 V
−
−
2
mA
EE2−100
EE2
LOGIC INPUT AND OUTPUT
V
IN+, IN−, Low Input Voltage
IN+, IN−, High Input Voltage
Input Hysteresis Voltage
IN− Input Current
Level scale for V
= 3.3 to 5 V
−
−
−
0.3 ×
V
V
V
IL
DDI
for V
> 5 V is the same as for
V
DD1
DDI
= 5 V
V
DDI
V
IH
Level scale for V
= 3.3 to 5 V
0.7 ×
V
DD1
−
DDI
for V
> 5 V is the same as for
DDI
V
= 5 V
DDI
V
Level scale for V
= 3.3 to 5 V
−
0.15 ×
V
DD1
−
IN−HYST
DDI
for V
> 5 V is the same as for
DDI
V
DDI
V
IN−
V
IN−
V
IN−
V
IN−
V
IN+
V
IN+
V
IN+
V
IN+
= 5 V
I
= 0 V, V
= 0 V
= 3.3 V
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
100
100
100
100
100
100
100
10
mA
mA
mA
mA
mA
mA
mA
mA
ns
IN−L−3.3
DD1
I
IN−L−5
I
= 0 V, V
= 0 V, V
= 15 V
= 20 V
IN−L−15
IN−L−20
DD1
DD1
I
I
IN+ Input Current
= V
= V
= V
= V
= 3.3 V
= 5 V
IN+H−3.3
DD1
DD1
DD1
DD1
I
IN+H−5
I
= 15 V
= 20 V
IN+H−15
IN+H−20
I
t
Input Pulse Width of IN+, IN− for
Guaranteed No Response at
Output
ON−MIN1
t
Input Pulse Width of IN+, IN− for
Guaranteed Response at Output
40
−
−
ns
ON−MIN2
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NCx57090y, NCx57091y
ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57090B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
Parameter
Test Conditions
Min
Typ
0.15
−
Max
Unit
DRIVER OUTPUT
V
V
Output Low State
(V – GND2 for
NCD57090A/D/F)
I
I
I
I
= 200 mA
−
0.3
V
OUTL1
OUTL2
OUTH1
OUTH2
SINK
SINK
SRC
SRC
OUT
(V
(V
– V
for NCD57090B)
OUT
OUTL
EE2
= 1.0 A, T = 25°C
−
0.8
A
– GND2 for
NCD57090C/E)
V
V
Output High State
= 200 mA
−
0.2
−
0.35
1.0
V
(V
DD2
– V
for
OUT
NCD57090A/B/D/F)
(V
DD2
(V
DD2
– V
– V
for NCD57090B)
OUTL
OUT
= 1.0 A, T = 25°C
−
A
for
NCD57090C/E)
I
Peak Driver Current, Sink
(Note 12)
−
−
6.5
6.5
−
−
A
A
PK−SNK1
I
Peak Driver Current, Source
(Note 12)
PK−SRC1
MILLER CLAMP (NCD57090A)
V
Clamp Voltage
I
I
= 2.5 A, T = 25°C
−
−
2
−
V
CLAMP
CLAMP
A
= 2.5 A,
T = −40°C to 125°C
−
3.5
CLAMP
A
V
Clamp Activation Threshold
1.5
2
2.5
0.9
V
V
CLAMP−THR
IGBT SHORT CIRCUIT CLAMPING
V
Clamping Voltage, Sourcing
IN+ = Low, IN− = High,
−
0.7
CLAMP−OUTH
(V / V – V
)
I
= 500 mA,
OUT
OUTH
DD2
CLAMP−OUT/OUTH
(pulse test, t
= 10 ms)
CLPmax
V
Clamping Voltage, Sinking
(V − V
IN+ = High, IN− = Low,
I = 500 mA,
CLAMP−OUTL
−
−
0.8
1.1
1.5
1.7
V
V
CLAMP−OUTL
)
OUTL
DD2
(pulse test, t
= 10 ms)
CLPmax
V
Clamping Voltage, Clamp
(V − V
IN+ = High, IN− = Low,
I = 500 mA
CLAMP−CLAMP
CLAMP−CLAMP
)
CLAMP
DD2
(NCD57090A/D/F)
(pulse test, t
= 10 ms)
CLPmax
DYNAMIC CHARACTERISTIC
IN+, IN− to Output High
Propagation Delay
C
IH
= 10 nF
−
−
−
−
LOAD
V
to 10% of output change
Pulse Width > 150 ns.
t
V
V
V
V
= V
= V
= V
= V
= 3.3V, V = 0 V
IN−
40
40
40
40
−
60
60
60
60
−
90
90
90
90
−
ns
ns
ns
ns
−
PD−ON−3.3
DD1
DD1
DD1
DD1
IN+
IN+
IN+
IN+
t
= 5 V, V
= 0 V
PD−ON−5
IN−
t
= 15 V, V
= 20 V, V
= 0 V
= 0 V
PD−ON−15
PD−ON−20
IN−
t
IN−
IN+, IN− to Output Low
Propagation Delay
C
= 10 nF
LOAD
to 10% of output change
V
IH
Pulse Width > 150 ns.
t
V
V
V
V
= V
= V
= V
= V
= 3.3 V, V
= 0 V
40
40
60
60
60
60
0
90
90
90
90
−
ns
ns
ns
ns
ns
ns
ns
PD−OFF−3.3
DD1
DD1
DD1
DD1
IN+
IN+
IN+
IN+
IN−
t
= 5 V, V
= 0 V
PD−OFF−5
IN−
t
= 15 V, V
= 20 V, V
= 0 V
= 0 V
40
PD−OFF−15
PD−OFF−20
IN−
t
40
IN−
t
Propagation Delay Distortion
T = 25°C, PW > 150 ns
A
−
DISTORT
(= t
− t
)
PD−ON
PD−OFF
T = −40°C to 125°C, PW > 150 ns
A
−25
−30
−
25
30
t
Prop Delay Distortion between
Parts
PW > 150 ns
0
DISTORT_TOT
t
Rise Time (see Figure 8)
C
= 1 nF,
LOAD
−
13
−
ns
RISE
10% to 90% of Output Change
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9
NCx57090y, NCx57091y
ELECTRICAL CHARACTERISTICS V
= 5 V, V
= 15 V, (V
= 0 V for NCD57090B).
DD1
DD2
EE2
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
DYNAMIC CHARACTERISTIC
Parameter
Test Conditions
Min
Typ
Max
Unit
t
Fall Time (see Figure 8)
C
= 1 nF,
LOAD
−
13
−
ns
FALL
90% to 10% of Output Change
t
UVLO1 Fall Delay (Note 12)
−
−
1500
770
−
−
−
−
ns
ns
ns
ns
UVF1
UVR1
t
UVLO1 Rise Delay (Note 12)
UVLO2 Fall Delay (Note 12)
UVLO2 Rise Delay (Note 12)
t
−
1000
1000
UVF2
UVR2
t
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
12.Values based on design and/or characterization.
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10
NCx57090y, NCx57091y
V
IH
V
IL
IN+
t
t
t
FALL
ON−MIN1
RISE
t
ON−MIN2
90%
t
PD−ON
t
ON−MIN1
t
PD−OFF
OUT/OUTH
10%
Figure 8. Propagation Delay, Rise and Fall time
V
DD2
V
UVLO1−HYST
V
V
UVLO1−OUT−ON
UVLO1−OUT−OFF
V
DD1
t
t
t
t
UVR1
t
t
UVR1−spread
UVF1
UVF1
UVR1
UVR2
IN+
OUT/OUTH
Output Ramp−up and Ramp−down Times during UVLO1
Figure 9A. UVLO1 and Associated Timing Waveforms
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11
NCx57090y, NCx57091y
V
DD2
V
V
UVLO1−OUT−ON
UVLO1−OUT−OFF
V
DD1
t
t
t
t
t
UVR1
t
UVR1
UVF1
UVF1
UVR1
UVR1−spread
IN+
OUT/OUTH
V
DD1
Glitch Filtering
Figure 9B. UVLO1 Waveforms Depicting VDD1 Glitch Filtering
V
DD1
V
UVLO2−HYST
V
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
DD2
t
t
t
t
UVF2
t
UVR2
UVF2
UVR2
t
UVR2
UVR2−spread
IN+
OUT/OUTH
Output Ramp−up and Ramp−down Times during UVLO2
Figure 9C. UVLO2 and Associated Timing Waveforms
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12
NCx57090y, NCx57091y
V
DD1
V
V
UVLO2−OUT−ON
UVLO2−OUT−OFF
V
DD2
t
t
t
t
t
UVR2
UVR2
UVF2
UVR2
UVR2
t
UVR2−spread
IN+
OUT/OUTH
V
DD2
Glitch Filtering
Figure 9D. UVLO2 Waveforms Depicting VDD2 Glitch Filtering
V
DD1
Clamping
Circuit
IN+
V
V
DD1 DD1
Clamping
Circuit
IN−
Figure 10. Input Pin Structure
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13
NCx57090y, NCx57091y
TYPICAL CHARACTERISTICS
6
5
4
3
2
1
0
5
(3)
(2)
(3)
4
3
(2)
2
(1)
(1)
1
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
DD1−0−3.3
Temperature [°C]
DD1−0−5
(1) I
(2) I
(3) I
(1) I
(2) I
(3) I
, IN+ = 3.3 V/200 kHz/50%
, IN+ = 5 V/200 kHz/50%
DD1−50−3.3
DD1−50−5
DD1−100−3.3
DD1−100−5
Figure 11. IDD1 Supply Current VDD1 = 3.3 V
Figure 12. IDD1 Supply Current VDD1 = 5 V
20
15
10
5
5
4
3
2
1
0
(3)
(3)
(2)
(1)
(2)
(1)
0
−40 −20
0
20
40
60
80
100 120
1
10
100
Frequency [kHz]
1000
Temperature [°C]
(1) C = 1 nF
(1) I
(2) I
(3) I
G
DD1−0−20
, IN+ = 20 V/200 kHz/50%
(2) C = 10 nF
DD1−50−20
G
(3) C = 100 nF
DD1−100−20
G
Figure 13. IDD1 Supply Current VDD1 = 20 V
Figure 14. IDD2 vs. Switching Frequency
2.5
2.5
2
(2)
(1)
2
1.5
1
1.5
1
(2)
(1)
0.5
0
0.5
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
(1) I
(2) I
(1) I
DD2−0−30
DD2−0−15
(2) I
DD2−100−15
DD2−100−30
Figure 15. IDD2 Supply Current VDD2 = 15 V
Figure 16. IDD2 Supply Current VDD2 = 30 V
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14
NCx57090y, NCx57091y
TYPICAL CHARACTERISTICS (continued)
1.5
1.4
2.9
2.8
2.7
2.6
(2)
(1)
1.3
1.2
1.1
1
(1)
(2)
0.9
0.8
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
(1) V
(2) V
(1) V
(2) V
UVLO1−OUT−ON
CLAMP−OUTH
CLAMP−CLAMP
UVLO1−OUT−OFF
Figure 17. UVLO1 Threshold Voltage
Figure 18. IGBT Short Circuit CLAMP
Voltage Drop
3
2.5
2
2.00
1.98
1.96
1.94
1.5
1
1.92
1.90
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
Figure 19a. Miller Clamp Voltage (2.5 A)
Figure 19b. Miller Clamp Activation
Voltage Threshold
13.5
13
9.5
9
(1)
(2)
(1)
12.5
8.5
(2)
12
8
11.5
7.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
(1) V
(2) V
(1) V
(2) V
UVLO2−OUT−ON
UVLO2−OUT−OFF
UVLO2−OUT−ON
UVLO2−OUT−OFF
Figure 20. NCx57090 UVLO2 Threshold Voltage
Figure 21. NCx57091 UVLO2 Threshold Voltage
www.onsemi.com
15
NCx57090y, NCx57091y
TYPICAL CHARACTERISTICS (continued)
72
70
68
66
64
62
71
69
(1)
(2)
(1)
67
(2)
65
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
(1) t
(2) t
, IN+
, IN−
(1) t
, IN+
, IN−
PD−ON−5
PD−OFF−5
(2) t
PD−ON−5
PD−OFF−5
Figure 22. Propagation Delay Turn−on
Figure 23. Propagation Delay Turn−off
15
14
13
12
14
13
(1)
(2)
(1)
(2)
12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Temperature [°C]
(1) t
(2) t
, IN+
, IN−
(1) t
(2) t
, IN+
, IN−
RISE
FALL
RISE
FALL
Figure 24. Rise Time, VDD1 = 5 V
Figure 25. Fall Time, VDD1 = 5 V
−35
50
40
30
20
(1)
(2)
−35
−40
(3)
(4)
(2)
−45
−50
−55
−60
(3)(4)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
(1) I
(2) I
(3) I
(4) I
(1) I
(2) I
(3) I
(4) I
IN+H−3.3
IN−L−3.3
IN+H−5
IN−L−5
IN+H−15
IN+H−20
IN−L−15
IN−L−20
Figure 26. Input Current – Positive Input
Figure 27. Input Current – Negative Input
www.onsemi.com
16
NCx57090y, NCx57091y
Under Voltage Lockout (Refer to Figure 9x)
UVLO ensures correct switching of IGBT/MOSFET
connected to the driver output.
of minimal value of 2 W has to be used in order to avoid
interference of the high di/dt with internal circuitry (e.g.
UVLO2).
After the power−on of the driver there has to be a rising
edge applied to the IN+ or falling edge to the IN− in order
for the output to start following the inputs. This serves as a
protection against producing partial pulses at the output if
• The IGBT/MOSFET is turned−off and the output is
disabled if the supply V
drops below
drops below
DD1
DD2
V
V
or V
UVLO1−OUT−OFF
.
UVLO2−OUT−OFF
• The driver output does not follow the input signal on
the V
or V
is applied in the middle of the input PWM
DD1
DD2
IN+ or IN− until the V rises above the
DDX
pulse.
If the V
V
and the input signal rising edge is
UVLOX−OUT−ON
rises over V
level the PWM
UVLO2−OUT−ON
DD2
applied to the IN+ or IN−
will appear on the output after t
+ t
. The
UVR2
UVR2−spread
• V
is not monitored (NCx5709zB)
EE2
t
time is variable and is defined as a time from
UVR2−spread
end of t
to first rising edge on IN+ input. If the V
UVR2
DD2
With high loading gate capacitances over 10 nF it is
important to follow the decoupling capacitor routing
guidelines as shown on Figure 35/36. The decoupling
capacitor value should be at least 10 mF. Also gate resistor
is starting from 0 V the time until PWM is at the output of
the driver is longer than t + t . This is caused
by start up time of internal circuits of the driver.
UVR2 UVR2−spread
www.onsemi.com
17
NCx57090y, NCx57091y
ACTIVE MILER CLAMP PROTECTION (CLAMP)
NCx5709yB supports bipolar power supply to prevent
unintentional turning on.
For operation with unipolar supply, typically,
V = 15 V with respect to GND2, and V = GND2. In
DD2
EE2
For operation with bipolar supplies, the IGBT/MOSFET
is turned off with a negative voltage through OUT with
respect to its emitter. This prevents the IGBT/MOSFET
from unintentionally turning on because of current induced
from its collector to its gate due to Miller effect. Typical
this case, the IGBT/MOSFET can turn on due to additional
charge from IGBT/MOSFET Miller capacitance caused by
a high voltage slew rate transition on the IGBT collector/
MOSFET drain. To prevent IGBT/MOSFET to turn on, the
CLAMP pin is connected directly to IGBT/MOSFET gate
and Miller current is sinked through a low impedance
CLAMP transistor. When the IGBT/MOSFET is turned−off
values for bipolar operation are V
V with respect to GND2.
= 15 V and V
= −5
DD2
EE2
Driver version A/D/F supports unipolar power supply
with active Miller clamp.
and the gate voltage transitions below V
output is activated.
, the CLAMP
CLAMP
OUT/OUTH
OUT/OUTH
Figure 28. Current Path with Miler Clamp Protection
Figure 29. Current Path without Miler Clamp Protection
Non−inverting and Inverting Input Pin (IN+, IN−)
The driver has two possible input modes to control
IGBT/MOSFET. Both inputs have defined minimum input
pulse width to filter occasional glitches.
WARNING: When the application uses an independent
or separate power supply for the control
unit and the input side of the driver, all
inputs should be protected by a serial
resistor (In case of a power failure of the
driver, the driver may be damaged due to
overloading of the input protection circuits)
• Non−inverting input IN+ controls the driver output
while inverting input IN− is set to LOW
• Inverting input IN− controls the driver output while
non−inverting input IN+ is set to HIGH
www.onsemi.com
18
NCx57090y, NCx57091y
Power Supply (VDD1, VDD2, VEE2
The driver variant A/C/D/E and F are designed to support
unipolar power supply.
The driver variant B is designed to support bipolar power
supply.
)
• In bipolar power supply the driver is typically supplied
with a positive voltage of 15 V at V and negative
DD2
voltage −5 V at V
(Figure 30). Negative power supply
EE2
prevents a dynamic turn on through the internal
IGBT/MOSFET input capacitance
Suitable external power capacitors are required for
reliable driving of IGBT/MOSFET gate with high current.
Parallel combination of 100 nF + 4.7 mF low ESR ceramic
capacitors is optimal for a wide range of applications using
IGBT/MOSFET. For reliable driving of IGBT modules
(containing several parallel IGBT’s) with a gate capacitance
over 10 nF a higher decoupling capacity is required
(typically 100 nF + 10 mF). Capacitors should be as close as
possible to the driver’s power pins. The recommended
layout is provided in the Figure 35 and 36.
• In Unipolar power supply the driver is typically supplied
with a positive voltage of 15 V at V
. Unwanted
DD2
turn−on caused by the internal IGBT/MOSFET Miller
capacitance could be prevented by Active Miler Clamp
function (variant A/D/F). CLAMP output should be
directly connected to IGBT/MOSFET gate (Figure 28)
V
V
EE2
DD1
V
IN+
IN−
GND2
OUT
10 mF
DD1
100nF
V
EE2
−
+
+
−
10mF
GND1
V
DD2
100nF
V
10mF
100nF
DD2
+
−
Figure 30. Bipolar Power Supply (Variant B)
V
GND2
CLAMP
OUT
DD1
V
DD1
IN+
+
−
IN−
100nF
10mF
V
DD2
GND1
V
DD2
10mF
100nF
+
−
Figure 31. Unipolar Power Supply (Variant A/D/F)
V
DD1
GND2
OUTL
V
DD1
IN+
+
−
OUTH
IN−
100nF
10mF
V
DD2
GND1
V
DD2
10 mF
100nF
+
−
Figure 32. Unipolar Power Supply (Variant C/E)
www.onsemi.com
19
NCx57090y, NCx57091y
Common Mode Transient Immunity (CMTI)
10μF
+
VDD1
IN+
GND2
CLAMP
OUT
5V
+
S1
OUT must remain stable
-
-
IN-
GND1
VDD2
15V
+
-
10μF
HV PULSE
FLOATING
10μF
5V
+
VDD1
IN+
GND2
OUTL
OUTH
VDD2
+
-
S1
OUT must remain stable
-
IN-
GND1
15V
+
-
10μF
HV PULSE
FLOATING
10μF
+
VDD1
IN+
VEE2
GND2
OUT
5V
+
-
S1
-
IN-
OUT must remain stable
GND1
VDD2
15V
+
10μF
-
HV PULSE
FLOATING
Figure 33. Common−Mode Transient Immunity Test Circuit
High-speed signals
Ground plane
10 mils
0.25 mm
10 mils
0.25 mm
Keep this space free
40 mils
1 mm
40 mils
1 mm
from traces, pads and
vias
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low-speed signals
314 mils
(8 mm)
Figure 34. Recommended Layer Stack
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20
NCx57090y, NCx57091y
Figure 35. Recommended Layout for Version A/B/C
www.onsemi.com
21
NCx57090y, NCx57091y
Figure 36. Recommended Layout for Version D/E/F
www.onsemi.com
22
NCx57090y, NCx57091y
ORDERING INFORMATION
Device
†
Package
Shipping
NCD57090ADWR2G
2500 / Tape & Reel
SOIC−8 Wide Body
(Pb−Free)
NCD57090BDWR2G
NCD57090CDWR2G
NCD57090DDWR2G
NCD57090EDWR2G
NCD57090FDWR2G
NCV57090ADWR2G*
NCV57090BDWR2G*
2500 / Tape & Reel
SOIC−8 Wide Body
(Pb−Free)
NCV57090CDWR2G*
NCV57090DDWR2G*
NCV57090EDWR2G*
NCV57090FDWR2G*
NCD57091ADWR2G (In Development)
NCD57091BDWR2G (In Development)
NCD57091CDWR2G (In Development)
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8 Wide Body
(Pb−Free)
NCV57091ADWR2G* (In Development)
NCV57091BDWR2G* (In Development)
NCV57091CDWR2G* (In Development)
SOIC−8 Wide Body
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
23
NCx57090y, NCx57091y
PACKAGE DIMENSIONS
SOIC8 WB
CASE 751EW
ISSUE A
q
q
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24
NCx57090y, NCx57091y
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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