NCD57200DR2G [ONSEMI]
Half Bridge Gate Driver (Isolated High Side & Non-Isolated Low Side);
| 型号： | NCD57200DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Half Bridge Gate Driver (Isolated High Side & Non-Isolated Low Side) 栅 |
| 文件： | 总18页 (文件大小：1583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Half Bridge Gate Driver
(Isolated High &
Non-Isolated Low)
8
1
SOIC- 8 NB
CASE 751- 07
NCD57200
The NCD57200 is a high voltage gate driver with one non-isolated
low side gate driver and one galvanically isolated high or low side gate
driver. It can directly drive two IGBTs in a half bridge configuration.
Isolated high side driver can be powered with an isolated power supply
or with Bootstrap technique from the low side power supply.
The galvanic isolation for the high side gate driver guarantees
reliable switching in high power applications for IGBTs that operate
up to 800 V, at high dv/dt. The optimized output stages provide a mean
of reducing IGBT losses. Its features include two independent inputs
with deadtime and interlock, accurate asymmetric UVLOs, and short
and matched propagation delays. The NCD57200 operates with its
VDD/VBS up to 20 V.
MARKING DIAGRAM
8
NCD57200
ALYWX
G
1
NCD57200
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb- Free Package
Features
High Peak Output Current (+1.9 A/-2.3 A)
Low Output Voltage Drop for Enhanced IGBT Conduction
Floating Channel for Bootstrap Operation up to +800 V
CMTI up to 100 kV/ms
PIN CONNECTIONS
VDD
HIN
VB
Reliable Operation for V Negative Swing to -800 V
S
HO
VS
VDD & VBS Supply Range up to 20 V
3.3 V, 5 V, and 15 V Logic Input
LIN
Asymmetric Under Voltage Lockout Thresholds for High Side and
Low Side
GND
LO
Matched Propagation Delay 90 ns
Built-in 20 ns Minimum Pulse Width Filter (or Input Noise Filter)
Built-in 340 ns Dead-Time and High and Low Inputs Interlock
Non- Inverting Output Signal
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
This Device is Pb-Free, Halogen Free/BFR Free and is RoHS
Compliant
Typical Applications
Fans, Pumps
Home Appliances
Consumer Electronics
General Purpose Half Bridge Applications
Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
November, 2022 - Rev. 2
NCD57200/D
NCD57200
V
B
V
DD
V
DD
UVLO2
HO
Minimum
Pulse
Width
Input
Logic
Output
Logic
HIN
V
S
Deadtime
and
Interlock
V
DD
UVLO1
LO
Minimum
Pulse
Width
Matching
Delay
LIN
GND
Figure 1. Simplified Block Diagram
V
DD
V
DD
V
B
HIN
LIN
HO
V
S
GND
LO
Figure 2. Simplified Application Schematics
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NCD57200
Table 1. FUNCTION DESCRIPTION
Pin Name
No.
I/O
Description
V
1
Power
Low side and main power supply. A good quality bypassing capacitor is required
from this pin to GND and should be placed close to the pins for best results.
DD
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than V
is present. Please
UVLO1- OUT- ON
see Figure 5 for more details. A filter time t
pin.
helps to suppress noise on V
UVF1
DD
HIN
LIN
2
3
I
I
High side non-inverting gate driver input. It has an equivalent pull- down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at HIN before HO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to V
.
DD
There is deadtime and interlocking logic between HIN and LIN.
Low side non-inverting gate driver input. It has an equivalent pull- down resistor
of 125 kW to ensure that output is low in the absence of an input signal.
A minimum positive or negative going pulse width is required at LIN before LO
reacts.
It adopts 3.3 V logic signal thresholds for input voltage up to V
.
DD
There is deadtime and interlocking logic between HIN and LIN.
GND
LO
4
5
Power
O
Logic ground and low side driver return.
Low side driver output that provides the appropriate drive voltage and source/
sink current to the IGBT gate. LO is actively pulled low during startup and under
UVLO1 condition. There is deadtime and interlocking logic to prevent unintended
HO and LO cross conduction.
V
6
7
Power
O
Bootstrap return or high side floating supply offset.
S
HO
Galvanically isolated high side driver output that provides the appropriate drive
voltage and source/sink current to the IGBT gate. HO is actively pulled low
during startup and under UVLOx condition. There is deadtime and interlocking
logic to prevent unintended HO and LO cross conduction.
V
B
8
Power
Bootstrap or high side floating power supply. A good quality bypassing capacitor
is required from this pin to V and should be placed close to the pins for best
S
results.
The under voltage lockout (UVLO) circuit enables the device to operate at power
on when a typical supply voltage higher than V
is present. Please
UVLO2- OUT- ON
see Figure 5 for more details. A filter time t
pin.
helps to suppress noise on V
UVF2
B
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Min
-
Typ
Max
Unit
Installation Classifications per DIN VDE 0110/1.89
Table 1 Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RMS
RMS
RMS
RMS
-
-
-
< 1000 V
-
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Maximum Working Insulation Voltage
External Creepage
600
800
4.0
4.0
8.65
150
75
1335
V
IORM
V
PK
E
CR
mm
mm
mm
C
E
External Clearance
CL
DTI
Insulation Thickness
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
T
Case
P
mW
mW
W
S,INPUT
P
S,OUTPUT
9
R
IO
Insulation Resistance at TS, V = 500 V
IO
10
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NCD57200
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free- air temperature range unless otherwise noted
Parameter
High- Side Offset Voltage (see Figure 2)
High- Side Supply Voltage (see Figure 2)
Symbol
Minimum
- 900
Maximum
900
Unit
V
V
S
B
V
- 900
900
V
Low- Side Supply Voltage
V
V
- 0.3
- 0.3
25
25
V
V
DD
BS
HO
High- Side Floating Supply Voltage
V
V
V
+0.3
BS
+0.3
DD
+0.3
DD
High- Side Output Voltage (HO) (see Figure 2)
Low- Side Output Voltage (LO)
V
V - 0.3
S
V
V
V
- 0.3
- 0.3
LO
Logic Input Voltage (HIN, LIN)
V
V
IN
Allowable Offset Voltage Slew Rate (see Figure 32)
dV /dt
S
100
150
150
±4
V/ns
C
C
kV
kV
-
Maximum Junction Temperature
TJ(max)
TSTG
- 40
- 65
Storage Temperature Range
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
Moisture Sensitivity Level
ESDHBM
ESDCDM
MSL
±2
1
Lead Temperature Soldering Reflow
(SMD Styles Only), Pb Free Versions (Note 3)
TSLD
260
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC- Q100- 002 (EIA/JESD22- A114).
ESD Charged Device Model tested per AEC- Q100- 011 (EIA/JESD22- C101).
Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78, 125C.
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Parameter
Symbol
Value
Unit
Thermal Characteristics, SOIC- 8 (Note 4)
Thermal Resistance, Junction- to- Air (Note 5)
C/W
167
RÒJA
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 100 mm2 (or 0.16 in2) of 1 oz copper thickness and FR4 PCB substrate.
Table 5. RECOMMENDED OPERATING RANGES (Note 6)
Parameter
High- Side Floating Supply Voltage
High- Side Offset Voltage (see Figure 2)
High- Side Output Voltage (HO) (see Figure 2)
Low- Side Output Voltage (LO)
Logic Input Voltage (HIN, LIN)
Symbol
Min
Max
Unit
V
V
BS
V +UVLO2
S
V +20
S
V
- 800
800
V
S
V
HO
V
V
V
S
BS
DD
DD
V
GND
GND
V
V
V
LO
V
V
IN
Low- Side Supply Voltage
V
UVLO1
- 40
20
+125
V
DD
Ambient Temperature
T
C
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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NCD57200
Table 6. ELECTRICAL CHARACTERISTICS V = V = 15 V.
DD
BS
For typical values T = 25C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VOLTAGE SUPPLY
V
Supply Under Voltage
V
V
11
10
0.5
12
11
11.5
10.5
1.0
12
11
V
V
BS
UVLO2- OUT
- ON
Output Enabled
V
BS
Supply Under Voltage
UVLO2- OUT
- OFF
Output Disabled
V
BS
Supply Voltage Output
V
1.2
13
12
1.2
V
UVLO2- HYST
Enabled/Disabled Hysteresis
V
DD
Supply Under Voltage
V
12.5
11.5
1.0
V
UVLO1- OUT
- ON
Output Enabled
V
DD
Supply Under Voltage
V
V
UVLO1- OUT
- OFF
Output Disabled
V
DD
Supply Voltage Output
V
0.5
V
UVLO1- HYST
Enabled/Disabled Hysteresis
Leakage Current Between V and
S
GND
V
= 800 V, T = 25C
I
I
20
200
600
nA
S
A
HV_LEAK1
HV_LEAK2
VS = 800 V, TA = 40 C to 125 C
Quiescent Current V Supply
B
HO = Low
I
260
330
380
440
2.4
325
440
440
500
3
mA
mA
mA
mA
mA
BS
QBS1
QBS2
QDD1
QDD2
QDD3
(V Only)
Quiescent Current V Supply
HO = High
I
BS
(V Only)
B
Quiescent Current V Supply
V
LIN
V
LIN
V
LIN
= Float, V
= 3.3 V, V
= 0 V,
= 0 V,
I
I
I
DD
HIN
(V Only)
DD
Quiescent Current V Supply
DD
HIN
(V Only)
DD
Quiescent Current V Supply
= 0 V, V
= 3.3 V,
DD
HIN
(V Only)
DD
LOGIC INPUT
Low Level Input Voltage
High Level Input Voltage
Logic “1” Input Bias Current
Logic “1” Input Bias Current
V
0.9
V
V
IL
V
IH
2.4
V
= 3.3 V, V
= 3.3 V
= 20 V,
I
I
, I
LIN1+ HIN1+
25
50
mA
mA
LIN
HIN
V
LIN
V
DD
= 20 V, V
, I
LIN2+ HIN2+
100
150
HIN
= V
= 20 V
BS
Logic “0” Input Bias Current
DRIVER OUTPUT
V
= 0 V, V
= 0 V
I
, I
40
100
nA
V
LIN
HIN
LIN- HIN-
Output Low State
V
0.2
0.3
0.5
I
I
= 200 mA, T = 25 C
A
SINK
OL1
= 200 mA,
40 C to 125 C
V
SINK
T
OL2
=
A
Output High State
V
14.4
14
14.5
V
A
A
I
I
= 200 mA, T = 25 C
A
SOURCE
OH1
OH2
= 200 mA,
40 C to 125 C
V
SOURCE
T
A
=
Peak Driver Current, Sink
(Note 7)
V
V
= V = 15 V
I
I
2.3
2.1
HO
LO
PK SNK1
= V = 9 V
HO
LO
PK SNK2
(near Miller Plateau)
Peak Driver Current, Source
(Note 7)
V
V
= V = 0 V
I
I
1.9
1.5
HO
LO
PK SRC1
= V = 9 V
HO
LO
PK SRC2
(near Miller Plateau)
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NCD57200
Table 6. ELECTRICAL CHARACTERISTICS V = V = 15 V.
DD
BS
For typical values T = 25C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
I
= 100 mA, I = 100 mA
V
0.8
1.3
V
HO
LO
CLAMP- OUT
(V – V ) / (V – V
)
(pulse test, t
= 10 ms)
HO
B
LO
DD
CLPmax
DYNAMIC CHARACTERISTIC
HO High Propagation Delay
C
= 1 nF, V to 10% of Output
t
PD- ON- H
50
50
90
90
0
110
110
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LOAD
IH
Change for PW > 150 ns
HO Low Propagation Delay
C
LOAD
= 1 nF, V to 90% of Output
t
IL
PD- OFF- H
DISTORT- H
Change for PW > 150 ns
Propagation Delay Distortion(HS)
PW >150 ns
t
- 25
50
(= t
t
)
PD- ON- H
PD- OFF- H
LO High Propagation Delay
LO Low Propagation Delay
Propagation Delay Distortion(LS)
CLOAD = 1 nF, VIH to 10% of Output
Change for PW > 150 ns
t
90
90
0
110
110
25
PD- ON- L
CLOAD = 1 nF, VIL to 90% of Output
Change for PW > 150 ns
t
50
PD- OFF- L
DISTORT- L
PW >150 ns
PW > 150 ns
PW > 150 ns
t
- 25
- 25
- 25
(= t
t
)
PD- ON- L
PD- OFF- L
High Propagation Delay Distortion
between High and Low Sides
t
0
25
DISTORT- HL- H
Low Propagation Delay Distortion
between High and Low Sides
t
0
25
DISTORT- HL- L
Rise Time (HO) (see Figure 3)
Fall Time (HO) (see Figure 3)
Rise Time (LO) (see Figure 3)
Fall Time (LO) (see Figure 3)
C
LOAD
= 1 nF,
t
t
13
8
RISE- H
FALL- H
10% to 90% of Output Change
C
LOAD
= 1 nF,
90% to 10% of Output Change
C
LOAD
= 1 nF,
t
13
8
RISE- L
FALL- L
10% to 90% of Output Change
C
LOAD
= 1 nF,
t
90% to 10% of Output Change
Deadtime, HO Delays (see Figure 6)
Deadtime, LO Delays (see Figure 6)
Deadtime Matching
V
V
= 0 V and 3.3 V
= 0 V and 3.3 V
t
t
340
350
10
ns
ns
ns
ns
LIN/HIN
DT1
LIN/HIN
DT2
t
MDT
Minimum Pulse Width Filtering Time
(see Figure 3)
T
A
= 25 C
t
, t
MIN1 MIN2
10
40
UVLO Fall Delay (HO and LO)
UVLO Rise Delay (HO and LO)
t
t
1300
1100
ns
ns
UVF1, UVF2
t
t
UVR1, UVR2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Values based on design and/or characterization.
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NCD57200
V
IH
V
IL
HIN/LIN
t
t
MIN2
t
RISE- X
FALL- X
90%
t
PD- ON- X
t
MIN1
t
PD- OFF- X
HO/LO
10%
Figure 3. Propagation Delay, Rise and Fall Time
V
DD
HIN
LIN
Clamping
Circuit
Figure 4. Input Pin Structure
HIN/LIN
V
UVLOx- OUT- ON
V
UVLOx- OUT- OFF
t
t
UVFX
V /V
DD BS
UVRX
V
V
UVLOx- OUT- ON
UVLOx- OUT- OFF
HO/LO
Figure 5. UVLO
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NCD57200
Figure 6. Deadtime, Interlock and Output Minimum Pulse Width
HIN
t
t
MIN1
MIN2
t
t
DT1
DT2
t
t
MIN1
LIN
MIN2
Figure 7. Input Circuit
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NCD57200
TYPICAL CHARACTERISTICS
0.5
0.5
0.45
0.45
(2)
0.4
0.4
0.35
0.3
(2)
(1)
(1)
0.35
0.3
- 40 - 20
0
20
40
60
80
100
120 125
- 40 - 20
0
20
40
60
80
100
120 125
Temperature [C]
Temperature [C]
(1) V = 20 V, V = 15 V, LIN = FLOAT, HIN = LOW
(1) V = 15 V, V = 15 V, LIN = FLOAT, HIN = LOW
DD
BS
DD
BS
(2) V = 20 V, V = 15 V, LIN = 3.3 V, HIN = LOW
(2) V = 15 V, V = 15 V, LIN = 3.3 V, HIN = LOW
DD
BS
DD
BS
Figure 8. IDD Supply Current VDD = 15 V
Figure 9. IDD Supply Current VDD = 20 V
0.5
8
7
(3)
6
5
4
3
2
1
0
0.45
0.4
(3)
(2)
(1)
(2)
0.35
0.3
(1)
- 40 - 20
- 40 - 20
0
20
Temperature [C]
(1) V = 15 V, V = 15 V, LIN = FLOAT, HIN = LOW
40
60
80
100
120 125
0
20
Temperature [C]
(1) V = 15 V, V = 15 V, LIN = HIN = 20 kHz / 50%
40
60
80
100
120 125
DD
BS
DD
BS
(2) V = 20 V, V = 15 V, LIN = FLOAT, HIN = LOW
(2) V = 20 V, V = 15 V, LIN = HIN = 20 kHz / 50%
DD
BS
DD
BS
(3) V = 25 V, V = 15 V, LIN = HIN = 20 kHz / 50%
(3) V = 25 V, V = 15 V, LIN = FLOAT, HIN = LOW
DD
BS
DD
BS
Figure 10. IDD Supply Current VDD = 15–25 V, Input Float
Figure 11. IDD Supply Current VDD = 15–25 V,
LIN = HIN = 20 kHz / 50%
1
2
1.8
1.6
1.4
1.2
1
0.9
(3)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
(3)
0.8
0.6
0.4
0.2
0
(2)
(1)
(2)
(1)
0.1
0
- 40 - 20
0
20
Temperature [C]
(1) V = 15 V, V = 15 V, LIN = LOW, HIN = LOW
40
60
80
100
120 125
- 40 - 20
0
20
40
Temperature [C]
(1) V = 15 V, V = 25 V, LIN = LOW, HIN = LOW
60
80
100
120 125
DD
BS
DD
DD
DD
BS
(2) V = 15 V, V = 15 V, LIN = LOW, HIN = 3.3V
(3) V = 15 V, V = 15 V, LIN = LOW, HIN = 50%
(2) V = 15 V, V = 25 V, LIN = LOW, HIN = 3.3 V
(3) V = 15 V, V = 25 V, LIN = LOW, HIN = 20 kHz / 50%
DD
BS
BS
BS
DD
BS
Figure 12. IBS Supply Current VBS = 15 V
Figure 13. IBS Supply Current VBS = 25 V
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NCD57200
TYPICAL CHARACTERISTICS (continued)
2
2.2
1.8
(2)
2
(1)
(3)
(2)
(1)
1.6
1.4
1.2
1.8
1
0.8
0.6
0.4
0.2
0
1.6
1.4
(3)
1.2
(4)
1
- 40 - 20
0
20
Temperature [C]
(1) V = 15 V, V = 15 V, LIN = LOW, HIN = 50%
40
60
80
100 120 125
- 40 - 20
0
20
Temperature [C]
(1) V , LIN = HIGH
40
60
80
100 120 125
(2) V , HIN = HIGH
DD
BS
IH
IH
(2) V = 15 V, V = 20 V, LIN = LOW, HIN = 50%
DD
BS
(3) V , LIN = LOW
(4) V , HIN = LOW
IL
IL
(3) V = 15 V, V = 25 V, LIN = LOW, HIN = 50%
DD
BS
Figure 14. IBS Supply Current VBS = 15–25 V,
HIN = 20 kHz / 50%
Figure 15. Input Voltage Level
1.2
1.1
1
13
(1)
12.5
12
(2)
(3)
11.5
11
0.9
0.8
0.7
0.6
(2)
(1)
(4)
10.5
10
- 40 - 20
0
20
40
60
80
100 120 125
- 40 - 20
0
20
40
60
80
100 120 125
Temperature [C]
Temperature [C]
(1) V
(2) V
UVLO1- HYST
(1) V
(2) V
(3) V
UVLO1- OUT- ON
UVLO1- OUT- OFF
UVLO2- OUT- ON
UVLO2- OUT- OFF
(4) V
UVLO2- HYST
Figure 16. UVLO Hysteresis
Figure 17. UVLO Threshold Voltage
28
27
26
25
24
105
100
95
(2)
(1)
(2)
(1)
90
- 40 - 20
0
20
40
60
80
100 120 125
- 40 - 20
0
20
40
60
80
100 120 125
Temperature [C]
Temperature [C]
(1) I
, LIN = 3.3 V, V = V = 15V
DD BS
(1) I
(2) I
, LIN = 20 V, V = V = 20 V
DD BS
LIN1+
LIN2+
(2) I
, HIN = 3.3 V, V = V = 15V
DD BS
, HIN = 20 V, V = V = 20 V
HIN1+
HIN2+
DD
BS
Figure 18. Input Current VDD = VBS = 15 V
Figure 19. Input Current VDD = VBS = 20 V
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NCD57200
TYPICAL CHARACTERISTICS (continued)
1
100
95
(2)
(1)
0.9
(4)
(2)
90
85
80
0.8
(1)
(3)
0.7
- 40 - 20
0
20
40
60
80
100
120 125
- 40 - 20
0
20
40
60
80
100
120 125
Temperature [C]
Temperature [C]
(1) t
V
= 15 V
= 15 V
(3) t
V
= 20 V
PD- ON- H BS
PD- ON- H BS
(1) V - V
(2) V - V
LO DD
HO BS
(2) t
V
(4) t
V = 20 V
PD- OFF- H BS
PD- OFF- H BS
Figure 20. IGBT Short Circuit CLAMP Voltage Drop
Figure 21. HO Propagation Delay
24
22
20
18
16
14
12
10
8
100
95
90
85
80
(3)
(1)
(4)
(2)
(2)(4)
(1)(3)
- 40 - 20
0
20
40
60
80
100
120 125
- 50
- 25
0
25
50
75
100
V
125
Temperature [C]
Temperature [C]
(1) t
(2) t
V
= 15 V
= 15 V
(3) t
V
= 20 V
RISE- H BS
(3) t
(4) t
= 20 V
RISE- H BS
(1) t
(2) t
V
= 15 V
= 15 V
PD- ON- L DD
PD- ON- L DD
V
V
(4) t
V
= 20 V
V
= 20 V
FALL- H BS
FALL- H BS
PD- OFF- L DD
PD- OFF- L DD
Figure 23. HO Rise – Fall Time
Figure 22. LO Propagation Delay
18
17
16
15
14
13
12
380
370
360
350
340
330
(2)
(1)
(1)(3)
(2)(4)
11
10
- 50
- 25
0
25
50
75
100
125
- 40 - 20
0
20
40
Temperature [C]
(1) t = 15 V, V = 15 V
60
80
100
120 125
Temperature [C]
V
DTX DD
BS
(3) t
(4) t
V
= 20 V
(1) t
(2) t
V
= 15 V
= 15 V
RISE- L DD
RISE- L DD
(2) t
V
= 20 V, V = 20 V
DTX DD BS
V
= 20 V
V
FALL- L DD
FALL- L DD
Figure 24. LO Rise – Fall Time
Figure 25. Deadtime
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11
NCD57200
TYPICAL CHARACTERISTICS (continued)
24
26
(4)
25
23.5 (3)
(3)
(4)
23
24
23
22.5
22
22
(1)
21
(2)
21.5
(1)
20
(2)
21
- 40 - 20
19
0
20
40
60
80
100
120 125
- 40 - 20
0
20
40
60
80
100
V
120 125
Temperature [C]
Temperature [C]
(3) t
(4) t
= 15 V
(1) t
(2) t
V
= 15 V
= 20 V
(3) t
V
= 15 V
(1) t V = 15 V
MIN1- H BS
MIN2- H BS
MIN1- L DD
MIN2- L DD
(2) t
V
= 20 V
V
= 20 V
MIN1- H BS
MIN2- H BS
V
(4) t
V
= 20 V
MIN1- L DD
MIN2- L DD
Figure 26. Minimum Pulse Width Filtering
Time (LO)
Figure 27. Minimum Pulse Width Filtering
Time (HO)
1.9
(4)
20
18
16
14
12
10
8
(3)
(2)
(1)
1.8
(1)
1.7
(2)
1.6
(3)
1.5
6
1.4
1.3
1.2
4
2
0
1
10
100
1000
- 40 - 20
0
20
40
60
80
100
120 125
Frequency [kHz]
Temperature [C]
(1) C = 1 nF
(2) C = 10 nF
G
G
(1) t
(3) t
(2) t
(4) t
UVF1
UVR1
(3) C = 100 nF
G
UVF2
UVR2
Figure 28. UVLO Delay
Figure 29. Power Supply Current vs. Switching
Frequency (Duty Cycle 50%)
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12
NCD57200
Under Voltage Lockout (UVLO)
UVLO ensures correct switching of IGBT connected to
the driver output.
For reliable high output current suitable external power
capacitors are required. Parallel combination of 100 nF +
4.7 mF ceramic capacitors is optimal for a wide range of
applications using IGBT. For reliable driving of IGBT
modules (containing several parallel IGBTs) a higher
capacitance is required (typically 100 nF + 10 mF).
Capacitors should be as close as possible to the driver’s
power pins.
The IGBT is turned-off, if the supply V drops below
DD
V
V
or V drops below
BS
UVLO1-OUT-OFF
UVLO2-OUT-OFF
The driver output does not start to react to the input
signal on HIN or LIN until the V or V rises above
DD
BS
Powersupply ofisolated(HO)channelcanbeprovidedby
an external DC power supply or Bootstrap circuit.
the V
UVLOX-OUT-ON
Power Supply (VDD, VBS
)
NCD57200 is designed to support unipolar power supply
on both individual channels.
V
V
B
DD
V
DD
10 mF
V
BS
100 n
HIN
HO
+
-
+
-
LIN
V
S
10 mF
100 n
LO
GND
Figure 30. Unipolar Power Supply
V
DD
V
B
R
R
10 mF
100 n
GH
HIN
HO
V
DD
+
-
LIN
V
S
10 mF
100 n
LO
GND
GL
Figure 31. Bootstrap Power Supply
Signal Inputs (HIN, LIN)
Inputs of NCD57200 are active high. Outputs are in phase
with inputs signals respecting internal logic (see Figure 5, 6,
7).
WARNING: When the application uses an independent or
separate power supply for the control unit on
the input side of the driver, all inputs should
be protected by a serial resistor (In case of
a power failure of the driver, the driver may
be damaged due to overloading of the input
protection circuits).
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13
NCD57200
Common Mode Transient Immunity (CMTI)
10 mF
+
15 V
V
DD
V
B
+
-
S1
-
HIN
LIN
HO
HO must remain stable
V
S
GND
LO
15 V
+
-
10 mF
HV PULSE
FLOATING
Figure 32. CMTI Test Setup
(Test Conditions: HV PULSE = 900 V, dV/dt = 1- 100 V/ns, V = 15 V, V = 15 V)
DD
B
NOTE: Purple - recommended isolation gap.
Figure 33. Recommended Layout
High-speed signals
Ground plane
10 mils
0.25 mm
10 mils
0.25 mm
Keep this space free
40 mils
1 mm
40 mils
1 mm
from traces, pads and
vias
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low-speed signals
157 mils
(4 mm)
Figure 34. Recommended Layer Stack
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14
NCD57200
ORDERING INFORMATION
Device
†
Package
Shipping
2500 / Tape & Reel
NCD57200DR2G
SOIC- 8 (Pb- Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
DATE 16 FEB 2011
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
Y
B
0.25 (0.010)
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8
1
8
1
8
8
XXXXX
ALYWX
XXXXXX
AYWW
G
XXXXX
ALYWX
XXXXXX
AYWW
1.52
0.060
G
1
1
Discrete
Discrete
(Pb−Free)
IC
IC
(Pb−Free)
7.0
0.275
4.0
0.155
XXXXX = Specific Device Code
XXXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
A
= Assembly Location
= Year
Y
Y
W
G
= Year
= Work Week
= Pb−Free Package
WW
G
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
6. EMITTER, #2
7. BASE, #1
6. SOURCE, #2
7. GATE, #1
7. BASE
8. EMITTER
8. EMITTER, #1
8. SOURCE, #1
8. COMMON CATHODE
STYLE 5:
STYLE 6:
PIN 1. SOURCE
2. DRAIN
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
3. DRAIN
3. BASE, #2
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
STYLE 12:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
STYLE 18:
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
STYLE 20:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
5. RXE
6. VEE
7. GND
8. ACC
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
STYLE 22:
STYLE 23:
STYLE 24:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
PIN 1. I/O LINE 1
PIN 1. LINE 1 IN
PIN 1. BASE
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 25:
PIN 1. VIN
2. N/C
STYLE 26:
PIN 1. GND
2. dv/dt
STYLE 27:
PIN 1. ILIMIT
2. OVLO
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
5. V_MON
6. VBULK
7. VBULK
8. VIN
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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