NCH-RSL10-101S51-ACG

DATA SHEET

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Bluetooth⁾5.2

System-in-Package (SiP)

RSL10 SIP

SIP51 8x6

CASE 127EY

Introduction

RSL10 System−In−Package (RSL10 SIP) is a complete solution

that provides the easiest way to integrate the industry’s lowest power

Bluetooth Low Energy technology into a wireless application.

The RSL10 SIP features an on−board antenna, RSL10 radio SoC,

and all necessary passive components in one package to help minimize

overall system size. Already fully qualified to FCC, CE, and other

regulatory standards; RSL10 SIP removes the need for additional

antenna design considerations or RF certifications.

XXXXX

AWLYWW

(SIP51)

XXXXXX = Specific Device Code

A

WL

Y

WW

G or G

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Key Features

• Fully Certified:

♦ Bluetooth 5.2

♦ QDID

♦ Declaration ID

♦ FCC, CE, IC, MIC, KCC

• Industry’s Lowest Power:

ORDERING INFORMATION

†

Device

Package

Shipping

♦ Peak Rx Current = 5.6 mA (1.25 V VBAT)

♦ Peak Rx Current = 3.0 mA (3 V VBAT)

♦ Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT)

♦ Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT)

NCH−RSL10−

101S51−ACG

SIP51

(Pb−Free)

2500 /

Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

• Deep Sleep Current Consumption (1.25 V VBAT):

♦ Deep Sleep, IO Wake−up: 50 nA

♦ Deep Sleep, 8 kB RAM Retention: 300 nA

• Current Consumption (3 V VBAT):

♦ Deep Sleep, IO Wake−up: 25 nA

♦ Deep Sleep, 8 kB RAM Retention: 100 nA

• EEMBC ULPMark Core Profile (3 V): 1090

• EEMBC ULPMark Core Profile (2.1 V): 1360

• Advanced Wireless:

♦ Bluetooth 5.2 Certified with LE 2−Mbit PHY (High Speed),

as well as Backwards Compatibility and Support for Earlier

Bluetooth Low Energy Specifications

♦ Supports FOTA (Firmware Over−The−Air) Updates

♦ Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −93 dB

♦ Transmitting Power: −17 to +6 dBm

♦ Range up to 100 Meters

Other Key Features

®

• Arm Cortex −M3 Processor Clocked at up to 48 MHz

• Supply Voltage Range: 1.1 − 3.3 V

• 384 kB of Flash Memory

• 76 kB of Program Memory

• 88 kB of Data Memory

1

Publication Order Number:

January, 2022 − Rev. 4

RSL10SIP/D

RSL10 SIP

FEATURES

2

• Arm Cortex−M3 Processor: A 32−bit core for real−time

applications, specifically developed to enable

high−performance low−cost platforms for a broad range

of low−power applications.

• Highly Configurable Interfaces: I C, UART, two SPI

interfaces, PCM interface, multiple GPIOs. It also

supports a digital microphone interface (DMIC) and an

output driver (OD).

• LPDSP32: A 32−bit Dual Harvard DSP core that

efficiently supports intensive signal processing

applications. Various codecs are available to customers

through libraries that are included in RSL10’s

development tools.

• Radio Frequency Front−End: Based on a 2.4 GHz RF

transceiver, the RFFE implements the physical layer of

the Bluetooth Low Energy technology standard and other

proprietary or custom protocols.

• Flexible Clocking Scheme: RSL10 must be clocked

from the XTAL/PLL of the radio front−end at 48 MHz

when transmitting or receiving RF traffic. When RSL10

is not transmitting/receiving RF traffic, it can run off the

48 MHz XTAL, the internal RC oscillators, the 32 kHz

oscillator, or an external clock. A low frequency RTC

clock at 32 kHz can also be used in Deep Sleep Mode. It

can be sourced from either the internal XTAL, the RC

oscillator, or a digital input pad.

• Diverse Memory Architecture: 76 kB of SRAM

program memory (4 kB of which is PROM containing the

chip boot−up program, and is thus unavailable to the user)

and 88 kB of SRAM data memory are available. A total

of 384 kB of flash is available to store the Bluetooth stack

and other applications.

The Arm Cortex−M3 processor can execute from SRAM

and/or flash.

• Security: AES128 encryption hardware block for custom

secure algorithms and code protection with authenticated

debug port access (JTAG ‘lock’)

• Protocol Baseband Hardware: Bluetooth 5.2 certified

and includes support for a 2 Mbps RF link and custom

protocol options. The RSL10 baseband stack is

supplemented by support structures that enable

implementation of onsemi and customer designed

custom protocols.

• Highly−Integrated SoC: The dual−core architecture is

complemented by high−efficiency power management

units, oscillators, flash and RAM memories, a DMA

controller, along with a full complement of peripherals

and interfaces.

• Ultra−Low Power Consumption Application

• Deep Sleep Mode: RSL10 can be put into a Deep Sleep

Mode when no operations are required. Various Deep

Sleep Mode configurations are available, including:

♦ “IO wake−up” configuration. The power consumption

in deep sleep mode is 50 nA (1.25 V VBAT).

♦ Embedded 32 kHz oscillator running with interrupts

from timer or external pin. The total current drain is

90 nA (1.25 V VBAT).

Examples:

♦ Low Duty Cycle Advertising: IDD 1.1 mA for

advertising at all three channels at 5 second intervals

@ VBAT 3 V, DCDC converter enabled.

• RoHS Compliant Device

♦ As above with 8 kB RAM data retention. The total

current drain is 300 nA (1.25 V VBAT).

♦ The DC−DC converter can be used in buck mode or

LDO mode during Sleep Mode, depending on VBAT

voltage.

• Standby Mode: Can be used to reduce the average power

consumption for off−duty cycle operation, ranging

typically from a few ms to a few hundreds of ms. The

typical chip power consumption is 30 mA in Standby

Mode.

• Multi−Protocol Support: Using the flexibility provided

by LPDSP32, the Arm Cortex−M3 processor, and the RF

front−end; proprietary protocols and other custom

protocols are supported.

• Flexible Supply Voltage: RSL10 integrates high−

efficiency power regulators and has a VBAT range of 1.1

to 3.3 V.

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2

RSL10 SIP

Notice

inside the SiP. If an external antenna is used instead of the

antenna internal to the SiP, this external antenna needs to be

connected to PIN E1.

All specifications for the RSL10 System−in−Package are

based on the RSL10 radio SoC. The RSL10 SIP data sheet

only contains key parameters. For a full list of RSL10

parameters and specifications, refer to the RSL10 data sheet.

Additionally, an external PCB connection is required for

the VDDO pad to ensure that it is not left floating. For

example, it can be connected to VBAT so that the logic high

level for the digital I/O (DIO) pads is equal to VBAT.

Figures 1 and 2 show proposed layout patterns for the

RSL10 SIP. The specific layout pattern used in the

application may have to be adjusted to meet certain needs of

the PCB manufacturer or assembly house. PCB design files

for the RSL10 SIP are available at www.onsemi.com.

Application Board Connection

The RSL10 SIP is designed to be reflowed onto low−cost

printed circuit boards. The RSL10 SIP connects to the

application board via solder pads located on the bottom.

To properly operate the RSL10 SIP an external PCB

connection between the RF and ANT pads is required. This

connection connects the RF pin on RSL10 to the antenna

Notes:

1. Align component edge to PCB edge if possible.

2. Extend keepout area to PCB edge.

3. Keepout area− All layers.

4. Keepout area− Top layer only.

5. Units = mm.

Figure 1. RSL10 SIP Keepout Area Requirements

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3

RSL10 SIP

Notes:

1. When incorporating internal antenna, join landing pads using 0.40 x 1.10 shape.

2. Establish 50 W impedance to underlying reference plane.

3. Maintain minimum 300 mm distance from ground plane.

4. Area for several vias.

5. Refer to radiation efficiency data for applicable ground plane sizing.

6. Units = mm.

Figure 2. Minimum Top Layer Ground Structure

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4

RSL10 SIP

RSL10 SiP Schematic

The schematic for the RSL10 SIP is shown in Figure 3.

Figure 3. RSL10 SIP Schematic

Figure 4. Pin Connection Diagram

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5

RSL10 SIP

PAD FUNCTION DESCRIPTION

For detailed pad function information see the RSL10 data sheet.

Table 1. PAD LIST

Pad Identifier

A1

Pad Name

JTMS

DOI12

JTCK

I/O

I

A/D

D

Pull

U

Description

CM3−JTAG Test Mode State

A2

D

U/D

U

Digital input output 12

CM3−JTAG Test Clock

Digital input output 10

Digital input output 6

Digital input output 3 / ADC 3

Digital input output 2 / ADC 2

Digital input output 5

Digital input output/CM3−JTAG Test Reset

Digital input output/CM3−JTAG Test Data In

Digital input output 11

Digital input output 8

Digital input output 1 / ADC 1

Digital input output 7

Digital input output 4

Digital input output/CM3−JTAG Test Data Out

Digital input output 9

Digital input output 0 / ADC 0

External clock input

Ground

A3

D

A4

DOI10

DOI6

D

U/D

U

A5

D

A6

DOI3

A/D

D

A7

DOI2

A8

DOI5

B1

DOI13

DOI14

DOI11

DOI8

D

B2

D

B3

D

B5

D

B6

DOI1

A/D

D

B7

DOI7

B8

DOI4

D

C1

C2

C7

C8

D1

D2

D7

D8

E1

DOI15

DOI9

D

DOI0

A/D

D

EXT_CLK

DGND

VDDO

VBAT

I/O

I

P

Ground

P

Digital O/I voltage supply

Battery input voltage

RF signal input/output

Ground

I

P

RF

I/O

I

A

E2

DGND

NRESET

AOUT

ANT

P

E7

D

U

Reset pin

E8

O

A

Analog test pin

F1

I/O

I

A

Antenna

F2

DGND

RES

P

Ground

F3

P

Ground

F4

P

Ground

F5

P

Ground

F6

P

Ground

F7

D

RESERVED

F8

WAKEUP

DGND

I

A

Wake−up pin for power modes

Ground

G1

G2

G3

G4

G5

I/O

P

Ground

P

Ground

P

Ground

P

Ground

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6

RSL10 SIP

Table 1. PAD LIST (continued)

Pad Identifier

Pad Name

I/O

A/D

Pull

Description

G6

G7

G8

H1

H8

J1

DGND

P

Ground

J8

K1

K8

L1

L8

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol

VBAT

VDDO

VSSRF

VSSA

VSSD

Vin

Parameter

Min

Max

3.63

Unit

V

Power supply voltage

I/O supply voltage (Note 1)

RF front−end ground

Analog ground

V

−0.3

V

Digital core and I/O ground

Voltage at any input pin

V

VSSD−0.3

VDDO+0.3

(Up to a maximum of 3.63 V)

V

T storage

Storage temperature range

−40

85

°C

Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)

The QFN package meets 450 V CDM level

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. VDDO voltage must not be applied before VBAT voltage on cold start.

Table 3. RECOMMENDED OPERATING CONDITIONS

Description

Symbol

VBAT

Conditions

Min

1.18

−40

Typ

1.25

−

Max

3.3

85

Unit

V

Supply voltage operating range

Functional temperature range

Input supply voltage on VBAT pin (Note 2)

T functional

°C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

2. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed:

− Maximum Tx power 0 dBm.

− SYSCLK ≤ 24 MHz.

− Functional temperature range limited to 0−50 deg C

The following trimming parameters should be used:

− VCC = 1.10 V

− VDDC = 0.92 V

− VDDM = 1.05 V, will be limited by VCC at end of battery life

− VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled

RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT ≥ 1.10 V under

the restricted operating conditions described above.

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7

RSL10 SIP

Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or

VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Unit

OVERALL

Current consumption RX,

I

1.8

1.15

50

mA

nA

mA

VBAT

V

= 1.25 V, low latency

BAT

Current consumption TX,

= 1.25 V, low latency

V

BAT

Current consumption RX,

= 1.25 V

V

BAT

Deep sleep current,

example 1, V = 1.25 V

Ids1

Ids2

Ids3

Istb

Wake up from wake up pin or DIO

wake up.

BAT

Deep sleep current,

example 2, V = 1.25 V

Embedded 32 kHz oscillator running

with interrupts from timer or external pin.

90

BAT

Deep sleep current,

example 3, V = 1.25 V

As Ids2 but with 8 kB RAM data

retention.

300

30

BAT

Standby Mode current,

= 1.25 V

Digital blocks and memories are not

clocked and are powered at a reduced

voltage.

V

BAT

Current consumption RX,

= 3 V

I

0.9

25

mA

nA

mA

VBAT

V

BAT

Current consumption TX,

= 3 V

I

VBAT

V

BAT

Deep sleep current,

example 1, V = 3 V

Ids1

Ids2

Ids3

Istb

Wake up from wake up pin or DIO

wake up.

BAT

Deep sleep current,

example 2, V = 3 V

Embedded 32 kHz oscillator running

with interrupts from timer or external pin.

40

BAT

Deep sleep current,

example 3, V = 3 V

As Ids2 but with 8 kB RAM data

retention.

100

17

BAT

Standby Mode current,

= 3 V

Digital blocks and memories are not

clocked and are powered at a reduced

voltage.

V

BAT

EEMBC ULPMark BENCHMARK, CORE PROFILE

ULPMark CP 3.0 V

Arm Cortex−M3 processor running from

RAM, VBAT= 3.0 V, IAR C/C++

Compiler for ARM 8.20.1.14183

1090

1260

ULP

Mark

ULPMark CP 2.1 V

Arm Cortex−M3 processor running from

RAM, VBAT= 2.1 V, IAR C/C++

Compiler for ARM 8.20.1.14183

ULP

Mark

EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP

Arm Cortex−M3 processor

At 48 MHz SYSCLK. Using the IAR

8.10.1 C compiler, certified

159

174

Core

Mark

running from RAM

LPDSP32 running from RAM

At 48 MHz SYSCLK

Using the 2020.03 release of

the Synopsys LPDSP32 C compiler

Core

Mark

Arm Cortex−M3 processor and

LPDSP32 running from RAM,

VBAT = 1.25 V

At 48 MHz SYSCLK

123

293

29.1

Core

Mark/

mA

Arm Cortex−M3 processor and

LPDSP32 running from RAM,

VBAT = 3 V

Core

Mark/

mA

Arm Cortex−M3 processor

running CoreMark from RAM,

VBAT = 1.25 V

At 48 MHz SYSCLK

(processor consumption only)

mA/MHz

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8

RSL10 SIP

Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or

VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Unit

EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP

Arm Cortex−M3 processor

running CoreMark from RAM,

VBAT = 3 V

At 48 MHz SYSCLK

(processor consumption only)

12.3

mA/MHz

Arm Cortex−M3 processor

running CoreMark from Flash,

VBAT = 1.25 V

At 48 MHz SYSCLK

34.3

14.6

mA/MHz

(processor consumption only)

Arm Cortex−M3 processor

running CoreMark from Flash,

VBAT = 3 V

At 48 MHz SYSCLK

(processor consumption only)

LPDSP32 running CoreMark

from RAM, VBAT = 1.25 V

At 48 MHz SYSCLK

19.5

8.2

mA/MHz

(processor consumption only)

LPDSP32 running CoreMark

from RAM, VBAT = 3 V

At 48 MHz SYSCLK

(processor consumption only)

INTERNALLY GENERATED VDDC: Digital Block Supply Voltage

Supply voltage: operating range

VDDC

0.92

0.75

1.15

1.32

V

(Note 3)

Supply voltage: trimming range

Supply voltage: trimming step

VDDC

1.38

V

RANGE

VDDC

10

mV

STEP

INTERNALLY GENERATED VDDM: Memories Supply Voltage

Supply voltage: operating range

VDDM

1.05

0.75

1.15

1.32

V

(Note 4)

Supply voltage: trimming range

Supply voltage: trimming step

VDDM

1.38

V

RANGE

VDDM

10

mV

STEP

INTERNALLY GENERATED VDDRF: Radio Front end supply voltage

Supply voltage: operating range

VDDRF

1.00

0.75

1.10

1.32 (Notes

5 and 6)

V

Supply voltage: trimming range

Supply voltage: trimming step

VDDRF

1.38

V

RANGE

VDDRF

10

mV

STEP

VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage

Digital I/O supply VDDO

INDUCTIVE BUCK DC−DC CONVERTER

1.1

1.25

3.3

V

VBAT range when the DC−DC

DCDC

IN_RANGE

1.4

1.1

3.3

V

converter is active (Note 7)

VBAT range when the LDO is

active

LDO

IN_RANGE

Output voltage: trimming range

DCDC

OUT_RANGE

1.2

10

1.32

V

Supply voltage: trimming step

POWER−ON RESET

POR voltage

DCDC

mV

STEP

VBAT

0.4

0.8

1.0

V

POR

RADIO FRONT−END: General Specifications

RF input impedance

Data rate FSK / MSK / GFSK

Data rate 4−FSK

Z

Single ended

50

W

in

R

OQPSK as MSK

62.5

250

1000

3000

4000

2000

kbps

FSK

On−air data rate

bps

GFSK

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9

RSL10 SIP

Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or

VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Unit

RADIO FRONT−END: Crystal and Clock Specifications

Xtal frequency

Settling time

F

XTAL

Fundamental

48

MHz

ms

0.5

1.5

RADIO FRONT−END: Synthesizer Specifications

Frequency range

RX frequency step

F

RF

Supported carrier frequencies

2360

2500

100

MHz

Hz

RX Mode frequency synthesizer

resolution

TX frequency step

TX Mode frequency synthesizer

resolution

600

Hz

PLL Settling time, RX

PLL Settling time, TX

t

RX Mode

15

5

25

10

ms

PLL_RX

t

TX mode, BLE modulation

PLL_TX

RADIO FRONT−END: Receive Mode Specifications

Current consumption at 1 Mbps,

= 1.25 V

IBAT

VDDRF = 1.1 V, 100% duty cycle

5.6

6.2

3.0

3.4

mA

RFRX

V

BAT

Current consumption at 2 Mbps,

= 1.25 V

V

BAT

Current consumption at 1 Mbps,

= 3 V, DC−DC

V

BAT

Current consumption at 2 Mbps,

= 3 V, DC−DC

V

BAT

RX Sensitivity, 0.25 Mbps

RX Sensitivity, 0.5 Mbps

RX Sensitivity, 1 Mbps, BLE

0.1% BER (Notes 8, 9)

−96

−95

−93

dBm

0.1% BER (Notes 8, 9) Single−ended

match to 50 W

RX Sensitivity, 2 Mbps, BLE

RSSI effective range

RSSI step size

0.1% BER (Notes 8, 9)

Without AGC

−91

60

dBm

dB

2.4

48

dB

RX AGC range

dB

RX AGC step size

Max usable signal level

Programmable

0.1% BER

6

dB

−10

dBm

RADIO FRONT−END: Transmit Mode Specifications

Tx peak power consumption at

VBAT = 1.25 V (Note 10)

IBAT

Tx power 0 dBm, VDDRF = 1.07 V,

VDDPA: off, LDO mode

8.9

17.4

25

mA

dBm

dB

RFTX

Tx power 3 dBm, VDDRF = 1.1 V,

VDDPA: 1.26 V, LDO mode

Tx power 6 dBm, VDDRF = 1.1 V,

VDDPA: 1.60 V, LDO mode

Tx peak power consumption at

VBAT = 3 V (Note 10)

IBAT

Tx power 0 dBm, VDDRF = 1.07 V,

VDDPA: off, DC−DC mode

4.6

8.6

12

RFTX

Tx power 3 dBm, VDDRF = 1.1 V,

VDDPA = 1.26 V, DC−DC mode

Tx power 6 dBm, VDDRF = 1.1 V,

VDDPA = 1.60 V, DC−DC mode

Transmit power range

BLE

−17

+6

(Note 12)

Transmit power step size

Full band

1

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RSL10 SIP

Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or

VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Unit

RADIO FRONT−END: Transmit Mode Specifications

Tx power 0 dBm. Full band. Relative to

the typical value.

−1.5

1.5

dB

nd

Power in 2 harmonic

0 dBm mode. 50 W for “Typ” value.

−62

−70

−82

dBm

(Note 11)

rd

Power in 3 harmonic

0 dBm mode. 50 W for “Typ” value.

(Note 11)

th

Power in 4 harmonic

0 dBm mode. 50 W for “Typ” value.

(Note 11)

ADC

Resolution

ADC

8

0

12

14

2

bits

V

RES

Input voltage range

ADC

RANGE

INL

ADC

−2

+2

mV

kHz

INL

DNL

ADC

−1

+1

Channel sampling frequency

ADC

For the 8 channels sequentially,

SLOWCLK = 1 MHz

0.0195

6.25

CH_SF

32 kHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency

Trimming steps

Freq

20

2

32

50

5

kHz

%

UNTR

Steps

1.5

3 MHz ON−CHIP RC OSCILLATOR

Untrimmed Frequency

Trimming steps

Freq

3

MHz

%

UNTR

Steps

Fhi

1.5

10

Hi Speed mode

MHz

32 kHz ON−CHIP CRYSTAL OSCILLATOR

Output Frequency

Startup time

Freq

Depends on xtal parameters

Steps of 0.4 pF

32768

1

Hz

s

32k

3

Internal load trimming range

Duty Cycle

0

25.2

60

pF

%

40

50

DC INPUT CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 2.97 V – 3.3 V, nominal: 3.0 V Logic

Voltage level for high input

Voltage level for low input

V

2

VDDO + 0.3

0.8

V

IH

V

VSSD −

0.3

IL

DC INPUT CHARACTERISTICS OF THE DIGITAL PADS − With VDDO = 1.1 V – 1.32 V, nominal: 1.2 V Logic

Voltage level for high input

V

0.65 *

VDDO + 0.3

V

IH

VDDO

Voltage level for low input

V

VSSD −

0.3

0.35 *

VDDO

IL

DC OUTPUT CHARACTERISTICS OF THE DIGITAL PADS

Voltage level for high output

V

I

= 2 mA to 12 mA

VDDO −

V

OH

0.4

Voltage level for low output

DIO DRIVE STRENGTH

DIO drive strength

V

I

= 2 mA to 12 mA

4

2

0.4

12

OL

OH

IDIO

12

mA

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RSL10 SIP

Table 4. ELECTRICAL PERFORMANCE SPECIFICATIONS (continued)

Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C for VBAT = VDDO = 1.25 V in LDO mode, or

VBAT = VDDO = 3 V in DC−DC (buck) mode.

Description

Symbol

Conditions

Min

Typ

Max

Unit

FLASH SPECIFICATIONS

Endurance of the 384 kB of flash

10000

write/

erase

cycles

Endurance for sections NVR1,

NVR2, and NVR3 (6 kB in total)

1000

write/

erase

cycles

Retention

25

years

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The maximum VDDC voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

4. The maximum VDDM voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

5. The maximum VDDRF voltage cannot exceed the VBAT input voltage or the VCC output from the buck converter.

6. The VDDRF calibrated target is 1.07 V (TX power = 0 dBm).

7. The LDO can be used to regulate down from VBAT and generate VCC. For VBAT values higher than 1.5 V, the LDO is less efficient and it

is possible to save power by activating the DC−DC converter to generate VCC.

8. Signal generated by RF tester.

9. Single−ended match to 50 ohms, measured at pin E1 including loss of integrated Tx harmonic filter.

10.All values are based on evaluation board performance, including the harmonic filter loss.

11. The values shown here are including integrated RF filter.

12.For optimal performance, charge pump frequency of 125 kHz should be avoided when VDDPA supply is enabled.

Table 5. VDDM TARGET TRIMMING VOLTAGE IN FUNCTION OF VDDO VOLTAGE

VDDM Voltage (V)

DIO_PAD_CFG DRIVE

Maximum VDDO Voltage (V)

1.05

1.10

1

0

2.7

3.2

3.3

NOTE: These are trimming targets at room/ATE temperature 25X30°C.

Table 6. VDDC TARGET TRIMMING VOLTAGE IN FUNCTION OF SYSCLK FREQUENCY

VDDC Voltage (V)

Maximum SYSCLK Frequency (MHz)

Restriction

0.92

≤ 24

The ADC will be functional in low frequency

mode and between 0 and 85°C only.

1.00

1.05

≤ 24

Fully functional

48

NOTE: These are trimming targets at room/ATE temperature 25X30°C.

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12

RSL10 SIP

ANTENNA SPECIFICATIONS

The antenna performance of the RSL10 SIP depends on the size of the ground plane on which it is mounted. Figure 5 shows

an overview of different ground plane sizes with expected antenna return losses shown in Figure 6.

1

2

3

4

5

6

50 x 60mm

40 x 60mm

30 x 60mm

25 x 60mm

25 x 25mm 12.4 x 60mm

Figure 5. PCB ground planes. 1) 50x60, 2) 40x60, 3) 30x60, 4) 25x60, 5) 12.5x60. All sizes in mm

Efficiency

80.00

70.00

60.00

50.00

40.00

30.00

20.00

10.00

0.00

1

2

3

4

5

6

Figure 6. Antenna Efficiency vs. PCB Size

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13

RSL10 SIP

Figure 7. Radiation Pattern for 50 x 60 mm PCB Ground Plane

Figure 8. Radiation Pattern for 40 x 60 mm PCB Ground Plane

Figure 9. Radiation Pattern for 30 x 60 mm PCB Ground Plane

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14

RSL10 SIP

Figure 10. Radiation Pattern for 25 x 60 mm PCB Ground Plane

Figure 11. Radiation Pattern for 25 x 25 mm PCB Ground Plane

Figure 12. Radiation Pattern for 12.5 x 60 mm PCB Ground Plane

ENVIRONMENTAL SPECIFICATIONS

Electrostatic Discharge (ESD) Sensitive Device

CAUTION: ESD sensitive device. Permanent damage may occur on devices subjected to high−energy electrostatic

discharges.

Proper ESD precautions in handling, packaging and testing are recommended to avoid performance degradation or loss of

functionality.

Solder Information

The RSL10 SIP is constructed with all RoHS compliant material and should be reflowed accordingly. This device is Moisture

Sensitive Class MSL3 and must be stored and handled accordingly. Re−flow according to IPC/JEDEC standard J−STD−020C,

Joint Industry Standard: Re−flow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Hand

soldering is not recommended for this part.

For more information, see SOLDERRM/D available from www.onsemi.com.

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15

RSL10 SIP

REGULATORY INFORMATION

FCC Regulatory and User Information

FCC ID: 2APD9−RSL10SIP

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) this device may not cause harmful interference, and (2) this device must accept any interference received, including

interference that may cause undesired operation.

Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.

Module Usage Conditions

Manufacturers of products incorporating the RSL10SIP Bluetooth 5.2 Module are authorized to use the FCC Grant of the

RSL10SIP module for their own products according to the conditions referenced in the grant.

A product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wording

such as: “Contains FCC ID:2APD9−RSL10SIP”

The label of the host device shall also contain the following statement. When this is not possible, the information shall be

included in the User Manual of the host device:

“This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

(1) this device may not cause harmful interference, and (2) this device must accept any interference received, including

interference that may cause undesired operation.

Any changes or modifications not expressly approved by onsemi could void the user’s authority to operate the equipment.”

WARNING: RF Exposure Compliance

In order to comply with FCC RF exposure requirements this device must be installed to provide a separation distance of 5 mm

or greater between this device and the user.

ISED Regulatory and User Information

ISED ID 23763−RSL10SIP

HVIN RSL10SIP

This device contains licence−exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic

Development Canada’s licence−exempt RSS(s). Operation is subject to the following two conditions:

(1) This device may not cause interference.

(2) This device must accept any interference, including interference that may cause undesired operation of the device.

L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences et

Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux

conditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillage

radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.

Module Usage Conditions

A product containing the RSL10SIP module shall bear a label referring to the enclosed module. The label shall use wording

such as: “Contains IC: 23763−RSL10SIP”

The label of the host device shall also contain the following statement. When this is not possible, the information shall be

included in the User Manual of the host device:

“This device contains licence−exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic

Development Canada’s licence−exempt RSS(s). Operation is subject to the following two conditions:

(1) This device may not cause interference.

(2) This device must accept any interference, including interference that may cause undesired operation of the device.”

The transmitter module may not be co−located with any other transmitter or antenna.

Un produit contenant le module RSL10SIP devra porter une étiquette du dispositif qui fait référence au module inclus.

L’étiquette du dispositif devra utiliser un libellé tel que: “Contient IC: 23763−RSL10SIP”

L’étiquette du dispositif devra également inclure la déclaration ci−dessous. Si cela n’est pas possible, cette information devra

être précisée dans le manuel de l’utilisateur:

L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation, Sciences et

Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation est autorisée aux deux

conditions suivantes: (1) L’appareil ne doit pas produire de brouillage; (2) L’appareil doit accepter tout brouillage

radioélectrique subi, même si le brouillage est susceptible d’en compromettre le fonctionnement.

Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne.

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16

RSL10 SIP

WARNING: RF Exposure Compliance

In order to comply with ISED RF exposure requirements this device must be installed to provide a separation distance of 7 mm

or greater between this device and the user.

Afin de se conformer aux exigences d’exposition ISDE RF, cet appareil doit être installé pour fournir une distance de séparation

de 7 mm ou plus entre cet appareil et l’utilisateur.

Korean Regulatory and User Information

ཀྵӅꢀੌꢁ ꢂꢃꢄꢄ(ꢅꢆ෠๥ꢇꢈꢉฌꢊ ꢂꢃꢄꢄ)

ӌ Ԡ р (ӌԠр): onsemi

ӌ Ԡ ꢋ (ꢌꢍٰ): ୀꢎꢏ

ӌ ᄸ ꢐ (ӌᄸ): NCH−RSL10−101S51−ACG

ꢑ ꢒ ꢐ (ꢑꢒ): RSL10SIP

ӌԠꢓꢔ (ꢕꢍꢖр): ꢗꢘ ׁ

ꢆ ѕଈꢙ ꢆꢚҴጄ, Wi−Fi ꢛꢙ ꢜꢝໜꢉ ѕଈ ᢱ ꢂꢃ๥ꢇѕଈ˰ ᶤ͠ ᆼӁሌ ѕꢀʀⓜ ⑬ꢊሐ ၽ͠ ˔сꢚϴ

ꢖϬ൜ ࿀ᙥ⓱ꢆ и♵ᚈꢏ.

ሤᚹ ꢂꢃⓤ∄ꢙ Ҵྼዬꢇ ࿀ᙥ⓱ꢆ иϬᾀᰜ ꢞꢐꢟҴꢠ ꢡꢢꢣ ⓜ∄ꢉꢙ ሐ ꢤ ꢥꢦ.

The following ID information needs to be added to the product package (application and user documentation).

Korean KC Mark and Identifier as shown below. Height of KC mark is 5mm minimum. Colour preference is Navy (5PB 2/8

color according to KS A 0062). Acceptable other colours are black, gold and silver. Other colours may only be used if preferred

colours are not legible for the mark. The conformity assessment certification number is to be near the KC mark. (usually below).

R-CRM-oNs-RSL10SIP

European Regulatory and User Information

This device complies with the essential requirements of the Radio Equipment Directive 2014/53/EU. The following ID

information needs to be added to the product package (application and user documentation).

Japanese Regulatory and User Information

The following ID information needs to be added to the product package (application and user documentation).

ID (209−J00320) and must be combined with the Giteki (MIC) Mark as specified below.

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17

RSL10 SIP

Development Tools

Export Control Classification Number (ECCN)

RSL10 is supported by a full suite of comprehensive tools

including:

• An easy−to−use development board

• Software Development Kit (SDK) including an Oxygen

Eclipse−based development environment, Bluetooth

protocol stacks, sample code, libraries, and

documentation

The ECCN designation for RSL10 is 5A991.g.

Company or Product Inquiries

For more information about onsemi products or services

visit our Web site at www.onsemi.com.

For sales or technical support, contact your local

representative or authorized distributor.

Bluetooth is a registered trademark of Bluetooth SIG.

Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries).

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18

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SIP51 8x6

CASE 127EY

ISSUE B

DATE 30 JUN 2020

GENERIC

MARKING DIAGRAM*

A

= Assembly Location

*This information is generic. Please refer to

XXXXXXXX

AWLYWG

WL = Wafer Lot

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present. Some products

may not follow the Generic Marking.

Y

W

G

= Year

= Work Week

= Pb−Free Package

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON85298G

SIP51 8x6

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	NCH-RSL10-101S51-ACG
厂家：	ONSEMI
描述：	封装内系统，Bluetooth® 5 认证电信电信集成电路
文件：	总20页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCH-RSL10-101S51-ACG [ONSEMI]

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NCH030A3-0.5000

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