NCID9211R2 [ONSEMI]
High Speed Dual-Channel, Bi-Directional Ceramic Digital Isolator;
| 型号： | NCID9211R2 |
| 厂家： | 
ONSEMI |
| 描述： | High Speed Dual-Channel, Bi-Directional Ceramic Digital Isolator |
| 文件： | 总12页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
High Speed Dual-Channel,
Bi-Directional Ceramic
Digital Isolator
SOIC16 W
CASE 751EN
NCID9211
Description
The NCID9211 is a galvanically isolated full duplex, bi−directional,
high−speed dual−channel digital isolator with output enable. This
device supports isolated communications thereby allowing digital
signals to communicate between systems without conducting ground
loops or hazardous voltages.
It utilizes onsemi’s patented galvanic off−chip capacitor isolation
technology and optimized IC design to achieve high insulation and
high noise immunity, characterized by high common mode rejection
and power supply rejection specifications. The thick ceramic substrate
yields capacitors with ~25 times the thickness of thin film on−chip
capacitors and coreless transformers. The result is a combination of
the electrical performance benefits that digital isolators offer with the
safety reliability of a >0.5 mm insulator barrier similar to what has
historically been offered by optocouplers.
MARKING DIAGRAM
AWLYWW
9211
A
= Assembly Location
WL = Wafer Lot / Assembly Lot
= Year
Y
WW = Work Week
9211 = Specific Device Code
The device is housed in a 16−pin wide body small outline package.
Features
• Off−Chip Capacitive Isolation to Achieve Reliable High Voltage
Insulation
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
♦ DTI (Distance Through Insulation): ≥ 0.5 mm
♦ Maximum Working Insulation Voltage: 2000 V
• Full Duplex, Bi−directional Communication
• 100 KV/ms Minimum Common Mode Rejection
peak
• High Speed:
♦ 50 Mbit/s Data Rate (NRZ)
♦ 25 ns Maximum Propagation Delay
♦ 10 ns Maximum Pulse Width Distortion
• 8 mm Creepage and Clearance Distance to Achieve Reliable High
Voltage Insulation.
• Specifications Guaranteed Over 2.5 V to 5.5 V Supply Voltage and
−40°C to 125°C Extended Temperature Range
• Over Temperature Detection
• Output Enable Function (Primary and Secondary Side)
• NCIV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable (Pending)
• Safety and Regulatory Approvals
♦ UL1577, 5000 V
for 1 Minute
RMS
♦ DIN EN/IEC 60747−17 (Pending)
Typical Applications
• Isolated PWM Control
• Programmable Logic Control
• Isolated Data Acquisition System
• Voltage Level Translator
• Industrial Fieldbus Communications
2
• Microprocessor System Interface (SPI, I C, etc.)
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
NCID9211/D
September, 2021 − Rev. 3
NCID9211
PIN CONFIGURATION
BLOCK DIAGRAM
1
16
15
VDD1
VDD2
2
GND 1
GND 2
NC
EN1
VOA
3
4
5
6
7
8
14 NC
EN 2
13
12
11
10
9
VINA
VOB
VINB
NC
NC
GND 2
GND 1
Figure 2. Functional Block Diagram
Figure 1. Pin and Channel Configuration
PIN DEFINITIONS
Pin No.
Name
Description
Power Supply, Primary Side
Ground, Primary Side
No Connect
1
2
V
DD1
GND1
NC
3
4
EN1
Enable, Primary Side
Output, Channel A
Input, Channel B
5
V
OA
6
V
INB
7
NC
GND1
GND2
NC
No Connect
8
Ground, Primary Side
Ground, Secondary Side
No Connect
9
10
11
12
13
14
15
16
V
OB
Output, Channel B
Input, Channel A
V
INA
EN2
NC
Enable, Secondary Side
No Connect
GND2
Ground, Secondary Side
V
DD2
Power Supply, Secondary Side
TRUTH TABLE (Note 1)
V
INX
EN
V
DDI
V
DDO
V
OX
Comment
X
H
H / NC
H / NC
L
Power Up
Power Up
Power Up
Power Up
Power Up
Power Up
Power Up
H
L
Normal Operation
Normal Operation
L
X
X
Hi−Z
L
H / NC
Power
Down
Default low; V return to normal operation when V
OX
DDI
change to Power Up
X
H / NC
Power Up
Power
Down
Undetermined
(Note 2)
V
return to normal operation when V
change to
OX
DDO
Power Up
1. V
= Input signal of a given channel (A or B). EN = Enable pin for primary or secondary side (1 or 2). V = Output signal of a given channel
X OX
INX
(A or B). V
= Input−side V . V
= Output−side V . X = Irrelevant. H = High level. L = Low level. NC = No Connection.
DDI
DD
DDO DD
2. The outputs are in undetermined state when V
< V
.
DDO
UVLO
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2
NCID9211
SAFETY AND INSULATION RATINGS
As per DIN EN/IEC 60747−17, this digital isolator is suitable for “safe electrical insulation” only within the safety limit data. Compliance with
the safety ratings must be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
I–IV
Max.
Units
Installation Classifications per DIN VDE 0110/1.89 Table 1
Rated Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
I–IV
I–IV
I–IV
< 1000 V
I–III
RMS
Climatic Classification
40/125/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
CTI
600
V
PR
Input−to−Output Test Voltage, Method b, V
x 1.875 = V , 100% Production
3750
V
V
IORM
PR
peak
Test with t = 1 s, Partial Discharge < 5 pC
m
Input−to−Output Test Voltage, Method a, V
x 1.6 = V , Type and Sample
3200
IORM
PR
peak
Test with t = 10 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
2000
8000
8.0
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
°C
External Clearance
8.0
Insulation Thickness
0.50
150
T
Safety Limit Values – Maximum Values in Failure;
Case Temperature
Case
P
Safety Limit Values – Maximum Values in Failure;
Input Power
100
600
mW
mW
Ω
S,INPUT
P
Safety Limit Values – Maximum Values in Failure;
Output Power
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
10
IO
IO
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)
A
Symbol
Parameter
Value
Units
T
Storage Temperature
Operating Temperature
Junction Temperature
−55 to +150
−40 to +125
−40 to +150
260 for 10sec
−0.5 to 6
−0.5 to 6
15
°C
°C
°C
°C
V
STG
OPR
T
T
J
T
Lead Solder Temperature (Refer to Reflow Temperature Profile)
Supply Voltage (V
SOL
V
)
DDx
DD
V
Voltage (V , V , ENx)
V
INx
Ox
I
O
Average Output Current
Power Dissipation
mA
mW
PD
210
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
NCID9211
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
−40
2.5
Max.
+125
5.5
Unit
°C
V
T
A
Ambient Operating Temperature
Supply Voltage (Notes 3, 4)
High Level Input Voltage
V
V
DD1 DD2
V
INH
0.7 x V
0
V
DDI
V
DDI
V
INL
Low Level Input Voltage
0.1 x V
V
DDI
V
V
Supply Voltage UVLO Rising Threshold
Supply Voltage UVLO Falling Threshold
Supply Voltage UVLO Hysteresis
High Level Output Current
2.2
2.0
0.1
−2
V
UVLO+
V
UVLO−
UVLO
V
HYS
I
−
mA
mA
Mbps
OH
I
OL
Low Level Output Current
−
2
DR
Signaling Rate
0
50
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. During power up or down, ensure that both the input and output supply voltages reach the proper recommended operating voltages to avoid
any momentary instability at the output state.
4. For reliable operation at recommended operating conditions, V supply pins require at least a pair of external bypass capacitors, placed
DD
within 2 mm from V pins 1 and 16 and GND pins 2 and 15. Recommended values are 0.1 mF and 1 mF.
DD
ISOLATION CHARACTERISTICS
Apply over all recommended conditions. All typical values are measured at T = 25°C.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
ISO
Input−Output Isolation Voltage
T = 25°C, Relative Humidity < 50%,
5000
V
RMS
A
t = 1.0 minute, I
(Notes 5, 6, 7)
v 10 mA, 50 Hz
I−O
11
R
C
Isolation Resistance
Isolation Capacitance
V
I−O
V
I−O
= 500 V (Note 5)
10
ISO
ISO
= 0 V, Frequency = 1.0 MHz (Note 5)
1
pF
5. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
6. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
7. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN EN/IEC 60747−17 Safety and Insulation
Ratings Table on page 3.
ELECTROSTATIC DISCHARGE RATINGS
Symbol
HBM
Parameter
Human Body Model
Charged Device Model
Contact Discharge
Air Discharge
Conditions
Ratings
3000
Units
JS−001−2017; AEC−Q100−002−Rev E (Note 9)
JS−002−2018; AEC−Q100−011−Rev D (Note 10)
IEC 61000−4−2 Insulation Barrier Withstand Test (Note 8)
V
CDM
1000
ESDI
8000
15000
8. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
9. ESD Human Body Model for NCID9211 tested per JEDEC JS−001−2017 standard; NCIV9211 tested per AEC−Q100−002−Rev E standard.
10.ESD Charged Device Model for NCID9211 tested per JEDEC JS−002−2018 standard; NCIV9211 tested per AEC−Q100−011−Rev D
standard.
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4
NCID9211
ELECTRICAL CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C, V
= V
= 2.5 V to 5.5 V, unless otherwise specified. All typical values
A
DD1
DD2
are measured at T = 25°C.
A
Symbol
Parameter
Conditions
= –4 mA
Min. Typ.
– 0.4 V – 0.1
DDO
Max.
Units Figure
V
OH
High Level Output Voltage
Low Level Output Voltage
Rising Input Voltage Threshold
Falling Input Voltage Threshold
Input Threshold Voltage Hysteresis
High Level Input Current
I
I
V
DDO
V
V
7
8
OH
V
OL
= 4 mA
0.11
0.4
OL
V
INT+
0.7 x V
V
DDI
V
INT−
0.1 x V
0.1 x V
V
DDI
V
0.2 x V
V
INT(HYS)
DDI
DDI
I
V
V
= V
DDI
1
μA
μA
kV/ms
pF
INH
IH
I
Low Level Input Current
= 0 V
−1
INL
IL
CMTI
Common Mode Transient Immunity V = V
or 0 V, V = 1500 V
100
150
2
12
I
DDI
CM
C
Input Capacitance
V
= V /2 + 0.4 x sin (2pft),
IN
IN DDI
f = 1MHz, V = 5 V
DD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
SUPPLY CURRENT CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C unless otherwise specified. All typical values are measured at T = 25°C.
A
V
V
V
V
V
V
A
Symbol
Parameter
Conditions
= 5 V, EN = 0 V / 5 V, V = 0 V
Min.
Typ.
4.5
Max.
Units Figure
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DC Supply Current
Input Low
6.3
mA
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD1
DD2
DD
DD
DD
DD
DD
DD
DD
IN
5.0
= 3.3 V, EN = 0 V / 3.3 V, V = 0 V
4.4
6.1
6
IN
4.9
= 2.5 V, EN = 0 V / 2.5 V, V = 0 V
4.3
IN
4.8
DC Supply Current
Input High
= 5 V, EN = 0 V / 5 V, V = 5 V
11.8
12.1
11.7
11.9
11.6
11.8
8.3
14.5
14.3
14.3
10.5
10.3
10.1
12
mA
IN
= 3.3 V, EN = 0 V / 3.3 V, V = 3.3 V
IN
= 2.5 V, EN = 0 V / 2.5 V, V = 2.5 V
IN
AC Supply Current
1 Mbps
V
V
= 5 V, EN = 5 V, C = 15 pF
mA
mA
mA
3,4
L
= 5 V Square Wave
IN
8.7
V
V
= 3.3 V, EN = 3.3 V, C = 15 pF
8.1
DD
IN
L
= 3.3 V Square Wave
8.5
V
V
= 2.5 V, EN = 2.5 V, C = 15 pF
8.0
DD
IN
L
= 2.5 V Square Wave
8.4
AC Supply Current
10 Mbps
V
V
= 5 V, EN = 5 V, C = 15 pF
9.9
DD
IN
L
= 5 V Square Wave
10.2
8.9
V
V
= 3.3 V, EN = 3.3 V, C = 15 pF
11
DD
IN
L
= 3.3 V Square Wave
9.3
V
V
= 2.5 V, EN = 2.5 V, C = 15 pF
8.6
10.5
17.5
14.3
13
DD
IN
L
= 2.5 V Square Wave
9.0
AC Supply Current
50 Mbps
V
V
= 5 V, EN = 5 V, C = 15 pF
14.8
15.2
12.1
12.6
11.1
11.6
DD
IN
L
= 5 V Square Wave
V
V
= 3.3 V, EN = 3.3 V, C = 15 pF
L
= 3.3 V Square Wave
DD
IN
V
V
= 2.5 V, EN = 2.5 V, C = 15 pF
L
= 2.5 V Square Wave
DD
IN
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5
NCID9211
SWITCHING CHARACTERISTICS
Apply over all recommended conditions, T =−40°C to +125°C unless otherwise specified. All typical values are measured at T = 25°C.
A
A
Symbol
Parameter
Conditions
= EN = 5 V, V Square Wave, C = 15 pF
Min.
Typ.
17.0
18.3
20.0
13.0
14.5
16.0
3.6
Max.
Units Figure
t
Propagation Delay
to Logic Low Output
(Note 8)
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
25
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
6,9
PHL
IN
L
= EN = 3.3 V, V Square Wave, C = 15 pF
IN
L
= EN = 2.5 V, V Square Wave, C = 15 pF
IN
L
t
Propagation Delay
to Logic High Output
(Note 9)
= EN = 5 V, V Square Wave, C = 15 pF
25
10
10
PLH
IN
L
= EN = 3.3 V, V Square Wave, C = 15 pF
IN
L
= EN = 2.5 V, V Square Wave, C = 15 pF
IN
L
PWD
Pulse Width Distor-
= EN = 5 V, V Square Wave, C = 15 pF
IN L
tion | t
– t
PLH
|
PHL
= EN = 3.3 V, V Square Wave, C = 15 pF
3.8
IN
L
(Note 10)
= EN = 2.5 V, V Square Wave, C = 15 pF
3.8
IN
L
t
Propagation Delay
Skew (Part to Part)
(Note 11)
= EN = 5 V, V Square Wave, C = 15 pF
−10
PSK(PP)
IN
L
= EN = 3.3 V, V Square Wave, C = 15 pF
IN
L
= EN = 2.5 V, V Square Wave, C = 15 pF
IN
L
t
R
Output Rise Time
(10% to 90%)
= EN = 5 V, V Square Wave, C = 15 pF
1.1
1.5
IN
L
= EN = 3.3 V, V Square Wave, C = 15 pF
IN
L
= EN = 2.5 V, V Square Wave, C = 15 pF
2.2
IN
L
t
F
Output Fall Time
(90% to 10%)
= EN = 5 V, V Square Wave, C = 15 pF
1.1
IN
L
= EN = 3.3 V, V Square Wave, C = 15 pF
1.4
IN
L
= EN = 2.5 V, V Square Wave, C = 15 pF
3.0
IN
L
t
t
High Impedance to
Logic Low Output
Delay (Note 12)
8.1
25
25
1
10
11
= 5 V, R = 1 kW
PZL
L
= 3.3 V, R = 1 kW
9.7
L
= 2.5 V, R = 1 kW
12.0
10.4
12.2
16.5
0.54
0.51
0.50
11.0
12.3
14.0
L
Logic Low to High
Impedance Output
Delay (Note 13)
= 5 V, R = 1 kW
PLZ
L
= 3.3 V, R = 1 kW
L
= 2.5 V, R = 1 kW
L
t
t
High Impedance to
Logic High Output
Delay (Note 14)
= 5 V, R = 1 kW
PZH
L
= 3.3 V, R = 1 kW
L
= 2.5 V, R = 1 kW
L
Logic High to High
Impedance Output
Delay (Note 15)
25
= 5 V, R = 1 kW
PHZ
L
= 3.3 V, R = 1 kW
L
= 2.5 V, R = 1 kW
L
11. Propagation delay t
12.Propagation delay t
is measured from the 50% level of the falling edge of the input pulse to the 50% level of the falling edge of the V signal.
O
PHL
PLH
is measured from the 50% level of the rising edge of the input pulse to the 50% level of the rising edge of the V signal.
O
13.PWD is defined as | t
– t
PLH
| for any given device.
PHL
14.Part−to−part propagation delay skew is the difference between the measured propagation delay times of a specified channel of any two parts
at identical operating conditions and equal load.
15.Enable delay t
is measured from the 50% level of the rising edge of the EN pulse to the 50% of the falling edge of the VO signal as it
PZL
switches from high impedance state to low state.
16.Disable delay t is measured from the 50% level of the falling edge of the EN pulse to 0.5 V level of the rising edge of the V signal as
PLZ
O
it switches from low state to high impedance state.
17.Enable delay t is measured from the 50% level of the rising edge of the EN pulse to the 50% of the rising edge of the VO signal as it switches
PZH
from high impedance state to high state.
18.Disable delay t is measured from the 50% level of the falling edge of the EN pulse to V − 0.5 V level of the falling edge of the V signal
PHZ
OH
O
as it switches from high state to high impedance state.
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6
NCID9211
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
20
T
A = 25°C
T
A = 25°C
IDD1
IDD2
IDD1
IDD2
LOAD = No Load
LOAD = 15 pF
15
10
5
VDD = 3.3 V
VDD = 3.3 V
VDD = 5 V
VDD = 5 V
VDD = 2.5 V
VDD = 2.5 V
0
0
0
10
20
30
40
50
0
10
20
30
40
50
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 3. Supply Current vs. Data Rate (No Load)
Figure 4. Supply Current vs. Data Rate
(Load = 15 pF)
25
20
15
10
5
3.0
tPHL VDD = 2.5 V
tPHL VDD = 3.3 V
tPHL VDD = 5 V
2.5
VUVLO+
VUVLO−
tPLH VDD = 5 V
tPLH VDD = 3.3 V
2.0
tPLH VDD = 2.5 V
1.5
−40
−40
−20
0
20
40
60
80
100
120
−20
0
20
40
60
80
100
120
TA - AMBIENT TEMPERATURE (°C )
TA - AMBIENT TEMPERATURE (°C)
Figure 5. Supply Voltage UVLO Threshold vs.
Ambient Temperature
Figure 6. Propagation Delay vs. Ambient
Temperature
6
1.0
0.8
0.6
0.4
0.2
0.0
T
A = 25 °C
T
A = 25 °C
VDD = 5 V
5
4
3
2
1
0
VDD = 3.3 V
VDD = 2.5 V
VDD = 2.5 V
VDD = 3.3 V
VDD = 5 V
−10
−8
−6
−4
−2
0
0
2
4
6
8
10
I
OH - HIGH LEVEL OUTPUT CURRENT (mA )
I
OL - LOW LEVEL OUTPUT CURRENT (mA )
Figure 7. High Level Output Voltage vs. Current
Figure 8. Low Level Output Voltage vs. Current
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7
NCID9211
TEST CIRCUITS
50%
VI
tPLH
VDDI
VDDO
V
VO
+
−
+
−
tPHL
90%
VIN
VEN
CL
50%
+
−
VO
10%
tR
tF
Figure 9. VIN to VO Propagation Delay Test Circuit and Waveform
RL
50%
VI
VDDI
VDDO
VO
+
−
+
−
tPZL
tPLZ
VI
VIN
VO
0.5 V
CL
+
−
50%
VEN
Figure 10. EN to Logic Low VO Propagation Delay Test Circuit and Waveform
50%
VI
tPZH
VDDI
VDDO
VO
+
−
+
−
tPHZ
VI
VIN
CL
RL
0.5 V
+
50%
−
VO
VEN
Figure 11. EN to Logic High VO Propagation Delay Test Circuit and Waveform
1
VDDI
VDDO
S at 0, VO remain consistently low
S at 1, VO remain consistently high
S at 2, VO data same as VIN data
VIN
VO
2
S
0
VCM
Figure 12. Common Mode Transient Immunity Test Circuit
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8
NCID9211
APPLICATIONS INFORMATION
Theory of Operation
below the components, power plane below the ground plane,
signal lines and power fill on top, and signal lines and ground
fill at the bottom. The alternating polarities of the layers
creates interplane capacitances that aids the bypass
capacitors required for reliable operation at digital
switching rates.
In the layout with digital isolators, it is required that the
isolated circuits have separate ground and power planes. The
section below the device should be clear with no power,
ground or signal traces. Maintain a gap equal to or greater
than the specified minimum creepage clearance of the
device package.
NCID9211 is a dual−channel digital isolator that enables
bi−directional communication between two isolated
circuits. It uses off−chip ceramic capacitors that serve both
as the isolation barrier and as the medium of transmission for
signal switching using on−off keying (OOK) technique,
illustrated in the single channel operational block diagram
in Figure 13.
At the transmitter side, the V input logic state is
IN
modulated with a high frequency carrier signal. The
resulting signal is amplified and transmitted to the isolation
barrier. The receiver side detects the barrier signal and
demodulates it using an envelope detection technique. The
output signal determines the V output logic state when the
O
Signal Lines / VDD2 Fill
GND2 Plane
Signal Lines / VDD1 Fill
GND1 Plane
output enable control EN is at high. When EN is at low,
output V is at high impedance state. V is at default state
No Trace
O
O
VDD1 Plane
VDD2 Plane
low when the power supply at the transmitter side is turned
off or the input V is disconnected.
Signal Lines / GND1 Fill
Signal Lines / GND2 Fill
IN
Figure 16. 4−Layer PCB for Digital Isolator
ISOLATION
TRANSMITTER
EN
VO
RECEIVER
BARRIER
For NCID9211, it is highly advised to connect at least a
pair of low ESR supply bypass capacitors, placed within
2mm from the power supply pins 1 and 16 and ground pins
2 and 15. Recommended values are 1 mF and 0.1 mF,
TX
Amplif ier
OOK
Modulator
RX
Amplif ier
Envelope
Detec tor
IO
VIN
OFF− CHIP
CAPACITORS
OSC
Figure 13. Operational Block Diagram of
Single Channel
respectively. Place them between the V pins of the device
DD
and the via to the power planes, with the higher frequency,
lower value capacitor closer to the device pins. Directly
connect the device ground pins 1, 8, 9 and 15 by via to their
corresponding ground planes.
VIN
ISOLATION
BARRIER
1μF 0.1μF
0.1μF 1μF
VDD1
VDD2
GND2
GND1
VO
Figure 14. On−Off Keying Modulation Signals
OFF− CHIP CAPACITIVE
ISOLATION BARRIER
GND1
GND2
EN1
VOA
VINA
IO
+
VTX
−
RX
TX
IO
IO
TX
RX
Figure 17. Placement of Bypass Capacitors
OSC
EN2
VOB
VINB
Over Temperature Detection
+
VTX
−
IO
NCID9211 has a built−in Over Temperature Detection
(OTD) feature that protects the IC from thermal damage.
The output pins will automatically switch to default state
when the ambient temperature exceeds the maximum
junction temperature at threshold of approximately 160°C.
The device will return to normal operation when the
temperature decreases approximately 20°C below the OTD
threshold.
OSC
Figure 15. NCID9211 Operational Block Diagram
Layout Recommendation
Layout of the digital circuits relies on good suppression of
unwanted noise and electromagnetic interference. It is
recommended to use 4−layer FR4 PCB, with ground plane
www.onsemi.com
9
NCID9211
ORDERING INFORMATION
Part Number
†
Grade
Package
SOIC16 W
SOIC16 W
SOIC16 W
SOIC16 W
Shipping
NCID9211
Industrial
Industrial
Automotive
Automotive
50 Units / Tube
750 Units / Tape & Reel
50 Units / Tube
NCID9211R2
NCIV9211* (pending)
NCIV9211R2* (pending)
750 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC16 W
CASE 751EN
ISSUE A
DATE 24 AUG 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AWLYWW
XXXXXXXXXX
XXXXXXXXXX
Y
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13751G
SOIC16 W
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
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