NCL30083_15 [ONSEMI]
Dimmable Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Thermal Fold-back;
| 型号： | NCL30083_15 |
| 厂家： | 
ONSEMI |
| 描述： | Dimmable Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Thermal Fold-back |
| 文件： | 总35页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30083
Dimmable Quasi-Resonant
Primary Side Current-Mode
Controller for LED Lighting
with Thermal Fold-back
www.onsemi.com
The NCL30083 is a PWM current mode controller targeting isolated
flyback and non−isolated constant current topologies. The controller
operates in a quasi−resonant mode to provide high efficiency. Thanks
to a novel control method, the device is able to precisely regulate a
constant LED current from the primary side. This removes the need
for secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs. It supports step dimming by monitoring the AC line
and detecting when the line has been toggled on−off−on by the user to
reduce the light intensity in 5 steps down to 5% dimming.
8
8
1
1
Micro8
SOIC−8
D SUFFIX
CASE 751
DM SUFFIX
CASE 846A
MARKING DIAGRAM
8
AAx
AYWG
G
Features
• Quasi−resonant Peak Current−mode Control Operation
• Primary Side Sensing (no optocoupler needed)
1
AAx
x
A
= Specific Device Code
= E or F
= Assembly Location
= Year
• Wide V Range
CC
• Source 300 mA/Sink 500 mA Totem Pole Driver with 12 V Gate Clamp
• Precise LED Constant Current Regulation 1% Typical
• Line Feed−forward for Enhanced Regulation Accuracy
• Low LED Current Ripple
Y
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
8
• 250 mV 2% Guaranteed Voltage Reference for Current Regulation
• ~ 0.9 Power Factor with Valley Fill Input Stage
• Low Start−up Current (13 mA typ.)
L30083x
ALYW
G
1
• 5 State Quasi−log Dimmable
L30083x = Specific Device Code
x
• Thermal Fold−back
= B
• Programmable soft−start
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Wide Temperature Range of −40 to +125°C
• Pb−free, Halide−free MSL1 Product
• Robust Protection Features
♦ Over Voltage / LED Open Circuit Protection
♦ Over Temperature Protection
♦ Latched and Auto−recoverable Versions
♦ Brown−out
PIN CONNECTIONS
♦ V Under Voltage Lockout
CC
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Pin Fault Detection
1
♦ Thermal Shutdown
SD
SS
ZCD
CS
GND
VIN
VCC
DRV
Typical Applications
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 35 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
January, 2015 − Rev. 2
NCL30083/D
NCL30083
.
.
Aux
.
1
2
3
4
8
7
6
5
Figure 1. Typical Application Schematic for NCL30083
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
SD
Thermal Fold−back
and shutdown
Connecting an NTC to this pin allows reducing the output current down to 50%
of its fixed value before stopping the controller. A Zener diode can also be
used to pull−up the pin and stop the controller for adjustable OVP protection
2
3
4
5
ZCD
CS
Zero Crossing Detection
Current sense
−
Connected to the auxiliary winding, this pin detects the core reset event.
This pin monitors the primary peak current
The controller ground
GND
DRV
Driver output
The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suit-
able to effectively drive a broad range of power MOSFETs.
6
7
VCC
VIN
Supplies the controller
This pin is connected to an external auxiliary voltage.
Brown−Out
Input voltage sensing
This pin observes the HV rail and is used in valley selection. This pin also
monitors and protects for low mains conditions.
8
SS
Soft−Start
A capacitor connected to ground select the soft−start duration.
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2
NCL30083
CS_shorted
Enable
V
REF
V
DD
STOP
Over Voltage
Protection
Aux_SCP
OFF
VCC
UVLO
Latch
Fault
Management
VCC Management
Over Temperature
Protection
Internal
Thermal
Shutdown
VCC_max
VCC Over Voltage
Protection
SD
Ipkmax
Thermal
Foldback
V
TF
WOD_SCP
BO_NOK
Qdrv
V
VIN
V
REF
V
CC
Clamp
Circuit
Zero Crossing Detection
offset_OK
ZCD
Valley Selection
Aux. Winding
DRV
Short Circuit Prot.
S
R
Qdrv
Aux_SCP
Q
V
VIN
offset_OK
V
VLY
Line
Feedforward
V
STOP
V
TF
REF
SS
CS
Leading
Edge
Blanking
CS_reset
V
SST
Constant−Current
Control
Soft−Start
Enable
Ipkmax
STOP
Enable
STEP_DIM
Ipkmax
V
SST
Max. Peak
Current
Limit
V
VIN
VIN
Step
Dimming
Brown−Out
BO_NOK
STEP_DIM
CS Short
Protection
CS_shorted
V
VIN
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
GND
Figure 2. Internal Circuit Architecture
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3
NCL30083
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3, +35
V
CC(MAX)
I
Internally limited
mA
CC(MAX)
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
DRV(MAX)
DRV
I
−500, +800
mA
DRV(MAX)
V
Maximum voltage on low power pins (except pins ZCD, SS, DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3, +5.5
−2, +5
V
MAX
I
mA
MAX
V
Maximum voltage for ZCD pin
Maximum current for ZCD pin
−0.3, +10
−2, +5
V
ZCD(MAX)
I
mA
ZCD(MAX)
V
Maximum voltage for SS pin
Thermal Resistance, Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
−0.3, +10
289
V
°C/W
°C
SST(MAX)
R
θ
J−A
T
150
J(MAX)
−40 to +125
−60 to +150
4
°C
°C
ESD Capability, HBM model (Note 2)
ESD Capability, MM model (Note 2)
kV
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V unless otherwise noted.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
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4
NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V;
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
increasing
decreasing
decreasing
V
V
16
8.2
8
18
8.8
–
20
9.4
–
CC
CC(on)
Minimum Operating Voltage
V
CC
V
CC
CC(off)
Hysteresis V
– V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset
V
3.5
4.5
5.5
Over Voltage Protection
VCC OVP threshold
V
26
28
30
V
CC(OVP)
V
V
noise filter
t
–
–
5
–
–
ms
CC(off)
VCC(off)
noise filter−
t
I
20
CC(reset)
VCC(reset)
Startup current
I
–
–
13
46
30
60
mA
mA
CC(start)
Startup current in fault mode
CC(sFault)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
0.8
–
1.2
2.3
2.7
1.4
4.0
5.0
CC
CC(off)
CC1
CC2
CC3
Device Enabled/No output load on pin 5
F
= 65 kHz
sw
Device Switching (F = 65 kHz)
C
= 470 pF,
= 65 kHz
–
sw
DRV
F
sw
CURRENT SENSE
Maximum Internal current limit
Leading Edge Blanking Duration for V
V
0.95
250
1
1.05
350
V
ILIM
t
300
ns
ILIM
LEB
(T = −25°C to 125°C)
j
Leading Edge Blanking Duration for V
t
240
300
350
ns
ILIM
LEB
(T = −40°C to 125°C)
j
Input Bias Current
DRV high
I
–
–
0.02
50
1.5
120
–
–
150
1.65
–
mA
ns
V
bias
Propagation delay from current detection to gate off−state
Threshold for immediate fault protection activation
t
ILIM
V
1.35
–
CS(stop)
Leading Edge Blanking Duration for V
t
ns
ms
ms
CS(stop)
BCS
Blanking time for CS to GND short detection V
= 1 V
t
t
6
12
4
pinVIN
CS(blank1)
CS(blank2)
Blanking time for CS to GND short detection V
= 3.3 V
2
–
pinVIN
GATE DRIVE
Drive Resistance
DRV Sink
DRV Source
W
R
SNK
R
SRC
–
–
13
30
–
–
Drive current capability
DRV Sink (Note 4)
DRV Source (Note 4)
mA
I
I
–
–
500
300
–
–
SNK
SRC
Rise Time (10% to 90%)
Fall Time (90% to 10%)
DRV Low Voltage
C
C
= 470 pF
t
–
–
8
40
30
–
–
–
–
ns
ns
V
DRV
DRV
r
= 470 pF
t
f
V
= V
+0.2 V
CC(off)
V
CC
DRV(low)
C
= 470 pF,
DRV
R
= 33 kW
DRV
DRV High Voltage
V
DRV
= 30 V
= 470 pF,
= 33 kW
V
10
12
14
V
CC
DRV(high)
C
R
DRV
4. Guaranteed by design
5. OTP triggers when R
= 4.7 kW
NTC
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5
NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V;
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
ZERO VOLTAGE DETECTION CIRCUIT
ZCD threshold voltage
V
increasing
decreasing
increasing
V
25
5
45
25
–
65
45
–
mV
mV
mV
V
ZCD
ZCD(THI)
ZCD(THD)
ZCD(HYS)
ZCD(short)
ZCD threshold voltage (Note 4)
ZCD hysteresis (Note 4)
V
ZCD
V
V
V
ZCD
10
0.8
Threshold voltage for output short circuit or aux. winding
short circuit detection
V
1
1.2
Short circuit detection Timer
Auto−recovery timer duration
V
ZCD
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD(short)
t
recovery
Input clamp voltage
High state
Low state
V
I
= 3.0 mA
= −2.0 mA
V
V
–
−0.9
9.5
−0.6
–
−0.3
pin1
CH
I
pin1
CL
Propagation Delay from valley detection to DRV high
Equivalent time constant for ZCD input (Note 4)
Blanking delay after on−time
V
ZCD
decreasing
t
–
–
–
20
3
150
–
ns
ns
ms
ms
DEM
t
PAR
t
2.25
5
3.75
8
BLANK
Timeout after last demag transition
t
6.5
TIMO
CONSTANT CURRENT CONTROL
Reference Voltage at T = 25°C
V
V
245
250
250
175
100
62.5
25
255
mV
mV
mV
mV
mV
mV
mV
mV
j
REF
Reference Voltage T = −40°C to 125°C
242.5
257.5
j
REF
70% reference voltage
40% reference Voltage
25% reference Voltage
10% reference Voltage
5% reference Voltage
V
REF70
V
REF40
V
REF25
V
REF10
V
REF05
–
–
–
–
–
–
–
–
–
12.5
55
–
Current sense lower threshold for detection of the
leakage inductance reset time
V
30
80
CS(low)
LINE FEED−FORWARD
V
to I
conversion ratio
K
15
67.5
–
17
76.5
37.5
50
19
85.5
–
mA/V
mA
VIN
CS(offset)
LFF
I
offset(MAX)
Offset current maximum value
V
= 4.5 V
pinVIN
V
value below which the offset current source is turned off
value above which the offset current source is turned on
V
REF
decreases
increases
V
V
mV
mV
REF
REF
REF(off)
REF(on)
V
V
REF
–
–
VALLEY SELECTION
Threshold for line range detection V increasing
V
increases
decreases
V
HL
2.28
2.18
15
2.4
2.3
25
2.52
2.42
35
V
V
in
VIN
st
nd
(1 to 2 valley transition for V
> 0.75 V)
REF
Threshold for line range detection V decreasing
V
VIN
V
LL
in
nd
st
(2 to 1 valley transition for V
> 0.75 V)
REF
Blanking time for line range detection
4. Guaranteed by design
t
ms
HL(blank)
5. OTP triggers when R
= 4.7 kW
NTC
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NCL30083
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V;
J
CC
For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
VALLEY SELECTION
Valley thresholds
mV
st
nd
nd
rd
1
2
2
4
4
7
7
to 2 valley transition at LL and 2 to 3 valley HL
V
V
V
V
V
decreases
increases
decreases
increases
decreases
increases
decreases
increases
decreases
increases
V
V
V
V
V
V
177.5 187.5 197.5
185.0 195.0 205.0
117.5 125.0 132.5
125.0 132.5 140.0
REF
VLY1−2/2−3
VLY2−1/3−2
VLY2−4/3−5
VLY4−2/5−3
VLY4−7/5−8
VLY7−4/8−5
nd
nd
th
th
th
th
st
rd
nd
to 1 valley transition at LL and 3 to 2 valley HL
V
REF
REF
th
rd
th
to 4 valley transition at LL and 3 to 5 valley HL
nd
th
rd
to 2 valley transition at LL and 5 to 3 valley HL
V
REF
REF
th
th
th
to 7 valley transition at LL and 5 to 8 valley HL
–
–
–
–
–
–
75.0
82.5
37.5
50.0
15.0
20.0
–
–
–
–
–
–
th
th
th
to 4 valley transition at LL and 8 to 5 valley HL
V
REF
REF
th
th
th
to 11 valley transition at LL and 8 to 12 valley HL
V
V
VLY7−11/8−12
VLY11−7/12−8
th
th
th
th
11 to 7 valley transition at LL and 12 to 8 valley HL
V
REF
REF
th
th
th
th
11 to 13 valley transition at LL and 12 to 15 valley HL
V
V
VLY11−13/12−15
VLY13−11/15−12
th
th
th
th
13 to 11 valley transition at LL and 15 to 12 valley HL
V
REF
SOFT−STAT PIN
SS pin voltage for zero output current (enable)
SS pin voltage for 100% of output current
Clamping voltage for SS pin
V
0.66
2.25
–
0.7
2.45
7.8
0.74
2.65
–
V
V
SST(EN)
V
SST100
V
V
SST(CLP)
Soft−start current source
I
8.5
–
10
11.5
–
mA
mA
SST
SST(pre)
Pre−charge current source
V
SST
< V
I
100
SST(EN)
THERMAL FOLD−BACK AND OVP
SD pin voltage at which thermal fold−back starts
SD pin voltage at which thermal fold−back stops
V
0.9
1
1.2
V
V
TF(start)
V
0.64
0.68
0.72
TF(stop)
(I = 50% I
)
out
out(nom)
Reference current for direct connection of an NTC (Note 5)
Fault detection level for OTP (Note 5)
I
80
85
0.5
90
mA
V
OTP(REF)
V
decreasing
increasing
V
0.47
0.64
0.53
0.72
SD
OTP(off)
OTP(on)
SD pin level at which controller re−start switching after OTP
detection
V
V
0.68
V
SD
Timer duration after which the controller is allowed to start
pulsing (Note 5)
t
180
–
300
ms
OTP(start)
Clamped voltage (SD pin left open)
Clamp series resistor
SD pin open
V
1.13
–
1.35
1.6
2.5
30
1.57
–
V
kW
V
SD(clamp)
R
SD(clamp)
SD pin detection level for OVP
Delay before OVP or OTP confirmation (OVP and OTP)
THERMAL SHUTDOWN
V
SD
increasing
V
OVP
2.35
15
2.65
45
T
ms
SD(delay)
Thermal Shutdown (Note 4)
Device switching
around 65 kHz)
T
130
–
155
55
170
–
°C
°C
SHDN
(F
SW
Thermal Shutdown Hysteresis (Note 4)
BROWN−OUT
T
SHDN(HYS)
Brown−Out ON level (IC start pulsing)
Brown−Out OFF level (IC shuts down)
BO comparators delay
V
increasing
decreasing
V
V
0.90
0.85
–
1
0.9
30
50
–
1.10
0.95
–
V
V
SD
BO(on)
V
SD
BO(off)
t
ms
ms
nA
BO(delay)
BO(blank)
Brown−Out blanking time
t
35
65
Brown−out pin bias current
4. Guaranteed by design
I
−250
250
BO(bias)
5. OTP triggers when R
= 4.7 kW
NTC
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NCL30083
TYPICAL CHARACTERISTICS
18.20
18.15
18.10
18.05
18.00
8.90
8.85
8.80
8.75
8.70
17.95
17.90
8.65
8.60
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
27.80
27.75
18
17
16
15
14
13
12
27.70
27.65
27.60
27.55
27.50
11
10
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. ICC(start) vs. Junction Temperature
52
50
48
46
44
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
42
40
1.14
1.12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. ICC(sFault) vs. Junction Temperature
Figure 8. ICC1 vs. Junction Temperature
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NCL30083
TYPICAL CHARACTERISTICS
2.40
2.35
2.30
2.25
2.20
2.85
2.80
2.75
2.70
2.65
2.60
2.55
2.15
2.10
2.50
2.45
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 9. ICC2 vs. Junction Temperature
Figure 10. ICC3 vs. Junction Temperature
1.000
0.995
1.495
1.490
1.485
0.990
0.985
0.980
1.480
1.475
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. VILIM vs. Junction Temperature
Figure 12. VCS(stop) vs. Junction Temperature
305
303
1.010
1.005
1.000
0.995
0.990
301
299
297
295
293
291
289
0.985
0.980
287
285
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. tLEB vs. Junction Temperature
Figure 14. VZCD(short) vs. Junction
Temperature
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NCL30083
TYPICAL CHARACTERISTICS
3.20
3.15
3.10
7.1
7.0
6.9
6.8
6.7
3.05
3.00
6.6
6.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. tBLANK vs. Junction Temperature
Figure 16. tTIMO vs. Junction Temperature
255
254
253
180
179
178
177
252
251
176
175
250
249
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. VREF vs. Junction Temperature
Figure 18. VREF70 vs. Junction Temperature
105
104
103
102
67.0
66.5
66.0
65.5
65.0
101
100
64.5
64.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 19. VREF40 vs. Junction Temperature
Figure 20. VREF25 vs. Junction Temperature
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10
NCL30083
TYPICAL CHARACTERISTICS
30.0
29.5
29.0
28.5
28.0
27.5
27.0
18.0
17.5
17.0
16.5
16.0
15.5
15.0
26.5
26.0
14.5
14.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 21. VREF10 vs. Junction Temperature
Figure 22. VREF05 vs. Junction Temperature
16.60
16.55
16.50
16.45
16.40
55.0
54.5
54.0
53.5
53.0
16.35
16.30
52.5
52.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 23. VCS(low) vs. Junction Temperature
Figure 24. KLFF vs. Junction Temperature
37.6
37.5
37.4
37.3
37.2
49.0
48.5
48.0
47.5
47.0
46.5
46.0
45.5
45.0
37.1
37.0
44.5
44.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 25. VREF(off) vs. Junction Temperature
Figure 26. VREF(on) vs. Junction Temperature
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11
NCL30083
TYPICAL CHARACTERISTICS
2.400
2.395
2.300
2.295
2.290
2.285
2.280
2.390
2.385
2.380
2.375
2.370
2.275
2.270
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 27. VHL vs. Junction Temperature
Figure 28. VLL vs. Junction Temperature
187.0
186.5
186.0
185.5
185.0
28.0
27.5
27.0
26.5
26.0
184.5
184.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 29. tHL(BLANK) vs. Junction Temperature
Figure 30. VVLY1−2/2−3 vs. Junction
Temperature
198
197
196
195
194
193
125.0
124.5
124.0
123.5
123.0
122.5
122.0
192
191
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 31. VVLY2−1/3−2 vs. Junction
Temperature
Figure 32. VVLY2−4/3−5 vs. Junction
Temperature
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12
NCL30083
TYPICAL CHARACTERISTICS
136
135
134
133
132
76.0
75.5
75.0
74.5
74.0
131
130
73.5
73.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 33. VVLY4−2/5−3 vs. Junction
Temperature
Figure 34. VVLY4−7/5−8 vs. Junction
Temperature
37.7
87
86
85
37.6
37.5
37.4
37.3
37.2
84
83
82
81
80
37.1
37.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 35. VVLY7−4/8−5 vs. Junction
Temperature
Figure 36. VVLY7−11/8−12 vs. Junction
Temperature
50
49
48
47
46
45
15.10
15.05
15.00
14.95
14.90
14.85
14.80
44
43
14.75
14.70
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 37. VVLY11−7/12−8 vs. Junction
Temperature
Figure 38. VVLY11−13/12−15 vs. Junction
Temperature
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13
NCL30083
TYPICAL CHARACTERISTICS
21.0
20.5
20.0
19.5
0.710
0.705
0.700
19.0
18.5
18.0
0.695
0.690
17.5
17.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 39. VVLY13−11/15−12 vs. Junction
Temperature
Figure 40. VSST(EN) vs. Junction Temperature
2.46
2.45
10.10
10.05
10.00
9.95
9.90
9.85
9.80
2.44
2.43
2.42
9.75
9.70
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 41. VSST(100) vs. Junction Temperature
Figure 42. ISST vs. Junction Temperature
100
99
98
97
96
88.0
87.5
87.0
86.5
86.0
85.5
85.0
95
94
84.5
84.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 43. ISST(pre) vs. Junction Temperature
Figure 44. tOVLD vs. Junction Temperature
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14
NCL30083
TYPICAL CHARACTERISTICS
4.55
4.50
4.45
4.40
2.500
2.495
2.490
2.485
2.480
4.35
4.30
2.475
2.470
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 45. trecovery vs. Junction Temperature
Figure 46. VOVP vs. Junction Temperature
86.5
86.0
85.5
85.0
84.5
0.690
0.688
0.686
0.684
84.0
0.682
0.680
83.5
83.0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 47. IOTP(ref) vs. Junction Temperature
Figure 48. VOTP(on), VTF(stop) vs. Junction
Temperature
0.994
0.992
0.990
0.988
0.986
0.997
0.995
0.993
0.991
0.989
0.984
0.982
0.987
0.985
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 49. VTF(start) vs. Junction Temperature
Figure 50. VBO(on) vs. Junction Temperature
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15
NCL30083
TYPICAL CHARACTERISTICS
0.906
0.904
0.902
0.900
56.0
55.5
55.0
54.5
54.0
53.5
0.898
0.896
53.0
52.5
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 51. VBO(off) vs. Junction Temperature
Figure 52. tBO(BLANK) vs. Junction
Temperature
APPLICATION INFORMATION
The NCL30083 implements a current−mode architecture
operating in quasi−resonant mode. Thanks to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current of the flyback converter without
using any opto−coupler or measuring directly the secondary
side current.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30083 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Thanks to a smart control
algorithm, the controller locks−out in a selected valley
and remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allow accurate control of the secondary
side current.
• Line Feed−forward: compensation for possible
variation of the output current caused by system slew
rate variation.
temperature continues to increase, the current will be
further reduced until the controller is stopped. The
control will automatically restart if the temperature is
reduced. This pin can implement a programmable OVP
shutdown that can also auto−restart the device.
• Brown−Out: the controller includes a brown−out
circuit which safely stops the controller in case the
input voltage is too low. The device will automatically
restart if the line recovers.
• Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold V
, the
ILIM
MOSFET is turned off for the rest of the switching
cycle.
• Winding Short−Circuit Protection: an additional
comparator with a short LEB filter (t ) senses the CS
BCS
signal and stops the controller if V reaches 1.5 x
CS
V . For noise immunity reasons, this comparator is
ILIM
enabled only during the main LEB duration t
.
LEB
• Output Short−circuit protection: If a very low
voltage is applied on ZCD pin for 90 ms (nominal), the
controllers assume that the output or the ZCD pin is
shorted to ground and enters shutdown. The
• Open LED protection: if the voltage on the VCC pin
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
auto−restart version (B suffix) waits 4 seconds, then the
controller restarts switching. In the latched version (A
suffix), the controller is latched as long as V stays
CC
above the V
threshold.
• Thermal Fold−back / Over Temperature / Over
Voltage Protection: by combining a dual threshold on
the SD pin, the controller allows the direct connection
of an NTC to ground plus a Zener diode to a monitored
voltage. The temperature is monitored and the output
current is linearly reduced in the event that the
CC(reset)
• Soft−start: The soft−start pin can be used to slowly
increase the output current at startup and provide a
smooth turn−on of the LED light.
• Step dimming: Each time the IC detects a brown−out
condition, the output current is decreased by discrete
steps.
temperature exceeds a prescribed level. If the
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16
NCL30083
Constant Current Control
Figure 54 portrays the primary and secondary current of
a flyback converter in discontinuous conduction mode
(DCM). Figure 53 shows the basic circuit of a flyback
converter.
Transformer
V
bulk
L
leak
N
sp
R
clp
V
out
C
clp
L
p
Clamping
network
DRV
C
lump
R
sense
Figure 53. Basic Flyback Converter Schematic
During the on−time of the MOSFET, the bulk voltage
is applied to the magnetizing and leakage inductors L
When the diode conducts, the secondary current decreases
linearly from I to zero. When the diode current has
V
bulk
p
D,pk
and L
and the current ramps up.
turned off, the drain voltage begins to oscillate because of
the resonating network formed by the inductors (L +L
leak
When the MOSFET is turned−off, the inductor current
first charges C . The output diode is off until the voltage
across L reverses and reaches:
)
leak
p
and the lump capacitor. This voltage is reflected on the
auxiliary winding wired in flyback mode. Thus, by looking
at the auxiliary winding voltage, we can detect the end of the
conduction time of secondary diode. The constant current
control block picks up the leakage inductor current, the end
of conduction of the output rectifier and controls the drain
current to maintain the output current constant.
lump
p
ǒ
Ǔ
Nsp Vout ) Vf
(eq. 1)
The output diode current increase is limited by the leakage
inductor. As a consequence, the secondary peak current is
reduced:
We have:
IL,pk
ID,pk
t
(eq. 2)
VREF
2NspRsense
Nsp
(eq. 3)
Iout
+
The diode current reaches its peak when the leakage inductor
is reset. Thus, in order to accurately regulate the output
current, we need to take into account the leakage inductor
current. This is accomplished by sensing the clamping
network current. Practically, a node of the clamp capacitor
The output current value is set by choosing the sense
resistor:
Vref
(eq. 4)
Rsense
+
2NspIout
is connected to R
Then, by reading the voltage on the CS pin, we have an
image of the primary current (red curve in Figure 54).
instead of the bulk voltage V
.
sense
bulk
From Equation 3, the first key point is that the output
current is independent of the inductor value. Moreover, the
leakage inductance does not influence the output current
value as the reset time is taken into account by the controller.
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17
NCL30083
I
L,pk
N
I
sp D,pk
I
pri
(t)
I
(t)
sec
time
t
1
t
2
t
on
t
demag
V
aux
(t)
time
Figure 54. Flyback Currents and Auxiliary Winding Voltage in DCM
Internal Soft−Start
At startup or after recovering from a fault, there is a small
internal soft−start of 40 ms.
In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak current
towards its nominal value as the output voltage grows.
Figure 55 shows a soft−start simulation example for a 9 W
LED power supply.
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18
NCL30083
16.0
12.0
8.00
4.00
0
V
out
1
800m
600m
400m
200m
0
I
2
out
800m
600m
400m
200m
0
V
V
4
3
Control
CS
604u
1.47m
2.34m
3.21m
4.07m
time in seconds
Figure 55. Startup Simulation Showing the Natural Soft−start
Cycle−by−Cycle Current Limit
Winding and Output Diode Short−Circuit Protection
When the current sense voltage exceeds the internal
In parallel with the cycle−by−cycle sensing of the CS pin,
threshold V , the MOSFET is turned off for the rest of the
ILIM
another comparator with a reduced LEB (t ) and a higher
BCS
switching cycle (Figure 56).
threshold (1.5 V typical) is able to sense winding
short−circuit and immediately stops the DRV pulses. The
controller goes into auto−recovery mode in version B.
In version A, the controller is latched. In latch mode, the
DRV pulses stop and VCC ramps up and down. The circuit
un−latches when VCC pin voltage drops below V
threshold.
CC(reset)
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19
NCL30083
S
aux
DRV
Q
Vdd
Q
latch
VCC
CS
R
Vcc
management
LEB1
+
−
PWMreset
Ipkmax
Rsense
Vcontrol
VCCstop
UVLO
+
−
grand
reset
8_HICC
OVP
V
ILIMIT
OVP
STOP
LEB2
+
−
WOD_SCP
latch
S
OFF
WOD_SCP
S
R
V
Q
Q
CS(stop)
Q
Q
R
8_HICC
grand
reset
from Fault Management Block
Figure 56. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
Thermal Fold−back and Over Voltage / Over
Temperature Protection
If V drops below V , the controller enters into the
auto−recovery fault mode for version B, meaning that the
4−s timer is activated. The controller will re−start switching
SD
OTP
The thermal fold−back circuit reduces the current in the
LED string when the ambient temperature exceeds a set
point. The current is gradually reduced to 50% of its nominal
value if the temperature continues to rise. (Figure 58). The
thermal foldback starting temperature depends on the
Negative Coefficient Temperature (NTC) resistor chosen by
the power supply designer.
after the 4−s timer has elapsed and when V > V
to
SD
OTP(on)
provide some temperature hysteresis (around 10°C).
For version A, this protection is latched: reset occurs when
< V
V
.
CC(reset)
CC
The thermal fold−back and OTP thresholds correspond
roughly to the following resistances:
Indeed, the SD pin allows the direct connection of an NTC
to sense the ambient temperature. When the SD pin voltage
• Thermal fold−back starts when R
≤ 11.76 kW.
≤ 8.24 kW.
NTC
• Thermal fold−back stops when R
NTC
V
SD
drops below V
, the internal reference for the
TF(start)
• OTP triggers when R
≤ 5.88 kW.
NTC
constant current control V
is decreased proportionally to
REF
• OTP is removed when R
≥ 8.24 kW.
NTC
V
V
. When V reaches V
, V
is clamped to
SD
SD
TF(stop)
REF
, corresponding to 50% of the nominal output
REF50
current.
I
out
I
out(nom)
50% I
out(nom)
V
SD
V
TF(start)
V
V
V
OTP(off)
TF(stop)
OTP(on)
Figure 57. Output Current Reduction versus SD Pin Voltage
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20
NCL30083
At startup, when V reaches V
not allowed to start pulsing for at least 180 ms in order to
, the controller is
filtering capacitor is connected to the SD pin. This is to avoid
flickering of the LED light in case of over temperature.
CC
CC(on)
allow the SD pin voltage to reach its nominal value if a
V
OVP
VCC
Vdd
noise delay
OVP
−
Dz
+
I
OTP(REF)
S
OFF
Q
Q
SD
OTP_Timer end
Rclamp
Vclamp
noise delay
R
−
+
OTP
NTC
4−s Timer
(OTP latched for version A)
S
0.5 V if OTP low
0.7 V if OTP high
V
OTP
Latch
Q
Q
V
TF
R
VCCreset
Figure 58. Thermal Fold−back and OVP/OTP Circuitry
In case of over voltage, the Zener diode starts to conduct
and inject current inside the internal clamp resistor R
thus causing the pin SD voltage to increase. When this
voltage reaches the OVP threshold (2.5 V typ.), the
controller shuts−down and waits for at least 4 seconds before
restarting switching.
clamp
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21
NCL30083
V
CC
V
V
CC(on)
CC(off)
V
CC
> V
:
CC(on)
DRV pulses restart
V
CC(reset)
V
DRV
4−s Timer
V
> V
:
SD
OVP
4−s timer has elapsed:
waiting for V > V
to restart DRV pulses
V
SD
controller stops
switching
CC
CC(on)
V
OVP
V
SD(clamp)
V
out
Figure 59. OVP with SD Pin Chronograms
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22
NCL30083
V
CC
V
CC(on)
V
CC(off)
V
CC(reset)
V
DRV
V
V
> V
> V
and
TF(stop)
SD
4−s Timer
:
CC
CC(on)
DRV pulses restart
V
< V
:
4−s timer has elapsed
SD
OTP(off)
V
SD
controller stops
switching
but V < V
SD
TF(stop)
≥ no restart
V
TF(start)
V
TF(stop)
OTP(off)
V
I
out
Figure 60. Thermal Fold−back / OTP Chronograms
Soft−Start
The NCL30083 provides a soft−start pin allowing
increasing slowly the LEDs light at startup. An internal
in parallel with I
charges the soft−start capacitor until it
SST
reaches the V
threshold. After that, I
is turned
SST(EN)
SST(pre)
current source I
generated voltage ramp directly controls the amount of
current flowing in the LEDs.
charges the soft−start capacitor. The
off and the soft−start capacitor keep on charging with the
soft−start current source I
When a fault is detected, the soft−start pin is discharged
SST
.
SST
At startup, if there are no faults (except “Enable_b” high),
down to V
to provide a clean soft−start when the fault
SST(EN)
an internal pre−charging current source I
connected
is removed.
SST(pre)
VCC
Clamp
Circuit
DRV
S
R
Qdrv
V
dd
Q
Q
V
SST
Output
Buffer 1
I
I
SST(pre)
SST
SST
−
Enable_b
+
CS_reset
STOP
V
SST(EN)
7.4V clamp
STOP
Figure 61. Soft−start Pin Bloc Diagram
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23
NCL30083
Step Dimming
Note:
The step dimming function decreases the output current
from 100% to 5% of its nominal value in discrete steps.
There are 5 steps in total. Table 4 shows the different steps
value and the corresponding output current set−point. Each
time a brown−out is detected, the output current is decreased
The power supply designer must ensure that V stays
high enough when the light is turned−off to let the controller
memorize the dimming step state.
CC
The power supply designer should use a split V circuit
CC
for step dimming with a capacitor allowing providing
by decreasing the reference voltage V
current value.
setting the output
enough V for 1 s (47 mF to 100 mF capacitor).
The step dimming state is memorized by the controller
REF
CC
When the 5% dimming step is reached, if a brown−out
event occurs, the controller restarts at 100% of the output
current.
until V crosses V
.
CC
CC(reset)
Table 4. DIMMING STEPS
Dimming Step
I
Perceived Light
out
ON
1
100%
70%
40%
25%
10%
5%
100%
84%
63%
50%
32%
17%
VCC
2
3
4
5
4.7 mF
47 − 100 mF
Figure 62. Split VCC Supply
V
bulk
V
V
bulk(on)
bulk(off)
V
CC
V
CC(on)
V
CC(off)
V
CC(reset)
BO
comp
100%
I
out
70%
40%
25%
10%
5%
Figure 63. Step Dimming Chronograms
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24
NCL30083
VCC Over Voltage Protection (Open LED Protection)
If no output load is connected to the LED power supply,
the controller must be able to safely limit the output voltage
excursion.
In the NCL30083, when the V voltage reaches the
CC
V
threshold, the controller stops the DRV pulses and
CC(OVP)
the 4−s timer starts counting. The IC re−start pulsing after
the 4−s timer has elapsed and when V ≥ V
.
CC
CC(on)
40.0
V
CC(OVP)
30.0
V
CC
1
V
CC(on)
20.0
10.0
0
V
CC(off)
40.0
30.0
20.0
10.0
0
V
2
out
800m
600m
400m
200m
0
I
3
4
out
8.00
6.00
4.00
2.00
0
OVP
1.38
3.96
6.54
9.11
11.7
time in seconds
Figure 64. Open LED Protection Chronograms
Valley Lockout
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
The NCL30083 changes valley as the input voltage
increases and as the output current set−point is varied
(thermal fold−back and step dimming). This limits the
switching frequency excursion. Once a valley is selected,
the controller stays locked in the valley until the input
voltage or the output current set−point varies significantly.
This avoids valley jumping and the inherent noise caused by
this phenomenon.
The input voltage is sensed by the VIN pin. The internal
logic selects the operating valley according to VIN pin
voltage (line range detector in Figure 65), SD pin voltage
and dimming state imposed by the Step Dimming circuit.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
www.onsemi.com
25
NCL30083
Vbulk
VIN
+
−
LLine
HLine
25−ms blanking time
2.4 V if LLine low
2.3 V if LLine high
Figure 65. Line Range Detector
VIN pin voltage for valley change
Table 5. VALLEY SELECTION
I
value at which the
I
value at which the
out
out
V
VIN
decreases
2.3 V
controller changes valley
controller changes valley
(I decreasing)
out
(I increasing)
out
0
−LL−
−HL−
5 V
100%
75%
100%
st
nd
1
2
78%
nd
rd
2
3
50%
30%
15%
6%
53%
33%
20%
8%
th
th
4
5
th
th
7
8
th
th
11
12
th
th
13
15
0%
0%
0
−LL−
2.4 V
−HL−
5 V
V
VIN
increases
VIN pin voltage for valley change
www.onsemi.com
26
NCL30083
Zero Crossing Detection Block
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
the valleys. To avoid such a situation, the NCL30083
features a Time−Out circuit that generates pulses if the
voltage on ZCD pin stays below the V
threshold
ZCD(THD)
A valley is detected when the voltage on pin 1 crosses
for 6.5 ms.
below the V
internal threshold.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
ZCD(THD)
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
V
V
ZCD
3
4
ZCD(THD)
The 3rd valley
is validated
high
low
14
12
2nd, 3rd
The 3rd valley is not detected
by the ZCD comp
The 2nd valley is detected
By the ZCD comparator
high
ZCD comp
TimeOut
low
15
16
high
low
Time−out circuit adds a pulse to
account for the missing 3rd valley
high
low
Clk
17
Figure 66. Time−out Chronograms
Line Feed−forward
Because of this time−out function, if the ZCD pin or the
auxiliary winding is shorted, the controller will continue
switching leading to improper regulation of the LED
current. Moreover during an output short circuit, the
controller will strive to maintain the constant current
operation.
Because of the propagation delays, the MOSFET is not
turned−off immediately when the current set−point is
reached. As a result, the primary peak current is higher than
expected and the output current increases. To compensate
the peak current increase brought by the propagation delay,
a positive voltage proportional to the line voltage is added
on the current sense signal. The amount of offset voltage can
In order to avoid these scenarios, a secondary timer starts
counting when the ZCD voltage is below the V
ZCD(short)
be adjusted using the R
The offset voltage is applied only during the MOSFET
on−time.
resistor as shown in Figure 67.
threshold. If this timer reaches 90 ms, the controller detects
a fault and enters the auto−recovery fault mode (controller
shuts−down and waits 4−s before re−starting switching).
LFF
This offset voltage is removed at light load during
dimming when the output current drops below 15% of the
programmed output current.
www.onsemi.com
27
NCL30083
Bulk rail
V
DD
VIN
CS
I
R
CS(offset)
LFF
R
sense
Q_drv
Offset_OK
Figure 67. Line Feed−Forward Schematic
Brown−out
shuts−down if the VIN pin voltage decreases and stays
below 0.9 V for 50 ms nominal. Exiting a brown−out
In order to protect the supply against a very low input
voltage, the NCL30083 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 1 V is applied to the VIN pin and
condition overrides the hiccup on V (V does not wait
CC
CC
to reach V ) and the IC immediately goes into startup
CC(off)
mode (I = I
).
CC
CC(start)
Vbulk
VIN
+
BO_NOK
50−ms blanking time
−
1 V if BONOK high
0.9 V if BONOK low
Figure 68. Brown−out Circuit
www.onsemi.com
28
NCL30083
160
120
80.0
40.0
0
V
Bulk
1
2
18.0
16.0
14.0
12.0
10.0
V
CC(on)
V
CC
V
CC(off)
1.10
900m
700m
500m
300m
V
V
BO(on)
BO(off)
V
pinVIN
3
8.00
6.00
4.00
2.00
0
50−ms Timer
BO_NOK low
=> Startup mode
BO_NOK
4
46.1m
138m
231m
time in seconds
323m
415m
Figure 69. Brown−Out Chronograms (Valley Fill circuit is used)
www.onsemi.com
29
NCL30083
CS Pin Short Circuit Protection
Normally, if the CS pin or the sense resistor is shorted to
ground, the Driver will not be able to turn off, leading to
potential damage of the power supply. To avoid this, the
NCL30083 features a circuit to protect the power supply
against a short circuit of the CS pin. When the MOSFET is
on, if the CS voltage stays below V after the adaptive
CS(low)
blanking timer has elapsed, the controller shuts down and
will attempt to restart on the next V hiccup.
CC
Adaptative
Blanking Time
V
VIN
Q_drv
CS
−
+
S
R
V
Q
Q
CS_short
CS(low)
UVLO
BO_NOK
Figure 70. CS Pin Short Circuit Protection Schematic
Fault Management
In this mode, the DRV pulses are stopped. The VCC
voltage decrease through the controller own consumption
OFF Mode
(I ).
CC1
The circuit turns off whenever a major condition prevents
it from operating:
For the output diode short circuit protection, the CS pin
short circuit protection, the output / aux. winding short
circuit protection and the OVP2, the controller waits 4
seconds (auto−recovery timer) and then initiates a startup
• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when V drops below
CC
V
CC(off)
and remains high until V exceeds V
.
CC
CC(on)
sequence (V ≥ V
) before re−starting switching.
CC
CC(on)
• OTP
Latch Mode
• V OVP
CC
This mode is activated by the output diode short−circuit
protection (WOD_SCP), the OTP and the Aux−SCP in
version A only.
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
In this mode, the DRV pulses are stopped and the
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
controller is latched. There are hiccups on V
The circuit un−latches when V < V
.
CC
.
CC(reset)
CC
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
www.onsemi.com
30
NCL30083
Timer has
finished
counting
V
CC
> V
CC(on)
V
CC
< V
CC(off)
or
BO_NOK ↓
OVP2 or
_OVP
BO_NOK high
or OTP
or TSD
V
CC
Stop
4−s
Timer
or CS_Short
V
CC
Disch.
BO_NOK high
or OTP
or TSD
or CS_Short
OVP2
or WOD_SCP
or Aux_SCP
or V _OVP
CC
Run
V
CC
< V
CC(off)
With states: Reset
→
→
→
→
→
Controller is reset, I = I
CC CC(start)
Controller is ON, DRV is not switching, t
Normal switching
Stop
Run
has elapsed
OTP(start)
V
CC
Disch.
No switching, I = I
, waiting for V to decrease to V
CC1 CC CC(off)
CC
4−s Timer
the auto−recovery timer is counting, V is ramping up and down between V
and V
CC(on) CC(off)
CC
Figure 71. State Diagram for B Version Faults
www.onsemi.com
31
NCL30083
Reset
Timer has
finished
counting
V
CC
> V
CC(on)
V
CC
< V
CC(off)
or
BO_NOK ↓
V
CC
< V
CC(reset)
OVP2 or
_OVP
BO_NOK high
or TSD
or CS_Short
V
4−s
Timer
CC
Stop
V
CC
Disch.
OTP
OVP2 or
V
CC
_OVP
BO_NOK high
or TSD
or CS_Short
Latch
Run
V
CC
< V
CC(off)
OTP or
WOD_SCP or
Aux_SCP
With states: Reset
→
→
→
→
→
→
Controller is reset, I = I
CC CC(start)
Controller is ON, DRV is not switching, t
Normal switching
Stop
Run
has elapsed
OTP(start)
V
CC
Disch.
No switching, I = I
, waiting for V to decrease to V
CC1 CC CC(off)
CC
4−s Timer
Latch
the auto−recovery timer is counting, V is ramping up and down between V
and V
CC
CC(on) CC(off)
Controller is latched off, V is ramping up and down between V
and V
,
CC
CC(on)
CC(off)
only V
can release the latch.
CC(reset)
Figure 72. State Diagram for A Version Faults
www.onsemi.com
32
NCL30083
PACKAGE DIMENSIONS
Micro8t
CASE 846A−02
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
D
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
H
E
E
MILLIMETERS
INCHES
NOM
−−
0.003
0.013
0.007
0.118
DIM
A
A1
b
c
D
MIN
−−
NOM
−−
MAX
MIN
−−
MAX
0.043
0.006
0.016
0.009
0.122
0.122
PIN 1 ID
1.10
0.15
0.40
0.23
3.10
3.10
e
0.05
0.25
0.13
2.90
2.90
0.08
0.002
0.010
0.005
0.114
0.114
b 8 PL
0.33
M
S
S
0.08 (0.003)
T B
A
0.18
3.00
E
3.00
0.118
e
L
H
E
0.65 BSC
0.55
4.90
0.026 BSC
0.021
0.193
0.40
4.75
0.70
5.05
0.016
0.187
0.028
0.199
SEATING
PLANE
−T−
A
0.038 (0.0015)
L
A1
c
RECOMMENDED
SOLDERING FOOTPRINT*
8X
8X
0.48
0.80
5.25
0.65
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
33
NCL30083
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
34
NCL30083
OPTIONS
Controller
Output SCP
Latched
Winding/Output Diode SCP
Over Temperature Protection
Latched
NCL30083A
NCL30083B
Latched
Auto−recovery
Auto−recovery
Auto−recovery
ORDERING INFORMATION
Device
†
Package Marking
Package Type
Shipping
NCL30083ADMR2G
AAE
Micro8
(Pb−Free, Halide−Free)
4000 / Tape & Reel
4000 / Tape & Reel
2500 / Tape & Reel
NCL30083BDMR2G
NCL30083BDR2G
AAF
Micro8
(Pb−Free, Halide−Free)
L30083B
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCL30083/D
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