NCL30085 [ONSEMI]
Quasi-Resonant Primary Side Current-Mode Controller;
| 型号： | NCL30085 |
| 厂家： | 
ONSEMI |
| 描述： | Quasi-Resonant Primary Side Current-Mode Controller |
| 文件： | 总27页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30085
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
Controller for LED Lighting
with Line Step Dimming and
Thermal Foldback
The NCL30085 is a power factor corrected flyback controller
targeting isolated and non−isolated constant current LED drivers. The
controller operates in a quasi−resonant mode to provide optimal
efficiency. Thanks to a novel control method, the device is able to
tightly regulate a constant LED current from the primary side. This
removes the need for secondary side feedback circuitry, biasing and an
optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact,
space efficient designs and supports 3 levels of log step dimming
which allows light output reduction by toggling the main AC switch
on and off to signal the controller to reduce the LED current point
down to 5% of full load.
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8
1
SOIC−8 NB
CASE 751
MARKING DIAGRAM
8
L30085x
ALYW
G
1
L30085x = Specific Device Code
x = A, B
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Features
• Quasi−resonant Peak Current−mode Control Operation
• Constant Current Control with Primary Side Feedback
• Tight LED Constant Current Regulation of 2% Typical
• Power Factor Correction
PIN CONNECTIONS
1
V
ZCD
VS
CC
DRV
GND
CS
• 3 Step Dimming (70/25/5%)
• Line Feedforward for Enhanced Regulation Accuracy
• Low Start−up Current (10 mA typ.)
COMP
SD
• Wide V Range
cc
(Top View)
• 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp
• Robust Protection Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
♦ OVP on V
CC
dimensions section on page 26 of this data sheet.
♦ Programmable Over Voltage / LED Open Circuit Protection
♦ Cycle−by−cycle Peak Current Limit
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Current Sense Short Protection
• Pb−Free, Halide−Free MSL1 Product
Typical Applications
• Integral LED Bulbs and Tubes
• LED Light Engines
• LED Drivers/Power Supplies
♦ User Programmable NTC Based Thermal Foldback
♦ Thermal Shutdown
♦ V Undervoltage Lockout
cc
♦ Brown−out Protection
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
April, 2015 − Rev. 3
NCL30085/D
NCL30085
.
Aux
.
.
NCL30085
1
8
7
6
5
2
3
4
Rsense
Figure 1. Typical Application Schematic for NCL30085
Table 1. PIN FUNCTION DESCRIPTION
Pin No
Pin Name
ZCD
Function
Pin Description
1
2
Zero Crossing Detection
Input Voltage Sensing
Connected to the auxiliary winding, this pin detects the core reset event.
VS
This pin observes the input voltage rail and protects the LED driver in case of
too low mains conditions (brown−out).
This pin also observes the input voltage rail for:
− Power Factor Correction
− Valley lockout
− Step dimming
3
4
COMP
SD
Filtering Capacitor
This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.70 mF
Thermal Foldback and
Shutdown
Connecting an NTC to this pin allows the user to program thermal current fold-
back threshold and slope. A Zener diode can also be used to pull−up the pin
and stop the controller for adjustable OVP protection.
5
6
7
8
CS
Current Sense
−
This pin monitors the primary peak current.
Controller ground pin.
GND
DRV
Driver Output
IC Supply Pin
The driver’s output to an external MOSFET
V
CC
This pin is the positive supply of the IC. The circuit starts to operate when V
CC
exceeds 18 V and turns off when V goes below 8.8 V (typical values). After
CC
start−up, the operating range is 9.4 V up to 26 V (V
minimum level).
CC(OVP)
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NCL30085
Internal Circuit Architecture
Enable
STOP
V
V
REF
DD
Over Voltage Protection
(Auto−recovery or Latched)
Aux_SCP
OFF
VCC
UVLO
Latch
Fault
Management
VCC Management
Over Temp. Protection
(Auto−recovery or Latched)
Internal
Thermal
Shutdown
VCC_max
VCC Over Voltage
Protection
SD
Thermal
Foldback
V
TF
WOD_SCP
BO_NOK
FF_mode
DRV
V
V
VS
REF
VCC
FF_mode
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
ZCD
Clamp
Circuit
Valley Selection
Frequency Foldback
Aux. Winding Short Circuit Prot.
DRV
Aux_SCP
S
V
Q
Q
REFX
CS_ok
V
VS
R
Line
feed−forward
V
REFX
V
VS
STOP
CS
Power Factor and
Constant−Current
Control
Leading
Edge
Blanking
CS_reset
Maximum
on time
Ipkmax STOP
t
on,max
COMP
Ipkmax
CS_ok
Max. Peak
Current
Limit
BO_NOK
V
VS
CS Short
VS
Protection
STEP_DIM
Brown−Out
UVLO
t
V
on,max
REFX
Dimming
control
V
REF
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
GND
V
TF
Figure 2. Internal Circuit Architecture
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NCL30085
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 30
V
CC(MAX)
CC
I
Maximum current for V pin
Internally limited
mA
CC(MAX)
CC
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
DRV(MAX)
DRV
I
−300, +500
mA
DRV(MAX)
V
Maximum voltage on low power pins (except DRV and V pins)
−0.3, 5.5 (Notes 2 and 5)
−2, +5
V
MAX
CC
I
Current range for low power pins (except DRV and V pins)
mA
MAX
CC
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
180
150
°C/W
°C
θ
J−A
T
J(MAX)
−40 to +125
−60 to +150
3.5
°C
Storage Temperature Range
°C
ESD Capability, HBM model (Note 3)
ESD Capability, MM model (Note 3)
ESD Capability, CDM model (Note 3)
kV
V
250
2
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can
be applied if the pin current stays within the −2−mA / 5−mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA
5. Recommended maximum V voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V pin recommended range.
S
S
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
V
rising
rising
falling
V
V
16.0
8.2
8
18.0
8.8
−
20.0
9.4
−
CC
CC
CC
CC(on)
Minimum Operating Voltage
CC(off)
Hysteresis V
– V
V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset
V
4
5
6
V
Over Voltage Protection Threshold
V
25.5
26.8
28.5
V
CC
CC(OVP)
VCC(off)
V
V
noise filter
t
−
−
5
−
−
ms
CC(off)
noise filter
t
20
CC(reset)
VCC(reset)
Startup current
I
−
13
58
30
75
mA
mA
CC(start)
Startup current in fault mode
I
CC(sFault)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
0.8
–
1.0
2.5
3.0
1.2
4.0
4.5
CC
CC(off)
CC1
CC2
CC3
Device Enabled/No output load on pin 7
F
= 65 kHz
sw
Device Switching (F
= 65 kHz)
C
= 470 pF, F = 65 kHz
−
SW
DRV
sw
CURRENT SENSE
Maximum Internal current limit
Leading Edge Blanking Duration for V
Line feed−forward current
V
0.95
240
35
1.00
300
40
1.05
360
45
V
ILIM
t
ns
mA
ILIM
LEB
DRV high, V = 2 V
I
FF
VS
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30085
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Propagation delay from current detection to gate
off−state
t
−
100
150
ns
ILIM
Maximum on−time
t
26
1.35
−
36
1.50
150
500
65
46
1.65
−
ms
V
on(MAX)
Threshold for immediate fault protection activation
V
CS(stop)
Leading Edge Blanking Duration for V
t
ns
mA
mV
CS(stop)
BCS
Current source for CS to GND short detection
I
400
30
600
100
CS(short)
Current sense threshold for CS to GND short de-
tection
V
CS
rising
V
CS(low)
GATE DRIVE
Drive Resistance
DRV Sink
W
R
R
−
−
13
30
−
−
SNK
DRV Source
SRC
Drive current capability
DRV Sink (Note 6)
mA
I
−
−
500
300
−
−
SNK
DRV Source (Note 6)
I
SRC
Rise Time (10% to 90%)
Fall Time (90% to 10%)
DRV Low Voltage
C
C
= 470 pF
= 470 pF
t
–
–
8
40
30
–
−
−
−
ns
ns
V
DRV
r
t
DRV
f
V
= V
+0.2 V
CC(off)
V
CC
DRV(low)
C
C
= 470 pF, R
=33 kW
DRV
DRV
DRV High Voltage
V
CC
= V
V
10
12
14
V
CC(MAX)
DRV(high)
= 470 pF, R
=33 kW
DRV
DRV
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
Lower ZCD threshold voltage
ZCD hysteresis
V
rising
V
−
35
90
55
150
−
mV
mV
mV
ns
ZCD
ZCD(rising)
V
ZCD(falling)
V
ZCD
falling
V
15
−
−
ZCD(HYS)
Propagation Delay from valley detection to DRV high
Blanking delay after on−time
Blanking Delay at light load
V
ZCD
falling
T
DEM
−
100
1.50
0.75
6.5
200
300
1.88
0.94
8.0
−
V
> 30% V
< 25% V
T
T
1.12
0.56
5.0
−
ms
REFX
REFX
REF
ZCD(blank1)
ZCD(blank2)
V
ms
REF
Timeout after last DEMAG transition
Pulling−down resistor
T
TIMO
ms
V
= V
R
kW
ZCD
ZCD(falling)
ZCD(PD)
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at T = 25°C
V
245
250
255
mV
mV
mV
mV
−
J
REF
Reference Voltage T = 25°C to 100°C
V
REF
242.5 250.0 257.5
J
Reference Voltage T = −40°C to 125°C
V
REF
240
20
−
250
50
4
260
100
−
J
Current sense lower threshold
V
CS
falling
V
CS(low)
V
control
to current setpoint division ratio
V
ratio
Error amplifier gain
V
REFX
=V
REF
(no dimming)
G
EA
40
50
60
mS
V
REFX
=25%* V
200
REF
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30085
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
CONSTANT CURRENT AND POWER FACTOR CONTROL
Test Condition
Symbol
Min
Typ
Max
Unit
Error amplifier current capability
V
=V
(no dimming)
I
EA
60
mA
mA
REFX
REF
V
=25%* V
240
REFX
REF
COMP Pin Start−up Current Source
No dimming, COMP pin
grounded
I
140
EA_STUP
LINE FEED FORWARD
V
to I
conversion ratio
K
I
18
35
80
20
40
22
45
mS
mA
mA
VS
CS(offset)
LFF
Line feed−forward current on CS pin
Offset current maximum value
DRV high, V = 2 V
VS
FF
V
VS
> 5 V
I
100
120
offset(MAX)
VALLEY LOCKOUT SECTION
Threshold for high− line range (HL) detection
Threshold for low−line range (LL) detection
Blanking time for line range detection
V
rising
falling
V
2.28
2.18
15
2.40
2.30
25
2.52
2.42
35
V
V
VS
HL
V
VS
V
LL
HL(blank)
t
ms
Valley Lockout
First step valley in High−Line.
Second step valley in High−Line.
Third step valley in High−Line.
First step valley in Low−Line.
Second step valley in Low−Line.
Third step valley in Low−Line.
V
2
3
6
1
2
5
HL100%
V
HL70%
HL25%
LL100%
V
V
V
LL70%
V
LL25%
FREQUENCY FOLDBACK
Additional dead time
V
= 25%*V
t
1.4
−
2.0
40
2.6
−
ms
ms
REFX
REF
FF1LL
Additional dead time
V
= 5%*V
t
REFX
REF
FF2HL
FAULT PROTECTION
Thermal Shutdown (Note 6)
Thermal Shutdown Hysteresis
F
SW
= 65 kHz
T
130
−
150
50
170
–
_C
_C
V
SHDN
T
SHDN(HYS)
Threshold voltage for output short circuit or aux.
winding short circuit detection
V
0.8
1.0
1.2
ZCD(short)
Short circuit detection Timer
Auto−recovery timer duration
SD pin Clamp series resistor
Clamped voltage
V
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD
ZCD(short)
t
recovery
R
1.6
kW
V
SD(clamp)
SD(clamp)
SD pin open
V
1.13
2.35
22.5
1.35
2.50
30.0
1.57
2.65
37.5
SD pin detection level for OVP
V
rising
V
OVP
V
SD
Delay before OVP or OTP confirmation (OVP and
OTP)
T
ms
SD(delay)
Reference current for direct connection of an NTC
(Note 8)
I
80
85
90
mA
OTP(REF)
Fault detection level for OTP (Note 7)
V
falling
rising
V
V
0.47
0.66
0.50
0.70
0.53
0.74
V
V
SD
OTP(off)
SD pin level for operation recovery after an OTP
detection
V
SD
OTP(on)
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30085
Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
FAULT PROTECTION
Test Condition
Symbol
Min
Typ
Max
Unit
OTP blanking time when circuit starts operating
(Note 8)
t
250
0.94
0.64
370
1.06
0.74
ms
V
OTP(start)
SD pin voltage at which thermal fold−back starts
V
V
R
1.00
0.69
TF(start)
TF(stop)
TF(start)
(V
REF
is decreased)
SD pin voltage at which thermal fold−back stops
V
(V
REF
is clamped to V
)
REF50
V
over I
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
T = +25°C to +125°C
10.8
7.4
5.4
7.5
40
11.7
8.1
5.9
8.1
50
12.6
8.8
6.4
8.7
60
kW
kW
kW
kW
%
TF(start)
TF(stop)
OTP(off)
OTP(on)
OTP(REF)
OTP(REF)
OTP(REF)
OTP(REF)
J
V
V
V
V
over I
over I
over I
T = +25°C to +125°C
J
R
R
R
V
TF(stop)
OTP(off)
OTP(on)
REF(50)
T = +25°C to +125°C
J
T = +25°C to +125°C
J
@ V = 600 mV (percent of V )
REF
SD pin falling, no OTP
detection
REFX
SD
BROWN−OUT
Brown−Out ON level (IC start pulsing)
V
rising
falling
V
0.95
0.85
1.00
0.90
30
1.05
0.95
V
V
S
BO(on)
Brown−Out OFF level (IC shuts down)
BO comparators delay
V
S
V
BO(off)
t
t
ms
ms
nA
s
BO(delay)
BO(blank)
Brown−Out blanking time
15
50
25
35
450
4.0
V
S
pin Pulling−down Current
V = V
S
I
BO(bias)
250
3.2
BO(on)
Step Dimming Reset Time
6. Guaranteed by Design
V
< V
t
2.4
S
BO(off)
step−reset
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
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NCL30085
TYPICAL CHARACTERISTICS
20.0
19.5
19.0
18.5
18.0
17.5
17.0
9.4
9.3
9.2
9.1
9.0
8.9
8.8
8.7
8.6
8.5
8.4
16.5
16.0
8.3
8.2
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC Start−up Threshold vs.
Temperature
Figure 4. VCC Minimum Operating Voltage vs.
Temperature
11.5
11.0
10.5
10.0
9.5
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
9.0
8.5
8.0
7.5
4.2
4.0
−50 −25
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. Hysteresis (VCC(on) − VCC(off)) vs.
Temperature
Figure 6. VCC(reset) vs. Temperature
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NCL30085
TYPICAL CHARACTERISTICS
28.0
27.8
40
35
30
25
20
15
10
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
26.0
5
0
25.8
25.6
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. VCC Over Voltage Protection
Threshold vs. Temperature
Figure 8. Start−up Current vs. Temperature
150
125
100
75
2.0
1.8
1.6
1.4
1.2
1.0
0.8
50
25
0
0.6
0.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 9. Start−up Current in Fault Mode vs.
Temperature
Figure 10. ICC1 vs. Temperature
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.6
1.4
1.2
1.5
1.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. ICC2 vs. Temperature
Figure 12. ICC3 vs. Temperature
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9
NCL30085
TYPICAL CHARACTERISTICS
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
400
380
360
340
320
300
280
260
240
220
200
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
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T , JUNCTION TEMPERATURE (°C)
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Figure 13. Maximum Internal Current Limit vs.
Temperature
Figure 14. Leading Edge Blanking vs.
Temperature
150
140
130
120
110
100
90
50
48
46
44
42
80
40
38
36
34
70
60
50
40
30
20
10
0
32
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
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T , JUNCTION TEMPERATURE (°C)
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Figure 15. Current Limit Propagation Delay vs.
Temperature
Figure 16. Maximum On−time vs. Temperature
1.60
1.58
1.56
1.54
1.52
1.50
1.48
220
210
200
190
180
170
160
150
140
130
120
1.46
1.44
1.42
1.40
1.38
110
100
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
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T , JUNCTION TEMPERATURE (°C)
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Figure 17. VCS(stop) vs. Temperature
Figure 18. Leading Edge Blanking Duration for
CS(stop) vs. Temperature
V
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10
NCL30085
TYPICAL CHARACTERISTICS
600
580
560
540
520
500
480
460
440
100
90
80
70
60
50
40
30
20
420
400
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
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T , JUNCTION TEMPERATURE (°C)
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Figure 19. ICS(short) vs. Temperature
Figure 20. VCS(low), VCS Rising vs.
Temperature
40
20
18
16
14
12
10
8
38
36
34
32
30
28
26
24
22
20
18
16
6
4
14
12
10
2
0
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 21. Sink Gate Drive Resistance vs.
Temperature
Figure 22. Source Gate Drive Resistance vs.
Temperature
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
5
0
5
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 23. Gate Drive Rise Time vs.
Temperature
Figure 24. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature
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11
NCL30085
TYPICAL CHARACTERISTICS
9.8
9.6
9.4
9.2
9.0
8.8
8.6
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
8.4
8.2
10.5
10.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
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T , JUNCTION TEMPERATURE (°C)
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Figure 25. DRV Low Voltage vs. Temperature
Figure 26. DRV High Voltage vs. Temperature
150
140
130
120
110
100
90
80
75
70
65
60
55
50
45
40
80
70
60
50
35
30
40
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 27. Upper ZCD Threshold Voltage vs.
Temperature
Figure 28. Lower ZCD Threshold vs.
Temperature
50
45
40
35
30
25
20
15
10
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−50 −25
5
0
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 29. ZCD Hysteresis vs. Temperature
Figure 30. ZCD Blanking Delay vs.
Temperature
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12
NCL30085
TYPICAL CHARACTERISTICS
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
256
255
254
253
252
251
250
249
248
247
246
6.0
5.8
−50 −25
245
244
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 31. ZCD Time−out vs. Temperature
Figure 32. Reference Voltage vs. Temperature
110
100
90
60
58
56
54
52
50
48
80
70
60
50
40
46
30
44
42
20
10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 33. Current Sense Lower Threshold
(VCS Falling) vs. Temperature
Figure 34. Error Amplifier Trans−conductance
Gain vs. Temperature
22.0
21.5
21.0
44
43
42
41
40
39
38
20.5
20.0
19.5
19.0
18.5
18.0
37
36
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 35. Feedforward VVS to ICS(offset)
Conversion Ratio vs. Temperature
Figure 36. Line Feedforward Current on CS
Pin (@ VVS = 2 V) vs. Temperature
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13
NCL30085
TYPICAL CHARACTERISTICS
120
115
110
105
100
95
2.55
2.50
2.45
2.40
2.35
90
2.30
2.25
85
80
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 37. Ioffset(MAX) vs. Temperature
Figure 38. Threshold for High−line Range
Detection vs. Temperature
40
38
36
34
32
30
28
26
24
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
22
20
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 39. Threshold for Low−line Range
Detection vs. Temperature
Figure 40. Blanking Time for Low−line Range
Detection vs. Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
115
110
105
100
95
90
85
0.85
0.80
80
75
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 41. Threshold Voltage for Output Short
Circuit Detection vs. Temperature
Figure 42. Short Circuit Detection Timer vs.
Temperature
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14
NCL30085
TYPICAL CHARACTERISTICS
5.00
4.75
4.50
4.25
4.00
3.75
3.50
2.20
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
3.25
3.00
1.10
1.00
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 43. Auto−recovery Timer Duration vs.
Temperature
Figure 44. SD Pin Clamp Series Resistor vs.
Temperature
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
1.15
1.10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 45. SD Pin Clamp Voltage vs.
Temperature
Figure 46. SD Pin OVP Threshold Voltage vs.
Temperature
38
36
34
32
30
28
26
91
90
89
88
87
86
85
84
83
82
81
24
22
80
79
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 47. TSD(delay) vs. Temperature
Figure 48. IOTP(REF) vs. Temperature
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15
NCL30085
TYPICAL CHARACTERISTICS
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
11.4
11.3
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
7.6
11.2
11.1
11.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 49. RTF(start) vs. Temperature
Figure 50. RTF(stop) vs. Temperature
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
7.8
7.7
7.6
5.5
5.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 51. ROTP(off) vs. Temperature
Figure 52. ROTP(on) vs. Temperature
55
54
53
52
51
50
49
48
47
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
46
45
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 53. Ratio VREF(50) over VREF vs.
Temperature
Figure 54. Brown−out ON Level vs.
Temperature
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16
NCL30085
TYPICAL CHARACTERISTICS
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
0.86
0.85
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
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Figure 55. Brown−out OFF Level vs.
Temperature
Figure 56. Brown−out Blanking Time vs.
Temperature
500
450
400
350
300
250
200
150
100
50
0
−50 −25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
Figure 57. VS Pin Pulling−down Current vs.
Temperature
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17
NCL30085
Application Information
The NCL30085 is a driver for power−factor corrected
second level, the controller stops operating. This
mode would only be expected to be reached if there
is a severe fault. The first and second temperature
thresholds depend on the value of the NTC
connected to the SD pin. Note, the SD pin can also
be used to shutdown the device by pulling this pin
flyback and non−isolated buck−boost and SEPIC
converters. It implements a current−mode, quasi−resonant
architecture including valley lockout and frequency
fold−back capabilities for maintaining high−efficiency
performance over a wide load range. A proprietary circuitry
ensures both accurate regulation of the output current
(without the need for a secondary−side feedback) and
near−unity power factor correction. The circuit contains a
suite of powerful protections to ensure a robust LED driver
design without the need for extra external components or
overdesign.
below the V
min level. A Zener diode can
OTP(off)
also be used to pull−up the pin and stop the
controller for adjustable OVP protection. Both
protections are latching−off (A version) or
auto−recovery (the circuit can recover operation
after 4−s delay has elapsed − B version).
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30085 optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below 2%
are typically obtained.
♦ Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
V , the MOSFET is immediately turned off for
ILIM
that switch cycle.
♦ Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller if it exceeds 150% x
V
ILIM
for 4 consecutive cycles. This feature can
protect the converter if a winding is shorted or if the
output diode is shorted or simply if the transformer
saturates. This protection is latching−off (A version)
or auto−recovery (B version).
♦ Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation. This protection
is latching−off (A version) or auto−recovery (B
version).
♦ Open LED protection: if the V pin voltage
CC
• Step dimming: The step dimming function decreases
the output current from 100% to 5% of its nominal
value in 3 discrete steps. Whenever a brown−out is
detected, the output current is decreased by reducing
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
♦ Floating or Short Pin Detection: the circuit can
detect most of these situations which helps pass
safety tests.
the reference voltage V . The step−dimming function
REF
is reset if the V pin remains below the lower
S
brown−out threshold (V ) for more than 3 s
BO(off)
typically.
Power Factor and Constant Current Control
• Main protection features:
The NCL30085 embeds an analog/digital block to control
the power factor and regulate the output current by
♦ Over Temperature Thermal Fold−back /
Shutdown/ Over Voltage Protection: the
monitoring the ZCD, V and CS pin voltages (signals ZCD,
S
NCL30085 features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. This represents a
power reduction of the LED by more than 50%. If
the temperature continues to rise after this point to a
V
and V of Figure 58). This circuitry generates the
VS
CS
current setpoint (V
current sense signal (V ) to dictate the MOSFET turning
off event when V exceeds V
/4) and compares it to the
CONTROL
CS
/4.
CONTROL
CS
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18
NCL30085
V
V
VS
ZCD STOP
REFX
PWM Latch reset
V
Power Factor and
Constant−Current
Control
CS
COMP
C1
Figure 58. Power Factor and Constant−Current Control
As illustrated in Figure 58, the V pin provides the
• The COMP pin is grounded when the circuit is off. The
S
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half−line period, it is equal to the
average COMP voltage needs to exceed the V pin
S
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
output current reference (V
). This averaging process is
REFX
made by an internal Operational Trans−conductance
Amplifier (OTA) and the capacitor connected to the COMP
pin (C1 of Figure 58). Typical COMP capacitance is 1 mF
and should not be less than 470 nF to ensure stability. The
COMP ripple does not affect the power factor performance
as the circuit digitally eliminates it when generating the
current setpoint.
If the V pin properly conveys the sinusoidal shape, power
S
• Whatever the step−dimming state is, the output current
factor will be close to unity and the Total Harmonic
Distortion (THD) will be low. In any case, the output current
will be well regulated following the equation below:
reference is set maximum (V
= V ) until the
REFX
REF
ZCD pin voltage reaches the 1−V V
threshold.
ZCD(short)
This prevents the circuit from detecting an output short
(AUX_SCP protection trips if the ZCD pin voltage
VREFX
2NPSRsense
(eq. 1)
Iout
+
does not exceed 1−V V
threshold within a
ZCD(short)
Where:
90−ms delay) just because dimming would make the
output voltage charge up slowly. If the system cannot
• N is the secondary to primary transformer turns
PS
start−up in one V cycle, the AUX_SCP 90−ms
N
• R
• V
V
= N /N
S P
CC
PS
blanking time is not reset and V
remains
is the current sense resistor (see Figure 1).
REFX
sense
maximum for all the necessary V cycles until the
CC
is the output current internal reference.
REFX
REFX
ZCD pin voltage reaches the 1−V V
threshold.
ZCD(short)
= V
(250 mV typically) at full load.
REF
• If V drops below the V
threshold because the
CC
CC(off)
The output current reference (V
) is 250 mV typically
REFX
circuit fails to start−up properly on the first attempt, a
new try takes place as soon as V is recharged to
(V ). In the event that step dimming is engaged, V
REF
REFX
CC
takes a lower value based on the step−dimming level (see
“step dimming” section) or if the temperature is high enough
to activate the thermal fold−back (see “protections”
section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
V . The COMP voltage is not reset at that
CC(on)
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• If the load is shorted, the circuit will operate in hiccup
mode with V oscillating between V
and
CC
CC(off)
V
CC(on)
until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30085A latches off in this case. With
the B version, the AUX_SCP protection forces the 4−s
auto−recovery delay to reduce the operation duty−ratio.
Figure 59 illustrates a start−up sequence with the output
shorted to ground, in this second case.
Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
the time to charge the V capacitor, initiate startup and
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string.
CC
To speed−up this phase, the following defines the start−up
sequence:
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19
NCL30085
VCC(on)
VCC
VCC(off)
(‧‧‧)
(‧‧‧)
time
time
AUX_SCPtrips
as t1 + t2 + t3 = tOVLD
t
(
^90 ms
)
DRV
OVLD
t1
t3
t1
t3
t2
t2
trecovery ^4 s
trecovery ^4 s
(
)
(
)
Figure 59. Start−up Sequence in a Load Short−circuit Situation (auto−recovery version)
Step Dimming
is selected by V
. This avoids long startup time while
REFX
The step dimming function decreases the output current
from 100% to 5% of its nominal value in 3 discrete steps.
The table below shows the different steps value and the
corresponding reference voltage value. Each time a
brown−out is detected, the output current is decreased by
dimming at low output current value.
decreasing the reference voltage V
A counter is incremented by the BO_NOK (brown−out
not OK) signal and selects one of the four corresponding
.
REF
VCC
reference thresholds: V , V
V
, V
. After
REF REF70, REF25
REF5
counting up to 4, the counter is reset.
C1
C2
Table 4. DIMMING STEPS
Dimming Step
Iout
Figure 60. Split VCC Supply
ON
1
100%
70%
25%
5%
The step−dimming function is reset if the V pin is
S
2
maintained below the V
brown−out threshold for the
BO(off)
3
T
time. T
is 3 s typically. In other words, any
step_reset
step_reset
brown−out event that is longer than T
controller to re−start at 100% current setting.
, leads the
step_reset
Note:
The step dimming state is memorized until V crosses
CC
Zero Crossing Detection Block
V
or V is below V
for 3 s (typical).
CC(reset)
VS
BO(off)
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold. At startup or in case of extremely
damped free oscillations, the ZCD comparator may not be
able to detect the valleys. To avoid such a situation, the
NCL30085 features a time−out circuit that generates pulses
if the voltage on ZCD pin stays below the 55−mV threshold
for 6.5 ms. The time−out also acts as a substitute clock for the
valley detection and simulates a missing valley in case the
free oscillations are too damped.
The circuit consumption is optimized (in particular, it
equals I when V is lower than V ) so that the
CC(fault)
CC
CC(off)
V
CC
voltage does not drop too fast for the step dimming
brown−out event.
The power supply designer should use a split V circuit
CC
as shown in Figure 60 where a small capacitor C is used for
1
a fast start−up while a larger C capacitance provides the
2
necessary storage capability for step dimming. During step
dimming, at startup, the controller generates the first DRV
pulses after 1 time−out pulse even if a higher valley number
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20
NCL30085
t
ZCD(blank1)
t
ZCD(blank)
FF_mode
t
ZCD(blank2)
ZCD
+
−
V
ZCD(TH)
Clock
Time−Out
+
−
+
−
V
ZCD(short)
S
R
Q
Q
Aux_SCP
90−ms Timer
4−s Timer (auto−recovery version)
Vcc<Vcc(reset) (latching−off version)
Figure 61. Zero Current Detection Block
If the ZCD pin or the auxiliary winding happen to be
shorted, the time−out function would normally make the
controller keep switching and hence lead to improper LED
current value. The “AUX_SCP” protection prevents such a
stressful operation: a secondary timer starts counting that is
• After the appropriate number of “clock” pulses in
valley lockout or frequency foldback mode (dimming
case)
For an optimal operation, the maximum ZCD level
should be maintained below 5 V to stay safely below the
built in clamping voltage of the pin.
only reset when the ZCD voltage exceeds the V
ZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no
ZCD voltage pulse having exceeded V for this time
ZCD(short)
Line Range Detection and Valley Lockout
period), the controller detects a fault and stops operation for
4 seconds (B version) or latches off (A version).
The “clock” shown in Figure 61 is used by the “valley
selection frequency foldback” circuitry of the block diagram
(Figure 2), to generate the next DRV pulse (if no fault
prevents it):
As sketched in Figure 62, this circuit detects the low−line
range if the V pin remains below the V threshold (2.3 V
S
LL
typical) for more than the 25−ms blanking time. High−line
is detected as soon as the V pin voltage exceeds V (2.4 V
S
HL
typical). These levels roughly correspond to 184−V rms and
192−V rms line voltages if the external resistors divider
• Immediately when the clock occurs in QR mode (heavy
applied to the V pin is designed to provide a 1−V peak value
at 80 V rms.
S
load)
Figure 62. Line Range Detection
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21
NCL30085
Quasi−square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
Table 5. VALLEY SELECTION
Load
Low Line
Valley 1 (QR)
High Line
Valley 2
100%
70%
25%
5%
Valley 2
Valley 5
Valley 3
Valley 6
Frequency foldback
Frequency foldback
A decimal counter counts the valley detected by the ZCD
logic block. In the low−line range, conduction losses are
generally dominant. Hence, only a short dead−time is
necessary to reach the MOSFET valley. In high−line
conditions, switching losses generally are the most critical.
It is thus efficient to skip a valley to lower the switching
frequency. Hence, when the current is not dimmed, the
NCL30085 optimizes the efficiency over the line range by
turning on the MOSFET at the first valley in low−line
conditions and at the second valley in the high−line case.
This is illustrated in Figure 63 that sketches the MOSFET
Drain−source voltage in both cases. In dimming cases, more
valleys can be skipped. Table 5 summarizes the valley
selection as a function of the output current.
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line
(right)
Frequency Foldback (FF)
Line Feedforward
The valley lockout function can make the circuit skip
As illustrated by Figure 64, the input voltage is sensed by
th
th
operation until the 5 valley (6 valley) is detected in
low−line case (high−line case) as obtained at 25% of the
nominal load. At the lowest step (5% of the nominal load),
the switching frequency is decreased by further adding
the V pin and converted into a current. By adding an
S
external resistor in series between the sense resistor and the
CS pin, a voltage offset proportional to the input voltage is
added to the CS signal for the MOSFET on−time to
th
th
dead−time after the 5 valley (low line) or the 6 valley
(high line) is detected. This extra dead−time is typically
40 ms.
compensate for the I
delay.
increase due to the propagation
peak
Bulk rail
vDD
VS
CS
RCS
ICS(offset)
Rsense
Q_drv
Figure 64. Line Feed−Forward Schematic
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
www.onsemi.com
22
NCL30085
Protections
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time will make possible
the current rise up to 50% or more of the nominal maximum
The circuit incorporates a large variety of protections to
make the LED driver very rugged. Among them, we can list:
value set by V
. As illustrated in Figure 65, the circuit
ILIM
Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage
uses this current overshoot to detect a winding short circuit.
The leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
remains below V
for 90 ms. In such a situation, the
ZCD(short)
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed (B version) or latches off (A
version).
exceed (V
=150% *V ), the controller enters
ILIM
CS(stop)
auto−recovery mode in version
B (4−s operation
Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
interruption between active bursts) and latches off in version
A. Similarly, this function can also protect the power supply
if the output diode is shorted or if the transformer simply
saturates.
up in a very abrupt manner. The V
comparator (current
ILIM
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
S
R
aux
DRV
Q
Q
Vdd
UVLO
TSD
VCC
CS
Vcc
management
BONOK
UVLO
LEB1
+
−
PWMreset
Ipkmax
Vcontrol / 4
latch
4−s timer
VCCreset
(grand
reset)
+
−
STOP
VILIMIT
AUX_SCP
VCC(ovp)
SD Pin OVP
(OVP2)
LEB2
+
−
WOD_SCP
4−pulse
counter
OTP
VCS(stop)
S
R
S
R
latch
OFF
Q
Q
Q
Q
AUTO − RECOVERY
(B version)
LATCHING − OFF
(A version)
VCCreset
4−s timer
Figure 65. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
VCC Over Voltage Protection
Programmable Over Voltage Protection (OVP2)
The circuit stops generating pulses if V
exceeds
Connect a Zener diode between V and the SD pin to set
CC
CC
V
and enters auto−recovery mode. This feature
a programmable V OVP (D of Figure 66). The triggering
CC(OVP)
CC Z
protects the circuit if the output LED string happens to open
or is disconnected.
level is (V +V
threshold. If this protection trips, the NCL30085A latches
off while the NCL30085B enters the auto−recovery mode.
) where V
is the 2.5−V internal
Z
OVP
OVP
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23
NCL30085
Vdd
NCL30085B
(autorecovery version)
IOTP(REF)
SD Pin OVP (OVP2) DETECTION
S
+
−
OFF
Q
VCC
Q
VOVP
TSD(delay)
DZ
R
SD
4−s Timer
OTP DETECTION
−
+
NTC
NCP30085A
(latching off version)
TOTP(start)
VOTP(off)
/ V
OTP(on)
S
Q
Latch
Q
R
VTF
Thermal
Foldback
grand reset
Rclamp
Vclamp
Figure 66. Thermal Foldback and OVP/OTP Circuitry
The SD pin is clamped to about 1.35 V (V
) through
circuit gradually reduces the LED current down 50% of its
clamp
a 1.6−kW resistor (R
). It is then necessary to inject about
initial value when V reaches V
, in accordance with
TF(stop)
clamp
SD
the characteristic of Figure 67 (Note 9).
If this thermal foldback cannot prevent the temperature
from rising (testified by V drop below V ), the circuit
VOVP * Vclamp
ǒ Ǔ
Rclamp
SD
OTP
latches off (A version) or enters auto−recovery mode
(B version) and cannot resume operation until V exceeds
that is
SD
V
to provide some temperature hysteresis (around
2.50 * 1.35
OTP(on)
ǒ
^ 700 mAǓ
1.6 k
10°C typically). The OTP thresholds nearly correspond to
the following resistances of the NTC:
• Thermal foldback starts when R
(11.7 kW, typically)
typically, to trigger the OVP protection. This current helps
ensure an accurate detection by using the Zener diode far
from its knee region.
≤ R
≤ R
NTC
TF(start)
• Thermal foldback stops when R
typically)
(8.0 kW,
NTC
TF(stop)
Programmable Over Temperature Foldback Protection
(OTP)
Connect an NTC between the SD pin and ground to detect
an over−temperature condition. In response to a high
• OTP triggers when R
• OTP is removed when R
≤ R
(5.9 kW, typically)
(8.0 kW,
NTC
OTP(off)
≥ R
OTP(on)
NTC
typically) (Note 10)
temperature (detected if V drops below V
), the
SD
TF(start)
9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if
step−dimming is not engaged or a lower one based on the step−dimming value.
10.This condition is sufficient for operation recovery of the B version. For the A version which latches off when OTP triggers, the circuit further
needs to be reset by a V drop below V
.
CC
CC(reset)
www.onsemi.com
24
NCL30085
At startup, when V
reaches V , the OTP
CC(on)
CC
comparator is blanked for at least 180 ms in order to allow the
SD pin voltage to reach its nominal value if a filtering
capacitor is connected to the SD pin. This avoids flickering
of the LED light during turn on.
Brown−Out Protection
The NCL30085 prevents operation when the line voltage
is too low for proper operation. As illustrated in Figure 68,
the circuit detects a brown−out situation if the V pin
S
remains below the V
threshold (0.9 V typical) for
BO(off)
more than the 25−ms blanking time. In this case, the
controller stops operating. Operation resumes as soon as the
V pin voltage exceeds V
(1.0 V typical) and V is
S
BO(on)
CC
higher than V
. To ease recovery, the circuit overrides
CC(on)
the V normal sequence (no need for V cycling down
Figure 67. Output Current Reduction versus SD
Pin Voltage
CC
CC
below V ). Instead, its consumption immediately
CC(off)
reduces to I
so that V
rapidly charges up to
CC(start)
CC
V . Once done, the circuit re−starts operating.
CC(on)
BONOK
VS pin
+
25−ms
blanking time
−
1.0 V / 0.9 V
Figure 68. Brown−out Circuit
Die Over Temperature (TSD)
The circuit stops operating if the junction temperature (T )
exceeds 150°C typically. The controller remains off until T
goes below nearly 100°C.
• Fault of the GND connection
J
If the GND pin is properly connected, the supply
J
current drawn from the positive terminal of the V
capacitor, flows out of the GND pin to return to the
CC
negative terminal of the V capacitor. If the GND pin
CC
Pin Connection Faults
is not connected, the circuit ESD diodes offer another
return path. The accidental non−connection of the GND
pin is monitored by detecting that one of the ESD diode
is conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
The circuit addresses most pin connection fault cases:
• CS pin short to ground
The circuit senses the CS pin impedance every time it
starts−up and after DRV pulses terminated by the 36−ms
maximum on−time. If the measured impedance does
not exceed 120 ohm typically, the circuit stops
operating. In practice, it is recommended to place a
minimum of 250−ohm in series between the CS pin and
the current sense resistor to take into account possible
parametric deviations.
More generally, incorrect pin connection situations
(open, grounded, shorted to adjacent pin) are covered by
AND9204/D.
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25
NCL30085
Fault Modes
In this mode, the DRV pulses generation is interrupted.
In the case of a latching−off fault, the circuit stops pulsing
The circuit turns off whenever a major faulty condition
prevents it from operating:
until the LED driver is unplugged and V drops below
CC
V
. At that moment, the fault is cleared and the circuit
• Severe OTP (V level below V
)
CC(reset)
OTP(off)
SD
could resume operation.
• V OVP
CC
In the auto−recovery case, the circuit cannot generate
DRV pulses for the auto−recovery 4−s delay. When this time
has elapsed, the circuit recovers operation as soon as the
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
high”
V
CC
voltage has exceeded V
.
CC(on)
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
In the B version, all these protections are auto−recovery.
The SD pin OTP and OVP, WOD_SCP and AUX_SCP are
latching off in the A version (see Table 6).
Table 6. PROTECTION MODES
AUX_SCP
WOD_SCP
Latching off
SD Pin OTP
Latching off
SD Pin OVP
Latching off
NCL30085A*
NCL30085B
Latching off
Auto−recovery
Auto−recovery
Auto−recovery
Auto−recovery
ORDERING INFORMATION
Device
Package Type
Shipping
NCL30085ADR2G*
NCL30085BDR2G
SOIC−8 (Pb−Free/Halide Free)
SOIC−8 (Pb−Free/Halide Free)
2500/Tape & Reel
2500/Tape & Reel
*Please contact local sales representative for availability
www.onsemi.com
26
NCL30085
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
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Phone: 421 33 790 2910
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For additional information, please contact your local
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NCL30085/D
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ONSEMI
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