NCL30088ADR2G [ONSEMI]
Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller;
| 型号： | NCL30088ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller |
| 文件： | 总26页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCL30088
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode
Controller for LED Lighting
with Thermal Foldback
www.onsemi.com
The NCL30088 is a power factor corrected flyback controller
targeting isolated and non−isolated constant current LED drivers. The
controller operates in a quasi−resonant mode to provide optimal
efficiency. Thanks to a novel control method, the device is able to
tightly regulate a constant LED current from the primary side. This
removes the need for secondary side feedback circuitry, biasing and an
optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact,
space efficient designs.
8
1
SOIC−8 NB
CASE 751
MARKING DIAGRAM
8
L30088x
ALYW
G
1
Features
L30088x = Specific Device Code
x = A, B, C, D
• Quasi−resonant Peak Current−mode Control Operation
• Constant Current Control with Primary Side Feedback
• Tight LED Constant Current Regulation of 2% Typical
• Power Factor Correction
• Line Feedforward for Enhanced Regulation Accuracy
• Low Start−up Current (13 mA typ.)
• Wide V Range
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb-Free Package
PIN CONNECTIONS
cc
1
V
ZCD
VS
CC
• 300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp
• Robust Protection Features
DRV
GND
CS
♦ OVP on V
CC
COMP
SD
♦ Programmable Over Voltage / LED Open Circuit Protection
♦ Cycle−by−cycle Peak Current Limit
♦ Winding Short Circuit Protection
(Top View)
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Shorted Current Sense Protection
♦ User Programmable NTC Based Thermal Foldback
♦ Thermal Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
♦ V Undervoltage Lockout
cc
♦ Brown−out Protection
• Pb−Free, Halide−Free Product
• Four Versions: NCL30088A, B, C and D (See Table 1)
Typical Applications
• Integral LED Bulbs and Tubes
• LED Light Engines
• LED Drivers/Power Supplies
• Electronic Control Gear for LED Lighting
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
April, 2015 − Rev. 4
NCL30088/D
NCL30088
.
Aux
.
.
NCL30088
1
2
3
4
8
7
6
5
Rsense
Figure 1. Typical Application Schematic in a Flyback Converter
Aux
.
.
NCL30088
1
2
3
4
8
7
6
5
Rsense
Figure 2. Typical Application Schematic in a Buck−Boost Converter
www.onsemi.com
2
NCL30088
Table 1. FOUR NCL30088 VERSIONS
Current Regulation
Reference Voltage
Part Number
Protection Mode
Recommended for (*):
(V
REF
)
Isolated converters.
Non−isolated converters with
NCL30088A
Latching−off
250 mV
250 mV
Ǹ
Vout v 2 @ (Vin,rms LL
)
Isolated converters.
Non−isolated converters with
NCL30088B
Auto−recovery
Ǹ
Vout v 2 @ (Vin,rms LL
)
Non−isolated converters with
NCL30088C
NCL30088D
Latching−off
200 mV
200 mV
Ǹ
Vout u 2 @ (Vin,rms LL
)
Non−isolated converters with
Auto−recovery
Ǹ
Vout u 2 @ (Vin,rms LL
)
*(V
)
designates the lowest line rms voltage. Refer to AND9200/D for more details.
in,rms LL
(http://www.onsemi.com/pub_link/Collateral/AND9200−D.PDF).
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
ZCD
Function
Pin Description
1
2
Zero Crossing Detection
Input Voltage Sensing
Connected to the auxiliary winding, this pin detects the core reset event.
VS
This pin observes the input voltage rail and protects the LED driver in case of
too low mains conditions (brown−out).
This pin also observes the input voltage rail for:
− Power Factor Correction
− Valley lockout
3
4
COMP
SD
Filtering Capacitor
This pin receives a filtering capacitor for power factor correction. Typical values
ranges from 1 − 4.70 mF
Thermal Foldback and
Shutdown
Connecting an NTC to this pin allows the user to program thermal current fold-
back threshold and slope. A Zener diode can also be used to pull−up the pin
and stop the controller for adjustable OVP protection.
5
6
7
8
CS
Current Sense
−
This pin monitors the primary peak current.
Controller ground pin.
GND
DRV
Driver Output
IC Supply Pin
The driver’s output to an external MOSFET
V
CC
This pin is the positive supply of the IC. The circuit starts to operate when V
CC
exceeds 18 V and turns off when V goes below 8.8 V (typical values). After
CC
start−up, the operating range is 9.4 V up to 25.5 V (V
minimum level).
CC(OVP)
www.onsemi.com
3
NCL30088
Internal Circuit Architecture
Enable
STOP
V
V
REF
DD
Over Voltage Protection
(Auto−recovery or Latched)
Aux_SCP
OFF
VCC
UVLO
Latch
Fault
Management
VCC Management
Over Temp. Protection
(Auto−recovery or Latched)
Internal
Thermal
Shutdown
VCC_max
VCC Over Voltage
Protection
SD
Thermal
Foldback
V
TF
WOD_SCP
BO_NOK
FF_mode
DRV
V
V
VS
REF
VCC
FF_mode
Zero Crossing Detection Logic
(ZCD Blanking, Time−Out, ...)
ZCD
Clamp
Circuit
Valley Selection
Frequency Foldback
Aux. Winding Short Circuit Prot.
DRV
Aux_SCP
S
V
Q
Q
TF
CS_ok
V
VS
R
Line
feed−forward
V
REF
V
VS
STOP
V
TF
CS
Power Factor and
Constant−Current
Control
Leading
Edge
Blanking
CS_reset
Maximum
on time
Ipkmax STOP
t
on,max
COMP
Ipkmax
CS_ok
Max. Peak
Current
Limit
V
VS
CS Short
VS
BO_NOK
Protection
Brown−Out
UVLO
t
on,max
Winding and
Output diode
Short Circuit
Protection
WOD_SCP
GND
Figure 3. Internal Circuit Architecture
www.onsemi.com
4
NCL30088
Table 3. MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, V pin, continuous voltage
−0.3 to 30
V
CC(MAX)
CC
I
Maximum current for V pin
Internally limited
mA
CC(MAX)
CC
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
DRV(MAX)
DRV
I
−300, +500
mA
DRV(MAX)
V
Maximum voltage on low power pins (except DRV and V pins)
−0.3, 5.5 (Notes 2 and 5)
−2, +5
V
MAX
CC
I
Current range for low power pins (except DRV and V pins)
mA
MAX
CC
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
180
150
°C/W
°C
θ
J−A
T
J(MAX)
−40 to +125
−60 to +150
3.5
°C
Storage Temperature Range
°C
ESD Capability, HBM model (Note 3)
ESD Capability, MM model (Note 3)
ESD Capability, CDM model (Note 3)
kV
V
250
2
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can
be applied if the pin current stays within the −2−mA / 5−mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds 100 mA
5. Recommended maximum V voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V pin recommended range.
S
S
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
V
Startup Threshold
V
V
rising
rising
falling
V
V
16.0
8.2
8
18.0
8.8
−
20.0
9.4
−
CC
CC
CC
CC(on)
Minimum Operating Voltage
CC(off)
Hysteresis V
– V
V
V
CC(on)
CC(off)
CC(HYS)
CC(reset)
Internal logic reset
V
4
5
6
V
Over Voltage Protection Threshold
V
25.5
26.8
28.5
V
CC
CC(OVP)
VCC(off)
V
V
noise filter
t
−
−
5
−
−
ms
CC(off)
noise filter
t
20
CC(reset)
VCC(reset)
Startup current
I
−
13
58
30
75
mA
mA
CC(start)
Startup current in fault mode
I
CC(sFault)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
0.8
–
1.0
2.6
3.0
1.2
4.0
4.5
CC
CC(off)
CC1
CC2
CC3
Device Enabled/No output load on pin 7
F
= 65 kHz
sw
Device Switching (F
= 65 kHz)
C
= 470 pF, F = 65 kHz
−
SW
DRV
sw
CURRENT SENSE
Maximum Internal current limit
Leading Edge Blanking Duration for V
6. Guaranteed by Design
V
0.95
240
1.00
300
1.05
360
V
ILIM
t
ns
ILIM
LEB
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
www.onsemi.com
5
NCL30088
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Propagation delay from current detection to gate
off−state
t
−
100
150
ns
ILIM
Maximum on−time
t
26
1.35
−
36
1.50
150
500
65
46
1.65
−
ms
V
on(MAX)
Threshold for immediate fault protection activation
V
CS(stop)
Leading Edge Blanking Duration for V
t
ns
mA
mV
CS(stop)
BCS
Current source for CS to GND short detection
I
400
30
600
100
CS(short)
Current sense threshold for CS to GND short de-
tection
V
CS
rising
V
CS(low)
GATE DRIVE
Drive Resistance
DRV Sink
W
R
R
−
−
13
30
−
−
SNK
DRV Source
SRC
Drive current capability
DRV Sink (Note 6)
mA
I
−
−
500
300
−
−
SNK
DRV Source (Note 6)
I
SRC
Rise Time (10% to 90%)
Fall Time (90% to 10%)
DRV Low Voltage
C
C
= 470 pF
= 470 pF
t
–
–
8
40
30
–
−
−
−
ns
ns
V
DRV
r
t
DRV
f
V
= V
+0.2 V
CC(off)
V
CC
DRV(low)
C
C
= 470 pF, R
=33 kW
DRV
DRV
DRV High Voltage
V
CC
= V
V
10
12
14
V
CC(MAX)
DRV(high)
= 470 pF, R
=33 kW
DRV
DRV
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
Lower ZCD threshold voltage
ZCD hysteresis
V
rising
V
−
35
15
−
90
55
150
−
mV
mV
mV
ns
ZCD
ZCD(rising)
V
ZCD(falling)
V
ZCD
falling
V
−
−
ZCD(HYS)
Propagation Delay from valley detection to DRV high
Blanking delay after on−time
V
ZCD
falling
T
100
1.50
6.5
200
300
1.88
8.0
−
DEM
ZCD(blank1)
T
1.12
5.0
−
ms
Timeout after last DEMAG transition
Pulling−down resistor
T
TIMO
ms
V
= V
R
kW
ZCD
ZCD(falling)
ZCD(PD)
CONSTANT CURRENT AND POWER FACTOR CONTROL
Reference Voltage at T = 25°C
A and B versions
C and D versions
V
245
195
250
200
255
205
mV
mV
mV
J
REF
Reference Voltage T = 25°C to 100°C
A and B versions
C and D versions
V
REF
242.5 250.0 257.5
192.5 200.0 207.5
J
Reference Voltage T = −40°C to 125°C
A and B versions
C and D versions
V
REF
240
190
250
200
260
210
J
Current sense lower threshold
V
CS
falling
V
20
−
55
4
100
−
mV
−
CS(low)
V
control
to current setpoint division ratio
V
ratio
Error amplifier gain
V
=V
=V
G
40
50
60
60
mS
mA
REFX
REF
EA
EA
Error amplifier current capability
6. Guaranteed by Design
V
REFX
I
REF
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
www.onsemi.com
6
NCL30088
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CONSTANT CURRENT AND POWER FACTOR CONTROL
COMP Pin Start−up Current Source
COMP pin grounded
I
140
mA
EA_STUP
LINE FEED FORWARD
V
to I
conversion ratio
K
I
18
35
80
20
40
22
45
mS
mA
mA
VS
CS(offset)
LFF
Line feed−forward current on CS pin
Offset current maximum value
DRV high, V = 2 V
VS
FF
V
VS
> 5 V
I
100
120
offset(MAX)
VALLEY LOCKOUT SECTION
Threshold for high− line range (HL) detection
Threshold for low−line range (LL) detection
Blanking time for line range detection
FAULT PROTECTION
V
rising
falling
V
2.28
2.18
15
2.40
2.30
25
2.52
2.42
35
V
V
VS
HL
V
VS
V
LL
t
ms
HL(blank)
Thermal Shutdown (Note 6)
F
SW
= 65 kHz
T
130
−
150
50
170
–
_C
_C
V
SHDN
Thermal Shutdown Hysteresis
T
SHDN(HYS)
Threshold voltage for output short circuit or
auxiliary winding short circuit detection
V
0.8
1.0
1.2
ZCD(short)
Short circuit detection Timer
Auto−recovery timer duration
SD pin Clamp series resistor
Clamped voltage
V
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD
ZCD(short)
t
recovery
R
1.6
kW
V
SD(clamp)
SD(clamp)
SD pin open
V
T
1.13
2.35
22.5
1.35
2.50
30.0
1.57
2.65
37.5
SD pin detection level for OVP
V
rising
V
OVP
V
SD
Delay before OVP or OTP confirmation (OVP and
OTP)
ms
SD(delay)
Reference current for direct connection of an NTC
(Note 8)
I
80
85
90
mA
OTP(REF)
Fault detection level for OTP (Note 7)
V
falling
rising
V
V
0.47
0.66
0.50
0.70
0.53
0.74
V
V
SD
OTP(off)
SD pin level for operation recovery after an OTP
detection
V
SD
OTP(on)
OTP blanking time when circuit starts operating
(Note 8)
t
250
0.94
0.64
370
1.06
0.74
ms
V
OTP(start)
SD pin voltage at which thermal fold−back starts
V
V
R
1.00
0.69
TF(start)
TF(stop)
TF(start)
(V
REF
is decreased)
SD pin voltage at which thermal fold−back stops
V
(V
REF
is clamped to V
)
REF50
V
over I
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
ratio (Note 7)
T = +25°C to +125°C
10.8
7.4
5.4
7.5
40
11.7
8.1
5.9
8.1
50
12.6
8.8
6.4
8.7
60
kW
kW
kW
kW
%
TF(start)
TF(stop)
OTP(off)
OTP(on)
OTP(REF)
OTP(REF)
OTP(REF)
OTP(REF)
J
V
V
V
V
over I
over I
over I
T = +25°C to +125°C
J
R
R
R
V
TF(stop)
OTP(off)
OTP(on)
REF(50)
T = +25°C to +125°C
J
T = +25°C to +125°C
J
@ V = 600 mV (SD pin falling no OTP
REF
SD
detection) (percent of V
)
REF
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
www.onsemi.com
7
NCL30088
Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
CS
= 0 V,
J
CC
ZCD
V
= 0 V, V = 1.5 V) For min/max values T = −40°C to +125°C, V = 12 V)
SD J CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
BROWN−OUT
Brown−Out ON level (IC start pulsing)
Brown−Out OFF level (IC shuts down)
BO comparators delay
V
rising
falling
V
V
0.95
0.85
1.00
0.90
30
1.05
0.95
V
V
S
BO(on)
V
S
BO(off)
t
t
ms
ms
nA
BO(delay)
BO(blank)
Brown−Out blanking time
15
50
25
35
V
S
pin Pulling−down Current
V = V
S
I
BO(bias)
250
450
BO(on)
6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters R
, R
, R
and R
give the resistance the
OTP(on)
TF(start) TF(stop) OTP(off)
NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
an OTP situation.
8. At startup, when V reaches V
, the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the
CC(on)
CC
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.
TYPICAL CHARACTERISTICS
20.0
9.4
9.3
9.2
9.1
9.0
8.9
8.8
8.7
8.6
19.5
19.0
18.5
18.0
17.5
17.0
8.5
8.4
16.5
16.0
8.3
8.2
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 4. VCC Start−up Threshold vs.
Temperature
Figure 5. VCC Minimum Operating Voltage vs.
Temperature
11.5
11.0
10.5
10.0
9.5
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
9.0
8.5
8.0
7.5
4.2
4.0
−50 −25
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 6. Hysteresis (VCC(on) − VCC(off)) vs.
Temperature
Figure 7. VCC(reset) vs. Temperature
www.onsemi.com
8
NCL30088
TYPICAL CHARACTERISTICS
28.0
27.8
40
35
30
25
20
15
10
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
26.0
5
0
25.8
25.6
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 8. VCC Over Voltage Protection
Threshold vs. Temperature
Figure 9. Start−up Current vs. Temperature
150
125
100
75
2.0
1.8
1.6
1.4
1.2
1.0
0.8
50
25
0
0.6
0.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 10. Start−up Current in Fault Mode vs.
Temperature
Figure 11. ICC1 vs. Temperature
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.6
1.4
1.2
1.5
1.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. ICC2 vs. Temperature
Figure 13. ICC3 vs. Temperature
www.onsemi.com
9
NCL30088
TYPICAL CHARACTERISTICS
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
400
380
360
340
320
300
280
260
240
220
200
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 14. Maximum Internal Current Limit vs.
Temperature
Figure 15. Leading Edge Blanking vs.
Temperature
150
140
130
120
110
100
90
50
48
46
44
42
80
40
38
36
34
70
60
50
40
30
20
10
0
32
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 16. Current Limit Propagation Delay vs.
Temperature
Figure 17. Maximum On−time vs. Temperature
1.60
1.58
1.56
1.54
1.52
1.50
1.48
220
210
200
190
180
170
160
150
140
130
120
1.46
1.44
1.42
1.40
1.38
110
100
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 18. VCS(stop) vs. Temperature
Figure 19. Leading Edge Blanking Duration for
CS(stop) vs. Temperature
V
www.onsemi.com
10
NCL30088
TYPICAL CHARACTERISTICS
600
580
560
540
520
500
480
460
440
100
90
80
70
60
50
40
30
20
420
400
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 20. ICS(short) vs. Temperature
Figure 21. VCS(low), VCS Rising vs.
Temperature
40
20
18
16
14
12
10
8
38
36
34
32
30
28
26
24
22
20
18
16
6
4
14
12
10
2
0
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 22. Sink Gate Drive Resistance vs.
Temperature
Figure 23. Source Gate Drive Resistance vs.
Temperature
50
45
40
35
30
25
20
15
10
50
45
40
35
30
25
20
15
10
5
0
5
0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 24. Gate Drive Rise Time vs.
Temperature
Figure 25. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature
www.onsemi.com
11
NCL30088
TYPICAL CHARACTERISTICS
9.8
9.6
9.4
9.2
9.0
8.8
8.6
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
8.4
8.2
10.5
10.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 26. DRV Low Voltage vs. Temperature
Figure 27. DRV High Voltage vs. Temperature
150
140
130
120
110
100
90
80
75
70
65
60
55
50
45
40
80
70
60
50
35
30
40
30
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 28. Upper ZCD Threshold Voltage vs.
Temperature
Figure 29. Lower ZCD Threshold vs.
Temperature
50
45
40
35
30
25
20
15
10
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
−50 −25
5
0
−50 −25
0
25
50
75
100
125 150
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 30. ZCD Hysteresis vs. Temperature
Figure 31. ZCD Blanking Delay vs.
Temperature
www.onsemi.com
12
NCL30088
TYPICAL CHARACTERISTICS
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
256
255
254
253
252
251
250
249
248
247
246
6.0
5.8
−50 −25
245
244
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 32. ZCD Time−out vs. Temperature
Figure 33. Reference Voltage vs. Temperature
(A and B versions)
110
100
90
60
58
56
54
52
50
48
80
70
60
50
40
46
30
44
42
20
10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 34. Current Sense Lower Threshold
(VCS Falling) vs. Temperature
Figure 35. Error Amplifier Trans−conductance
Gain vs. Temperature
22.0
21.5
21.0
44
43
42
41
40
39
38
20.5
20.0
19.5
19.0
18.5
18.0
37
36
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 36. Feedforward VVS to ICS(offset)
Conversion Ratio vs. Temperature
Figure 37. Line Feedforward Current on CS
Pin (@ VVS = 2 V) vs. Temperature
www.onsemi.com
13
NCL30088
TYPICAL CHARACTERISTICS
120
115
110
105
100
95
2.55
2.50
2.45
2.40
2.35
90
2.30
2.25
85
80
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 38. Ioffset(MAX) vs. Temperature
Figure 39. Threshold for High−line Range
Detection vs. Temperature
40
38
36
34
32
30
28
26
24
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
22
20
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 40. Threshold for Low−line Range
Detection vs. Temperature
Figure 41. Blanking Time for Low−line Range
Detection vs. Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
115
110
105
100
95
90
85
0.85
0.80
80
75
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 42. Threshold Voltage for Output Short
Circuit Detection vs. Temperature
Figure 43. Short Circuit Detection Timer vs.
Temperature
www.onsemi.com
14
NCL30088
TYPICAL CHARACTERISTICS
5.00
4.75
4.50
4.25
4.00
3.75
3.50
2.20
2.10
2.00
1.90
1.80
1.70
1.60
1.50
1.40
1.30
1.20
3.25
3.00
1.10
1.00
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 44. Auto−recovery Timer Duration vs.
Temperature
Figure 45. SD Pin Clamp Series Resistor vs.
Temperature
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
1.15
1.10
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 46. SD Pin Clamp Voltage vs.
Temperature
Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature
38
36
34
32
30
28
26
91
90
89
88
87
86
85
84
83
82
81
24
22
80
79
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 48. TSD(delay) vs. Temperature
Figure 49. IOTP(REF) vs. Temperature
www.onsemi.com
15
NCL30088
TYPICAL CHARACTERISTICS
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
11.4
11.3
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
7.6
11.2
11.1
11.0
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 50. RTF(start) vs. Temperature
Figure 51. RTF(stop) vs. Temperature
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
7.8
7.7
7.6
5.5
5.4
−50 −25
0
25
50
75
100
125
150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 52. ROTP(off) vs. Temperature
Figure 53. ROTP(on) vs. Temperature
55
54
53
52
51
50
49
48
47
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
46
45
0.96
0.95
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 54. Ratio VREF(50) over VREF vs.
Temperature
Figure 55. Brown−out ON Level vs.
Temperature
www.onsemi.com
16
NCL30088
TYPICAL CHARACTERISTICS
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
0.86
0.85
−50 −25
0
25
50
75
100
125 150
−50 −25
0
25
50
75
100
125 150
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 56. Brown−out OFF Level vs.
Temperature
Figure 57. Brown−out Blanking Time vs.
Temperature
500
450
400
350
300
250
200
150
100
50
0
−50 −25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
Figure 58. VS Pin Pulling−down Current vs.
Temperature
www.onsemi.com
17
NCL30088
Application Information
The NCL30088 is a driver for power−factor corrected
connected to the SD pin. Note, the SD pin can also
be used to shutdown the device by pulling this pin
flyback and non−isolated buck−boost and SEPIC
converters. Its current−mode, quasi−resonant architecture
optimizes the efficiency by turning on the MOSFET when
its drain−source voltage is minimal (valley). At high line, the
circuit delays the MOSFET turn on until the second valley
is detected to reduce the switching losses. A proprietary
circuitry ensures both accurate regulation of the output
current (without the need for a secondary−side feedback)
and near−unity power factor correction. The circuit contains
a suite of powerful protections to ensure a robust LED driver
design without the need for extra components or overdesign.
below the V
min level. A Zener diode can
OTP(off)
also be used to pull−up the pin and stop the
controller for adjustable OVP protection. Both
protections are latching−off (A and C versions) or
auto−recovery (the circuit can recover operation
after 4−s delay has elapsed − B and D versions).
♦ Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
V , the MOSFET is immediately turned off
ILIM
(cycle−by−cycle current limitation).
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30088 optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below 2%
are typically obtained.
♦ Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller if it exceeds 150% x
VILIM for 4 consecutive cycles. This feature can
protect the converter if a winding is shorted or if the
output diode is shorted or simply if the transformer
saturates. This protection is latching−off (A and C
versions) or auto−recovery (B and D versions).
♦ Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation. This protection
is latching−off (A and C versions) or auto−recovery
(B and D versions).
♦ Open LED protection: if the V pin voltage
CC
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
♦ Floating or Short Pin Detection: the circuit can
detect most of these situations which helps pass
safety tests.
• Main protection features:
♦ Over Temperature Thermal Fold−back /
Shutdown/ Over Voltage Protection: the
NCL30088 features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. This represents a
power reduction of the LED by more than 50%. If
the temperature continues to rise after this point to a
second level, the controller stops operating. This
mode would only be expected to be reached if there
is a severe fault. The first and second temperature
thresholds depend on the value of the NTC
Power Factor and Constant Current Control
The NCL30088 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, V and CS pin voltages (signals ZCD,
S
V
S
and V of Figure 59). This circuitry generates the
CS
current setpoint (V /4) and compares it to the
CONTROL
current sense signal (V ) to dictate the MOSFET turning
CS
off event when V exceeds V
/4.
CONTROL
CS
V
V
VS
ZCD STOP
REFX
PWM Latch reset
V
Power Factor and
Constant−Current
Control
CS
COMP
C1
Figure 59. Power Factor and Constant−Current Control
www.onsemi.com
18
NCL30088
Start−up Sequence
As illustrated in Figure 59, the V pin provides the
S
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half−line period, it is equal to the
the time to charge the V capacitor, begin switching and
CC
the time to charge the output capacitor until sufficient
current flows into the LED string. To speed−up this phase,
the following defines the start−up sequence:
output current reference (V
). This averaging process is
REFX
made by an internal Operational Trans−conductance
Amplifier (OTA) and the capacitor connected to the COMP
pin (C1 of Figure 59). Typical COMP capacitance is 1 mF
and should not be less than 470 nF to ensure stability. The
COMP ripple does not affect the power factor performance
as the circuit digitally eliminates it when generating the
current setpoint.
• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the V pin
S
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
If the V pin properly conveys the sinusoidal shape, power
S
factor will be close to unity and the Total Harmonic
Distortion (THD) will be low. In any case, the output current
will be well regulated following the equation below:
VREFX
2NPSRsense
(eq. 1)
Iout
+
Where:
• If V drops below the V
threshold because the
CC
CC(off)
• N is the secondary to primary transformer turns
PS
circuit fails to start−up properly on the first attempt, a
new try takes place as soon as V is recharged to
N
PS
= N /N . N is 1 in the case of non−isolated
S P PS
CC
buck−boost or SEPIC converter.
V . The COMP voltage is not reset at that
CC(on)
• R
is the current sense resistor (see Figure 1).
is the output current internal reference.
sense
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• V
REFX
V
= V
(250 mV in A and B versions and
REFX
REF
200 mV in C and D versions, typically) at full load.
• If the load is shorted, the circuit will operate in hiccup
mode with V oscillating between V
and
The output current reference (V ) is V unless the
CC
CC(off)
REFX
REF
V
until the AUX_SCP protection trips
temperature is high enough to activate the thermal fold−back
(see “protections” section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
CC(on)
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30088A and NCL30088C latch off in
this case. With the B and D versions, the AUX_SCP
protection forces the 4−s auto−recovery delay to reduce
the operation duty−ratio. Figure 60 illustrates a start−up
sequence with the output shorted to ground, in this
second case.
www.onsemi.com
19
NCL30088
VCC(on)
VCC
VCC(off)
(‧‧‧)
(‧‧‧)
time
time
AUX_SCPtrips
as t1 + t2 + t3 = tOVLD
t
(
^90 ms
)
DRV
OVLD
t1
t3
t1
t3
t2
t2
trecovery ^4 s
trecovery ^4 s
(
)
(
)
Figure 60. Start−up Sequence in a Load Short−circuit Situation (auto−recovery versions)
Zero Crossing Detection Block
The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold. At startup or in case of extremely
damped free oscillations, the ZCD comparator may not be
able to detect the valleys. To avoid such a situation, the
NCL30088 features a time−out circuit that generates pulses
if the voltage on ZCD pin stays below the 55−mV threshold
for 6.5 ms. The time−out also acts as a substitute clock for the
valley detection and simulates a missing valley in case the
free oscillations are too damped.
Figure 61. Zero Current Detection Block
www.onsemi.com
20
NCL30088
If the ZCD pin or the auxiliary winding happen to be
• After the appropriate number of “clock” pulses in
shorted, the time−out function would normally make the
controller keep switching and hence lead to improper LED
current value. The “AUX_SCP” protection prevents such a
stressful operation: a secondary timer starts counting that is
thermal foldback mode
For an optimal operation, the maximum ZCD level
should be maintained below 5 V to stay safely below the
built in clamping voltage of the pin.
only reset when the ZCD voltage exceeds the V
ZCD(short)
threshold (1 V typically). If this timer reaches 90 ms (no
ZCD voltage pulse having exceeded V for this time
Line Range Detection
As sketched in Figure 62, this circuit detects the low−line
ZCD(short)
period), the controller detects a fault and stops operation for
4 seconds (B and D versions) or latches off (A and C
versions).
range if the V pin remains below the V threshold (2.3 V
S
LL
typical) for more than the 25−ms blanking time. High−line
is detected as soon as the V pin voltage exceeds V (2.4 V
S
HL
The “clock” shown in Figure 61 is used by the “valley
selection frequency foldback” circuitry of the block diagram
(Figure 3), to generate the next DRV pulse (if no fault
prevents it):
typical). These levels roughly correspond to 184−V rms and
192−V rms line voltages if the external resistors divider
applied to the V pin is designed to provide a 1−V peak value
S
at 80 V rms.
• Immediately when the clock occurs in QR mode at low
line or valley 2 at high line (full load)
Figure 62. Line Range Detection
In the low-line range, conduction losses are generally
dominant. Adding a dead-time would further increase these
losses. Hence, only a short dead-time is necessary to reach
the MOSFET valley. In high-line conditions, switching
losses generally are the most critical. It is thus efficient to
skip one valley to lower the switching frequency. Hence,
under normal operation, the NCL30088 optimizes the
efficiency over the line range by turning on the MOSFET at
the first valley in low-line conditions and at the second
valley in the high-line case. This is illustrated by Figure 63
that sketches the MOSFET Drain-source voltage in both
cases. In the event that thermal foldback is activated,
additional valleys can be skipped as the power is reduced.
Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line (right)
Line Feedforward
As illustrated by Figure 64, the input voltage is sensed by
external resistor in series between the sense resistor and the
CS pin, a voltage offset proportional to the input voltage is
added to the CS signal for the MOSFET on−time.
the V pin and converted into a current. By adding an
S
www.onsemi.com
21
NCL30088
Bulk rail
vDD
VS
CS
RCS
ICS(offset)
Rsense
Q_drv
Figure 64. Line Feed−Forward Schematic
In Figure 64, Q_drv designates the output of the PWM latch which is high for the on−time and low otherwise.
Protections
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time will make possible
the current rise up to 50% or more of the nominal maximum
The circuit incorporates a large variety of protections to
make the LED driver very rugged. Among them, we can list:
value set by V
. As illustrated in Figure 65, the circuit
ILIM
Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage
uses this current overshoot to detect a winding short circuit.
The leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
remains below V
for 90 ms. In such a situation, the
ZCD(short)
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed (B and D versions) or
latches off (A and C versions).
exceed (V
=150% *V ), the controller enters
ILIM
CS(stop)
auto−recovery mode in B and D versions (4−s operation
interruption between active bursts) and latches off in A and
C versions. Similarly, this function can also protect the
power supply if the output diode is shorted or if the
transformer simply saturates.
Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
up in a very abrupt manner. The V
comparator (current
ILIM
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
S
R
aux
DRV
Q
Q
Vdd
UVLO
TSD
VCC
CS
Vcc
management
BONOK
UVLO
LEB1
+
−
PWMreset
Ipkmax
Vcontrol / 4
latch
4−s timer
VCCreset
(grand
reset)
+
−
STOP
VILIMIT
AUX_SCP
VCC(ovp)
SD Pin OVP
(OVP2)
LEB2
+
−
WOD_SCP
4−pulse
counter
OTP
VCS(stop)
S
R
S
R
latch
OFF
Q
Q
Q
Q
AUTO − RECOVERY
(B and D versions)
LATCHING − OFF
(A and C versions)
VCCreset
4−s timer
Figure 65. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
www.onsemi.com
22
NCL30088
VCC Over Voltage Protection
Programmable Over Voltage Protection (OVP2)
The circuit stops generating pulses if V
exceeds
Connect a Zener diode between V and the SD pin to set
CC
CC
V
and enters auto−recovery mode. This feature
a programmable V OVP (D of Figure 66). The triggering
CC(OVP)
CC Z
protects the circuit if the output LED string happens to open
or is disconnected.
level is (V +V
) where V
is the 2.5−V internal
Z
OVP
OVP
threshold. If this protection trips, the NCL30088A and
NCL30088C latch off while the NCL30088B and
NCL30088D enter the auto−recovery mode.
Vdd
NCL30088B / NCL30088D
(autorecovery versions)
IOTP(REF)
SD Pin OVP (OVP2) DETECTION
S
+
OFF
Q
Q
VCC
−
VOVP
TSD(delay)
DZ
R
SD
4−s Timer
OTP DETECTION
−
NTC
+
NCP30088A / NCL30088C
(latching off versions)
TOTP(start)
VOTP(off)
/ V
OTP(on)
S
Q
Latch
Q
R
VTF
Thermal
Foldback
grand reset
Rclamp
Vclamp
Figure 66. Thermal Foldback and OVP/OTP Circuitry
The SD pin is clamped to about 1.35 V (V
) through
circuit gradually reduces the LED current down 50% of its
clamp
a 1.6−kW resistor (R
). It is then necessary to inject about
nominal value when V reaches V
, in accordance
TF(stop)
clamp
SD
with the characteristic of Figure 67.
VOVP * Vclamp
If this thermal foldback cannot prevent the temperature
from rising (testified by V drop below V ), the circuit
ǒ Ǔ
Rclamp
SD
OTP
latches off (A and C versions) or enters auto−recovery mode
(B and D versions) and cannot resume operation until V
that is
SD
exceeds V
to provide some temperature hysteresis
2.50 * 1.35
OTP(on)
ǒ
^ 700 mAǓ
1.6 k
(around 10°C typically). The OTP thresholds nearly
correspond to the following resistances of the NTC:
• Thermal foldback starts when R
(11.7 kW, typically)
typically, to trigger the OVP protection. This current helps
ensure an accurate detection by using the Zener diode far
from its knee region.
≤ R
≤ R
NTC
TF(start)
• Thermal foldback stops when R
typically)
(8.0 kW,
NTC
TF(stop)
Programmable Over Temperature Foldback Protection
(OTP)
Connect an NTC between the SD pin and ground to detect
an over−temperature condition. In response to a high
• OTP triggers when R
≤ R
(5.9 kW, typically)
(8.0 kW,
NTC
OTP(off)
• OTP is removed when R
≥ R
OTP(on)
NTC
typically) (Note 9)
temperature (detected if V drops below V
), the
SD
TF(start)
9. This condition is sufficient for operation recovery of the B and D versions. For the A and C versions which latch off when OTP triggers, the
circuit further needs to be reset by a V drop below V
An online EXCEL −based design tool is available to aid in selecting the appropriate NTC value.
.
CC
CC(reset)
®
www.onsemi.com
23
NCL30088
At startup, when V
reaches V , the OTP
CC(on)
CC
comparator is blanked for at least 250 ms in order to allow the
SD pin voltage to reach its nominal value if a filtering
capacitor is connected to the SD pin. This avoids flickering
of the LED light during turn on.
Brown−Out Protection
The NCL30088 prevents operation when the line voltage
is too low for proper operation. As illustrated in Figure 68,
the circuit detects a brown−out situation if the V pin
S
remains below the V
threshold (0.9 V typical) for
BO(off)
more than the 25−ms blanking time. In this case, the
controller stops operating. Operation resumes as soon as the
V pin voltage exceeds V
(1.0 V typical) and V is
S
BO(on)
CC
higher than V
. To ease recovery, the circuit overrides
CC(on)
the V normal sequence (no need for V cycling down
Figure 67. Output Current Reduction versus SD
Pin Voltage
CC
CC
below V ). Instead, its consumption immediately
CC(off)
reduces to I
so that V
rapidly charges up to
CC(start)
CC
V . Once done, the circuit re−starts operating.
CC(on)
Figure 68. Brown−out Circuit
Die Over Temperature (TSD)
The circuit stops operating if the junction temperature (T )
exceeds 150°C typically. The controller remains off until T
goes below nearly 100°C.
• Fault of the GND connection
J
If the GND pin is properly connected, the supply
J
current drawn from the positive terminal of the V
capacitor, flows out of the GND pin to return to the
CC
negative terminal of the V capacitor. If the GND pin
CC
Pin Connection Faults
is not connected, the circuit ESD diodes offer another
return path. The accidental non−connection of the GND
pin is monitored by detecting that one of the ESD diode
is conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 ms, the
circuit stops generating DRV pulses.
The circuit addresses most pin connection fault cases:
• CS pin short to ground
The circuit senses the CS pin impedance every time it
starts−up and after DRV pulses terminated by the 36−ms
maximum on−time. If the measured impedance does
not exceed 120 ohm typically, the circuit stops
operating. In practice, it is recommended to place a
minimum of 250−ohm in series between the CS pin and
the current sense resistor to take into account possible
parametric deviations.
More generally, incorrect pin connection situations
(open, grounded, shorted to adjacent pin) are covered by
AND9204/D.
www.onsemi.com
24
NCL30088
Fault Modes
In the case of a latching−off fault, the circuit stops pulsing
until the LED driver is unplugged and V drops below
The circuit turns off whenever a major faulty condition
prevents it from operating:
CC
V
. At that moment, the fault is cleared and the circuit
CC(reset)
could resume operation.
• Severe OTP (V level below V
)
OTP(off)
SD
In the auto−recovery case, the circuit cannot generate
DRV pulses for the auto−recovery 4−s delay. When this time
has elapsed, the circuit recovers operation as soon as the
• V OVP
CC
• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD_SCP
V
CC
voltage has exceeded V
.
CC(on)
high”
In the B and D versions, all these protections are
• Output / Auxiliary winding Short circuit protection:
“Aux_SCP high”
• Die over temperature (TSD)
auto−recovery. The SD pin OTP and OVP, WOD_SCP and
AUX_SCP are latching off in the A and C versions (see
Table 5).
In this mode, the DRV pulses generation is interrupted.
Table 5. PROTECTION MODES
AUX_SCP
WOD_SCP
Latching off
SD Pin OTP
Latching off
SD Pin OVP
Latching off
NCL30088A*
NCL30088B
NCL30088C*
NCL30088D
Latching off
Auto−recovery
Latching off
Auto−recovery
Latching off
Auto−recovery
Latching off
Auto−recovery
Latching off
Auto−recovery
Auto−recovery
Auto−recovery
Auto−recovery
ORDERING INFORMATION
Device
Package Type
Shipping
NCL30088ADR2G*
NCL30088BDR2G
NCL30088CDR2G*
NCL30088DDR2G
SOIC−8
(Pb−Free/Halide Free)
2500 / Tape & Reel
*Please contact local sales representative for availability.
www.onsemi.com
25
NCL30088
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
1.27 BSC
0.050 BSC
−Z−
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
0.10 (0.004)
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
EXCEL is a registered trademark of Microsoft Corporation.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCL30088/D
相关型号：
©2020 ICPDF网 联系我们和版权申明