NCL30125A2_技术文档

Current-Mode Controller,

Fixed Frequency, for

Two-Switch Forward

Converter

NCL30125

The NCL30125 is a fixed−frequency current−mode controller

featuring the Dynamic Self−Supply (DSS). This function greatly

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simplifies the design of the auxiliary supply and the V capacitor by

cc

activating the internal startup current source to supply the controller

during start−up, transients, latch, stand−by etc.

With a supply range up to 35 V, the controller hosts an adjustable

switching frequency with jittering function operated in peak current

mode control. When the power on the secondary side drops drastically,

the part enters skip cycle while limiting the peak current that insures

the output voltage regulation and excellent efficiency in light load

condition.

SOIC−16

CASE 751DU

MARKING DIAGRAM

16

It features a timer−based fault detection that ensures the detection of

overload and a brown−out protection against low input voltages.

XXXXXXXXXX

AWLYWWG

Features

1

• Integrated High−side Driver

XXXXX = Specific Device Code

• Adjustable Switching Frequency Up to 300 kHz

• Peak Current−mode Control

A

WL

Y

= Assembly Location

= Wafer Lot

= Year

• Skip Mode to Maximize Performance in Light Load Conditions

• High−voltage Current Source with DSS

• Brown−out (BO) Detection

WW

G

= Work Week

= Pb−Free Package

• Internal Slope Compensation

PIN CONNECTION

• Adjustable Soft−start Duration

• Frequency Jittering

HV

Boot

16

1

2

3

4

• 15 ms Timer−based Short−circuit Protection with Auto−recovery or

Latched Operation

HB 15

• Auto−recovery or Latched OVP on V

cc

• Latched OVP/OTP Input for Improved Robustness

Fault

BO

DRV_HI

14

13

• 35−V V Operation

cc

• +0.9 A / −1.2 A Peak Source/Sink Drive Capability

• Internal Thermal Shutdown

5 FB

DRV_LO 12

• These Devices are Pb−Free and are RoHS Compliant

RT

SS

FW

GND

Vcc

CS

6

7

8

11

10

9

Typical Applications

• Power Supplies for PC Silver Boxes, Games Adapter

• Two−Switch Forward Converter

• Dc−to−Dc Application Capability

ORDERING INFORMATION

See detailed ordering, marking and shipping information in the

package dimensions section on page 34 of this data sheet.

1

Publication Order Number:

January, 2020 − Rev. 0

NCL30125/D

NCL30125

Figure 1. Two−Switch Forward Application Schematic

Vcc hiccup Latch

Autorecovery

HV

Boot

Thermal

Shutdown

TSD

Start−up

UVLO_Reset

V_dd

Start-up

Reset

POReset

UVLO

Detect

Vcc Management

Logic

DRV_HI

HB

Vcc

RT

Drivers

Vcc hiccup Latch

Autorecovery

DRV_LO

Clock Logic

Up to 1 MHz

Jittering

Main Logic

Clamp

FW Signal

GND

Fault

BO

MaxDC

LEB1 LEB2 Ramp

Fault Logic

OVP/OTP

FW

FB

Skip mode

Skip Logic

LineOVP

BO_NOK

FB Reset

BO and LineOVP Logic

Current Limiation

And Regulation Loop

Max_Ipk reset

CS

SS

TSD

OCP

SCP

Vcc Hiccup

OVP/OTP

LineOVP

BO_NOK

UVLO_Reset

CS pin Fault

Vcc(OVP)

Autorecovery, Latch or

Vcc hiccup Logic

Soft Start Ramp

generation

Autorecovery

Latch

Reset POReset

Figure 2. Simplified Block Diagram

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2

NCL30125

PIN FUNCTION DESCRIPTION

Pin No.

Pin Name

Description

1

HV

Connected to the rectified ac line, this pin powers the internal current source to deliver a

startup current.

2

3

NC

Non−connected for improved creepage

Fault

The controller enters fault mode if the voltage of this pin is pulled above or below the fault

thresholds. A precise pull up current source allows direct interface with an NTC thermistor.

Fault detection triggers a latch

4

5

6

7

8

9

BO

FB

RT

SS

FW

CS

This pin monitors the input voltage to offer a Brown−out protection

Hooking an optocoupler collector to this pin will allow regulation

A resistor connected to ground fixes the switching frequency

A capacitor connected to ground selects the soft−start duration

The driver’s output used to refresh the bootstrap capacitor during startup or skip mode

This pin monitors the primary peak current but also used to select the ramp compensation

nd

amplitude. When CS pin is brought above 0.75 V, the part detects the 2 OCP level

10

V

cc

This pin is connected to an external auxiliary voltage. An OVP comparator monitors this

pin and offers a means to stop the converter in fault conditions

11

12

13

14

15

16

GND

DRV_LO

NC

The controller ground

The driver’s output to an external low−side MOSFET gate

Non−connected for improved creepage

The driver’s output to an external high−side MOSFET gate

Connects to the half−bridge output

DRV_HI

HB

Boot

The floating V supply for the upper stage

cc

OPTIONS

Fault OTP/OVP

FW (Pin 8) in

protection (Pin 3)

normal operation

Device

OCP Protection

Latched

SCP Protection

Latched

V

cc

OVP Protection

Autorecovery

NCL30125A2

NCL30125B2

Latched

Enabled

Autorecovery

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3

NCL30125

MAXIMUM RATINGS

Rating

Power Supply voltage, V pin, continuous voltage

Symbol

Value

Unit

V

cc

−0.3 to 35

−0.3 to 5.5

cc

Maximum voltage on low power pins FB, BO, CS, RT, SS and Fault

FW Driver Output Voltage (Pin 8) (Note 3)

Low Side Driver Output Voltage (Pin 11)

High Side Driver Output Voltage (Pin 16)

High Side Offset Voltage (Pin 15)

V

FW

−0.3 to V + 0.3

V

cc

V

−0.3 to V + 0.3

V

DRV_LO

cc

V

– 0.3 to V

BOOT

+ 0.3

V

DRV_HI

HB

V

HB

V

Boot

* 20 to V

Boot

V

High Side Boot Voltage (Pin 16)

V

BOOT

*0.3 to 620

V

T = *40°C to +125°C

J

High Side Floating Supply Voltage (Pin 15 and 16)

High Voltage Pin Voltage

V

– V

*0.3 to 20.0

−0.3 to 700

163

V

boot

HB

HV

Thermal Resistance Junction−to−Air

R

°C/W

θ

J−A

2

Single layer PCB 50 mm , 2 Oz Cu Printed Circuit Copper Clad

Maximum Junction Temperature

T

150

°C

kV

J(max)

Storage Temperature Range

T

−60 to 150

STG

ESD Capability, Human Body Model – All pins except HV (Note 4)

Charged Device Model ESD capability per JEDEC JESD22−C101E

ESD

3

1

HBM

CDM

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and/or APPLICATION INFORMATION for Safe Operating parameters.

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

3. Maximum current flowing into pin 8 in high state must be limited to 10 mA.

4. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Charged Device Model tested per JEDEC standard: JESD22, Method C101E

Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, except pin 8 (FW) in high state. Maximum current flowing

into pin 8 in high state must be limited to 10 mA.

2

5. Values based on copper area of 25 mm of 2 oz copper thickness and FR4 PCB substrate.

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4

NCL30125

ELECTRICAL CHARACTERISTICS

For typical values T = 25°C, for min/max values T = −40°C to +125°C; V = 100 V, V = 12 V unless otherwise noted. (Notes 6, 7)

J

HV

CC

Parameter

Test Conditions

Symbol

Min Typ Max Unit

STARTUP SECTION

Minimum voltage for current source operation

I

= 6 mA, V = V

− 0.5 V

V

HV(min)

−

30

60

V

HV

CC

CC(on)

Current delivered by the internal HV current

source

V

CC

V

CC

V

CC

V

HV

= 0 V

I

0.2

0.5

0.8

mA

start1

start2

start3

Current delivered by the internal HV current

source

= V

– 0.5 V

8.0 11.0 14.0 mA

3.0 10.0 14.0 mA

CC(on)

Current delivered by the internal HV current

source for lower HV pin voltage

− 0.5 V, V = 35 V

HV

CC(on)

HV pin leakage current

= 600 V

I

−

1.5 10.0 mA

leak1

SUPPLY SECTION

Startup Threshold

HV current source stop threshold

V

increasing

V

15.0 16.0 17.0

9.0 10.0 11.0

V

cc

cc(on)

HV current source restart threshold

Minimum Operating Voltage

V

decreasing

V

cc

cc(min)

V

8.0

8.8

9.4

cc

cc(off)

Internal Latch / Logic Reset Level

V

−

8.55

−

cc(reset)

Hysteresis above V

mode

for fast hiccup in latch

V

0.1 0.25 0.5

cc(off)

cc(hyst)

Hysteresis below V

level for I

before Latch reset

V

0.1

0.5

−

0.4

1.0

1.8

2.8

780

740

0.7

1.5

2.2

3.3

−

V

cc(off)

cc(reset_hyst)

V

CC

to I

transition

V

cc(inhibit)

V

start1

start2

Internal IC consumption

V

=2.0 V , f =100 kHz and C = 0

I

mA

FB

CC

sw

L

CC(steady1)

CC(steady2)

=2.0 V , f =100 kHz and C = 1 nF

I

−

sw

L

Internal IC consumption in Skip cycle

= 12 V, V = V

− 50 mV

I

CC(stb)

−

FB

skip

Internal IC consumption in fault mode (after a

Autorecovery or latch mode

I

−

CC(fault)

fault when V decreasing to V

)

cc

cc(off)

Internal IC consumption before start−up

V

< V + V and FB pin un-

I

−

100 190

mA

cc

cc(reset)

cc(hyst)

CC(start1)

loaded

Internal IC consumption before start−up

V

= 9.5 V and FB pin unloaded

I

−

800 950

1.05 1.7

mA

cc

CC(start2)

< V < V and FB pin unload-

cc(on)

mA

cc(min)

cc

CC(start3)

ed

BOOTSTRAP SECTION

Startup voltage on the floating section

Cutoff voltage on the floating section

Upper driver consumption

V

8.1

7.5

−

8.5

7.9

75

9.1

8.5

130

V

Boot(on)

Minimum operating voltage

No DRV pulses

Boot(off)

I

mA

Boot(STB)

Upper driver consumption

C = 0 nF between Pins 14 & 16

L

I

−

0.19 0.35 mA

Boot1

f

sw

= 100 kHz, HB connected to GND

Upper driver consumption

C = 1 nF between Pins 14 & 16

L

I

−

1.6

2.0

mA

Boot2

f

sw

= 100 kHz, HB connected to GND

st

Minimum Internal delay from ONIPP ends to 1

DRV pulse

Note: SS ramp start with the 1 DRV

pulse

t

180 200 220

ms

boot(start)

FW OUTPUT

Delay to turn on the FW signal

Duration between the DRV falling edge

and the FW pin rising edge

t

480 550 630

120 150 185

ns

delay1

Delay to turn off the FW signal

Duration between the FW pin falling edge

and the DRV rising edge

delay2

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5

NCL30125

ELECTRICAL CHARACTERISTICS (continued)

For typical values T = 25°C, for min/max values T = −40°C to +125°C; V = 100 V, V = 12 V unless otherwise noted. (Notes 6, 7)

J

HV

CC

Parameter

Test Conditions

Symbol

Min Typ Max Unit

FW OUTPUT

Peak source current

FW high state, V

= 0 V

I

−

100

200

−

mA

FW

source(FW)

V

cc

= V + 0.2 V, C = 1 nF (Note 8)

cc(off) L

Peak sink current

FW low state, V

= V

I

sink(FW)

FW

cc

V

cc

= V + 0.2 V, C = 1 nF (Note 8)

cc(off) L

Source resistance

Sink resistance

R

−

33

11.0

−

W

V

OH(FW)

R

OL(FW)

FW(low)

High State Voltage (Low V level)

V

cc

= V

+ 0.2 V, R = 33 kΩ

FW

V

7.6

CC

CC(off)

FW high state

High State Voltage (High V level)

V

cc

= V

– 0.2 V,

V

11.0 12.7 16.0

V

CC

cc(OVP)

FW(clamp)

FW high state and unloaded

DRIVE OUTPUTS

Rise Time (10−90%)

V

from 10 to 90%

t

−

13

22

ns

DRV

r

= V

+ 0.2 V, C = 1 nF

L

cc

cc(off)

Fall Time (90−10%)

V

from 90 to 10%

t

f

DRV

= V

+ 0.2 V , C = 1 nF

L

cc

cc(off)

Source resistance

Sink resistance

R

−

2.6

2.1

0.9

−

W

A

OH

R

OL

Peak source current

DRV high state, V

= 0 V

I

source

DRV

V

cc

= V + 0.2 V, C = 1 nF (Note 8)

cc(off) L

Peak sink current

DRV low state, V

= V

I

sink

−

1.2

−

A

V

DRV

cc

V

cc

= V + 0.2 V, C = 1 nF (Note 8)

cc(off) L

High State Voltage (Low V level)

V

cc

= V

+ 0.2 V, R

= 33 kΩ

V

DRV(low)

8.8

−

CC

CC(off)

DRV

DRV high state

High State Voltage (High V level)

V

cc

= V – 0.2 V,

V

DRV(clamp)

11.0 13.5 16.0

CC

cc(OVP)

DRV_LO high state and unloaded

CURRENT COMPARATOR

Maximum Internal Current Setpoint

Short Current Protection Threshold

Leading Edge Blanking Duration

V

0.470 0.500 0.530

0.69 0.75 0.81

V

ILimit

V

CS(stop)

R

= 200 kΩ

= 100 kΩ

= 32 kΩ

t

−

300

285

200

−

ns

RT

LEB1

(Note 9)

Abnormal Overcurrent Fault Blanking Duration

R

= 200 kΩ

= 100 kΩ

= 32 kΩ

t

−

100

90

50

−

ns

RT

LEB2

for V

CS(stop)

(Note 9)

Propagation delay from V

to DRV off−state

C

= 0 nF

t

−

40

4

80

−

ILimit

DRV

delay

Number of clock cycles before fault confirmation

t

count

Pull−up Current Source on CS pin for Open de-

tection

Before start−up only

I

60

−

mA

CS

CS pin Open detection

CS pin open

V

−

0.75

−

V

CS(open)

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6

NCL30125

ELECTRICAL CHARACTERISTICS (continued)

For typical values T = 25°C, for min/max values T = −40°C to +125°C; V = 100 V, V = 12 V unless otherwise noted. (Notes 6, 7)

J

HV

CC

Parameter

Test Conditions

Symbol

Min Typ Max Unit

INTERNAL OSCILLATOR

Oscillation Frequency

R

= 200 kΩ

= 100 kΩ

= 32 kΩ

f

46

92

51

58

kHz

RT

OSC

100 108

275 300 325

Maximum allowed switching frequency for A2

and B2 versions

F

−

300

−

max

Maximum duty−cycle

R

= 100 kΩ

= 32 kΩ

D

43.0 45.0 48.0

40.8 42.5 46.0

%

RT

max

jitter

Maximum duty−cycle

Frequency jittering

In percentage of f

f

−

5

−

%

OSC

Swing frequency

f

300

Hz

swing

FEEDBACK SECTION

FB internal pull−up resistor

Equivalent ac resistor from FB to GND

Internal pull−up voltage on FB pin

R

−

11.6

10

−

kΩ

V

FB

(Note 8)

FB open

R

eq

V

4.0

−

4.3

4

FB(ref)

V

FB

to Current Setpoint Division Ratio

K

FB

INTERNAL RAMP COMPENSATION

Internal Ramp Compensation Voltage

(Note 8)

V

−

3.5

−

V

ramp

Internal Ramp Compensation resistance to CS

R

26.5

kΩ

ramp

SOFT START

Soft−start pull−up current source

Soft start completion voltage threshold

SKIP SECTION

SS pin = GND

I

4.5

1.8

5.2

2.0

6.0

2.2

mA

SS

V

SS

Skip threshold

V

−

0.3

50

−

V

skip

Skip threshold Hysteresis

BROWN−OUT (BO)

V

mV

skip(HYS)

Brown−out function is disabled below this level

V

BO(en)

80

100 120 mV

st

(Before the 1 DRV pulse only)

Pull−down Current Source on BO pin for Open

I

−

400

−

nA

V

BO(en)

detection

Brown−out level at which the controller starts

pulsing

V

increasing

decreasing

V

0.76 0.80 0.84

0.66 0.70 0.74

BO

BO(on)

BO(off)

Brown−out level at which the controller stops

pulsing

V

BO

Brown−out filter duration

t

40

−

50

−

60

50

ms

nA

V

BO

I

BO(bias)

Brown−out input bias current

V

= 2.5 V

BO

Line OVP level at which the controller stops

pulsing

increasing

V

2.6

2.9

3.2

BO

LineOVP(on)

Line OVP level at which the controller resumes

operation

V

BO

decreasing

2.3

2.6

20

2.9

V

LineOVP(off)

Blanking time for Line OVP detection

FAULT INPUT (OTP/OVP)

t

−

ms

LineOVP(blank)

Overvoltage protection threshold

Overtemperature protection threshold

V

increasing

V

2.43 2.5 2.57

0.36 0.40 0.44

V

Fault

Fault(OVP)

decreasing, T = 110 °C

Fault

J

Fault(OTP)

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7

NCL30125

ELECTRICAL CHARACTERISTICS (continued)

For typical values T = 25°C, for min/max values T = −40°C to +125°C; V = 100 V, V = 12 V unless otherwise noted. (Notes 6, 7)

J

HV

CC

Parameter

Test Conditions

Symbol

Min Typ Max Unit

FAULT INPUT (OTP/OVP)

NTC biasing current

V

= 0 V

I

40

50

60

mA

kΩ

Fault

OTP

OTP resistance threshold

External NTC resistance is going down

T = 110 °C

R

7.6

8.0

8.4

OTP

J

Blanking time for OTP input during startup

NTC biasing current during start−up only

Fault clamping voltage

t

7.3

80

1.0

1.8

−

8.0

8.7

ms

mA

V

OTP(blank)

V

= 0 V − During t

only

I

100 120

Fault

OTP(blank)

OTP(boost)

I

= 0 mA (V

= 1 mA

= open)

V

1.2

2.4

10

4

1.4

3.0

−

fault

Fault

Fault(clamp)0

Fault(clamp)1

Fault clamping voltage

V

Fault filter time

t

ms

Fault(filter)

Number of clock cycles before latch confirmation

t

−

latch(count)

(after elapsing t

)

Fault(filter)

OVERCURRENT PROTECTION (OCP)

Internal OCP timer duration

Autorecovery timer

t

12

15

1

18

ms

s

OCP

t

0.85

1.35

autorec

V

CC

OVERVOLTAGE (VCC OVP)

Over Voltage Protection on V pin

V

increasing

decreasing

V

24.0 25.9 27.0

V

CC

cc

cc(OVP)

Over Voltage Protection on V pin Hysteresis

V

−

0.8

10

−

CC

cc

cc(OVP_hyst)

Blanking before OVP on V confirmation

t

ms

CC

OVP(blank)

THERMAL SHUTDOWN (TSD)

Temperature shutdown

T increasing − (Note 8)

T

135 150 165

20

°C

J

SHDN

Temperature shutdown hysteresis

T decreasing − (Note 8)

J

T

−

SHDN(hyst)

6. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

7. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25_C.

J

A

Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.

8. Guaranteed by design.

9. The LEB duration does not include the propagation delay.

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8

NCL30125

TYPICAL CHARACTERISTICS

16.32

16.22

16.12

16.02

15.92

15.82

15.72

15.62

1.24

1.14

1.04

0.94

0.84

0.74

0.64

0.54

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

TEMPERATURE (°C)

Figure 3. V_cc(inhibit)vs. Junction Temperature

Figure 4. V_cc(on)vs. Junction Temperature

8.8

10.36

10.26

10.16

10.06

9.96

8.7

8.6

8.5

8.4

8.3

9.86

9.76

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

Figure 5. V_cc(min)vs. Junction Temperature

Figure 6. V_cc(reset)vs. Junction Temperature

9.26

9.16

9.06

8.96

8.86

8.76

8.66

1.862

1.852

1.842

1.832

1.822

1.812

1.802

1.792

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

Figure 7. V_cc(off)vs. Junction Temperature

Figure 8. I_CC(steady1)vs. Junction Temperature

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9

NCL30125

TYPICAL CHARACTERISTICS

0.224

0.219

0.214

0.209

0.204

0.199

0.194

0.189

7.99

7.94

7.89

7.84

7.79

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 10. V_Boot(off)vs. Junction Temperature

Figure 9. I_Boot1vs. Junction Temperature

8.57

8.55

8.53

8.51

8.49

8.47

8.45

8.43

8.41

8.39

8.37

192

182

172

162

152

142

132

122

112

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

Figure 11. V_Boot(off)vs. Junction Temperature

Figure 12. t_delay2vs. Supply Voltage

15.2

14.7

14.2

13.7

13.2

12.7

0.509

0.507

0.505

0.503

0.501

0.499

0.497

0.495

0.493

0.491

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

Figure 13. V_DRV(clamp)vs. Junction Temperature

Figure 14. V_ILIMITvs. Junction Temperature

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10

NCL30125

TYPICAL CHARACTERISTICS

288

283

278

273

268

263

258

58

53

48

43

38

33

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE(°C)

TEMPERATURE (°C)

Figure 15. t_delayvs. Junction Temperature

Figure 16. t_LEB1@ 100 kHz vs. Junction

Temperature

107

105

103

101

99

5.242

5.232

5.222

5.212

5.202

5.192

5.182

5.172

5.162

97

95

93

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

TEMPERATURE(°C)

Figure 17. f_OSC@ 100 kW vs. Junction

Figure 18. I_SSvs. Junction Temperature

Temperature

0.728

0.723

0.718

0.713

0.708

0.703

0.698

0.693

0.308

0.303

0.298

0.293

0.288

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 19. V_skipvs. Junction Temperature

Figure 20. V_BO(off)vs. Junction Temperature

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11

NCL30125

TYPICAL CHARACTERISTICS

0.83

0.825

0.82

52

51.5

51

0.815

0.81

50.5

50

0.805

0.8

49.5

49

0.795

48.5

0.79

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 21. V_BO(on)vs. Junction Temperature

Figure 22. t_BOvs. Junction Temperature

50.75

50.25

49.75

49.25

48.75

2.526

2.516

2.506

2.496

2.486

2.476

2.466

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 24. V_Fault(OVP)vs. Junction Temperature

TEMPERATURE (°C)

Figure 23. I_OTPvs. Junction Temperature

8.115

0.403

0.402

0.401

0.4

8.095

8.075

8.055

8.035

8.015

7.995

7.975

7.955

7.935

0.399

0.398

0.397

0.396

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 25. V_Fault(OTP)vs. Junction Temperature

Figure 26. R_OTPvs. Junction Temperature

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12

NCL30125

TYPICAL CHARACTERISTICS

26.12

26.02

25.92

25.82

25.72

25.62

25.52

15.55

15.35

15.15

14.95

14.75

14.55

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 27. t_OCPvs. Junction Temperature

Figure 28. V_CC(OVP)vs. Junction Temperature

64

54

44

34

24

14

4

-50

-25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 29. V_HV(min)vs. Junction Temperature

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13

NCL30125

DEFINITIONS

General

externally adjusted with a capacitor. Soft−start is activated

when a new startup sequence occurs or during an

The NCL30125 implements a standard current mode

architecture where the switch−off event is dictated by the

peak current setpoint. This component represents the ideal

candidate for two−switch forward application with

integrated high side driver. The NCL30125 packs all the

necessary components normally needed in today modern

power supply designs, bringing several enhancements such

as a brown−out protection or HV startup current source.

auto−recovery hiccup or BO event.

Skip Cycle Feature

When the power supply loads are decreasing to a low

level, the duty cycle also decreases to the minimum value the

controller can offer. If the output loads disappear, the

converter runs at the minimum duty cycle fixed by the

leading edge blanking duration and propagation delay. It

often delivers too much energy to the secondary side and it

trips the voltage supervisor. To avoid this problem, when the

FB pin drops below the internal skip threshold, zero duty

cycle is imposed.

Current−mode Operation with Internal Ramp

Compensation

Implementing peak current mode control operating at

fixed switching frequency, the NCL30125 offers an internal

ramp compensation signal that can easily by summed up to

the sensed current. The controller can thus prevents the

appearance of sub−harmonic oscillations

Fault Input

The NCL30125 includes a dedicated fault input

accessible via the Fault pin. It can be used to sense an

overvoltage condition on the adapter and latch off the

controller by pulling up the pin above the upper fault

Adjustable Switching Frequency

A resistor to ground precisely sets the switching

frequency between 50 kHz and a maximum of 300 kHz.

threshold, V

, typically 2.5 V. The controller is also

Fault(OVP)

disabled if the Fault pin voltage, V

, is pulled below the

Fault

Internal Brown−Out Protection

lower fault threshold, V

, typically 0.4 V. The lower

Fault(OTP)

A portion of the input mains (or the rectified bulk rail) is

brought to the BO pin via a resistive network. When the

voltage on this pin is too low, the part stops pulsing. No

re−start attempt is made until the controller senses that the

voltage is back within its normal range. When the

brown−out comparator senses the voltage is acceptable, it

sends a general reset to the controller (latched states are

released) and authorizes re−start. Please note that a re−start

threshold is normally used for detecting an overtemperature

fault (by the means of an NTC).

OVP Protection on V_cc

It is sometimes interesting to implement a circuit

protection by sensing the V level. This is what this

cc

controller does by monitoring its V pin. When the voltage

cc

on this pin exceeds V

threshold, the pulses are

cc(OVP)

is always synchronized with a V

transition event for a

immediately stopped and the part enters in autorecovery

mode.

cc(on)

clean start−up sequence. If V is naturally above V

cc

cc(on)

when the BO circuit recovers, re−start is immediate. An

external transistor pulling down the BO pin to ground during

operation will shut−off the controller after the end of the BO

timer.

Short−circuit/Overload protection

Short−circuit and especially overload protections are

difficult to implement when a strong leakage inductance

between auxiliary and power windings affects the

transformer (the aux winding level does not properly

collapse in presence of an output short). Here, every time the

internal 0.5 V maximum peak current limit is activated, an

error flag is asserted and a time period starts, thanks to the

OCP timer. When the fault is validated, all pulses are

stopped and the controller enters an auto−recovery burst

mode, with a soft−start sequence at the beginning of each

cycle. An internal timer keeps the pulses off for 1 s typically

which, associated to the pulsing re−try period, ensures a

duty−cycle in fault mode less than 10%, independent from

the line level. As soon as the fault disappears, the SMPS

resumes operation. Please note that B version is

auto−recovery as we just described, A version does not and

latch off in case of a short−circuit.

High−Voltage Start−up with DSS

Low standby power results cannot be obtained with the

classical resistive start−up network. In this part, a

high−voltage current−source provides the necessary current

at start−up and turns off afterwards. The dynamic

Self−Supply (DSS) restarting the start−up current source to

supply the controller if the V voltage transiently drops

cc

EMI Jittering

An internal low−frequency modulation signal varies the

pace at which the oscillator frequency is modulated. This

helps spreading out energy in conducted noise analysis.

Since the bulk capacitor ripple brings a natural jittering at

low line, the jittering modulation is enabled only at high line.

Adjustable Soft−start

A soft−start precludes the main power switch from being

stressed upon start−up. In this controller, the soft−start is

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14

NCL30125

HV Current Source Pin

The NCL30125 HV circuitry provides two features:

• Dynamic Self−Supply to maintain the V voltage

cc

above V

threshold

cc(off)

• Start−up current source to charge the V capacitor at

cc

The Figure 30 shows the typical schematic around the HV

pin. The pin can also be connected to the bulk capacitor.

start−up

+

ac

N

EMI

+

Filter

L1

−

ac

D

2

1

R

2

1

1 HV

2

Boot 16

HB 15

3

4

5

Fault DRV_HI 14

BO

FB

13

12

DRV_LO

6 RT

7 SS

8 FW

GND 11

Vcc 10

CS 9

C

Vcc

+

Figure 30. Two Diodes Route the Full−wave Rectified Mains to the HV Pin.

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15

NCL30125

Start−up Sequence

The start−up time of a power supply largely depends on

the time necessary to charge the V capacitor to the

(V_cc(min)* V_cc(inhibit))C_Vcc

(eq. 2)

(eq. 3)

t_start2

+

I_start2* I_CC(start2)

cc

• Charge from V

to V

:

cc(min)

cc(on)

controller V start−up threshold (V

which is 16 V

cc

cc(on)

(V_cc(on)* V_cc(min))C_Vcc

I_start2* I_CC(start3)

typically). The NCL30125 high−voltage current−source

provides the necessary current for a prompt start−up and

t_start3

+

turns off afterwards. The delivered current (I

) is

start1

Assuming a 47−mF V capacitor is selected and replacing

cc

reduced to less than 0.5 mA when the V voltage is below

cc

I

V

, I

I

V

and

start1 start2 CC(start1) CC(start2), CC(start3), cc(inhibit)

V

(1.0 V typically). This feature reduces the die

cc(inhibit)

by their typical values, it comes:

cc(on)

stress if the V pin happens to be accidentally grounded.

cc

1.0 47 m

500 m * 100 m

(eq. 4)

When V exceeds V

a 11−mA current (I

) is

t_start1

+

+ 118 ms

+ 41 ms

+ 28 ms

cc

cc(inhibit),

start2

provided that charges the V capacitor.

cc

(10 * 1.0) 47 m

11 m * 800 m

The V charging time is then the total of the three

cc

t_start2

+

following durations:

• Charge from 0 V to V

:

(16 * 10) 47 m

11 m * 1.05 m

cc(inhibit)

_cc(inhibit)C_Vcc

I_start1* I_CC(start1)

t_start3

V

(eq. 1)

t_start1

+

t_start+ t_start1) t_start2) t_start3+ 187 ms

• Charge from V

to V

:

cc(inhibit)

cc(min)

V

cc(on)

P−PRUEBLICATION COPY

V

cc(min)

V

cc(inhibit)

V

cc

(t)

t

start1

start2

start3

Figure 31. The V_ccat Start−up is Made of Two Segments Given

the Short−circuit Protection Implemented on the HV Source

If the V capacitor is first dimensioned to supply the

a key feature since it allows keeping short start−up times

cc

controller for the traditional 5 to 50 ms until the auxiliary

winding takes over, no−load standby requirements usually

cause it to be larger. The HV start−up current source is then

with large V capacitors (the total start−up sequence

duration is often required to be less than 1 s).

cc

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16

NCL30125

Soft Start

CS pin as long as the SS pin voltage is below the FB pin

voltage. The driver latch is reset as soon as the CS pin

voltage becomes higher than the SS pin voltage divided by

4.

At start−up, in order to limit the stress on the MOSFET,

the primary peak current is limited by an internal ramp. As

illustrated by the Figure 32, the rising voltage on the SS pin

voltage divided by 4 controls the peak current sensed on the

CS

LEB1

V_DD

I_SS

Clock

S

R

DRV

Q

SS

1/4

C

SS

UVLO

Reset

Figure 32. Soft Start Simplified Schematic

The soft start ramp slope is defined by the internal current

source and the external capacitor connected to the SS pin. It

is a capacitor charged at constant current. The maximum

primary peak current is 0.5 V so the primary peak current can

x K ). The needed capacitance for defined soft start

duration is:

FB

I

_SST_SS

2.0 V

(eq. 5)

C_SS

+

be defined by the soft start block from 0 V to 2.0 V (V

Ilimit

An example is shown in Figure 33.

SS

2 V

time

Regulation

CS

V

Ilimit

0.5 V

V

min

time

NOTE:

V

min

is defined by the LEB & R

sense

Figure 33. Typical Soft start sequence

Please note that the soft start capacitor is internally

grounded after a fault detection (OCP, UVLO etc) or during

a BO event. The next restart will be started with the soft start

ramp up.

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17

NCL30125

Brown−out Circuitry

When the BO pin voltage exceeds V , the input is

BO(on)

Power supplies are always designed to operate with a

specific bulk voltage range. Operation below minimum bulk

voltage level would result in current and temperature

overstress of the converter power stage. The NCL30125

controller features a Brown−Out (BO) input in order to

precisely adjust the bulk voltage turn−on and turn−off levels.

considered sufficient. On the contrary, if V

remains

BO

below V

for 50 ms, the circuit detects a brown−out

BO(off)

situation and stops pulsing until the input level goes back to

normal and resumes the operation via a new soft start

sequence. The internal circuitry is shown in Figure 34.

LineOVP

blanking

V_Bulk

V_LineOVP(on)

Init pulse

R_BO(hi)

Clock

S

DRV

Q

S

BO

BO_NOK

Q

R

R_BO(lo)

C_BO

Reset Timer

V_BO(on)if BO_NOK = ‘1’

V_BO(off)if BO_NOK = ‘0’

BO timer

Reset

BO_dis

UVLO_Reset

1−ms filter

V_BO(en)

Figure 34. Simplified BO pin schematic

Ǹ

To ensure a clean re−start, the controller waits the next

event to initiate a new start−up sequence. This

V_turn(on)2 * V_BO(on)

Ǹ

80 2 * 0.8

R_BO(hi)

+

+ 6.2 MW

V

cc(on)

I_bridge

40 m

ensures a fully−charged V capacitor when the controller

cc

(eq. 7)

pulses again. From the above schematic, the calculation of

the resistor is straightforward. We have connected the

resistor to the bulk capacitor. Choose a bridge current

compatible with the power consumption you can accept. If

The hysteresis on the internal reference source is 100 mV

typically. The ratio of the two voltages is 1.14. With the

upper resistive network, the turn−off voltage can then easily

be derived:

we chose 40 mA, the pull−down resistor R

calculation

BO(lo)

V_turn(on)

is simple:

80

1.14

(eq. 8)

V_turn(off)

+

+ 70 V

1.14

V_BO(on)

0.8

(eq. 6)

R_BO(lo)

+

+ 20 kW

I_bridge

40 m

Now suppose we want a typical turn−on voltage V

turn(on)

of 80 V . From the two above equations, we can calculate

rms

the value of the upper resistive string:

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18

NCL30125

V

BO

V

BO(on)

BO(off)

BO timer

starts

BO timer

reset

time

BO_NOK

BO Timer

BO timer

ends

V

CC

Restarts at

next V

CC(on)

V

CC(on)

V

CC(min)

V

CC(off)

time

DRV

Figure 35. BO Event during Normal Operation

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19

NCL30125

V

BO

V

BO(on)

BO(off)

time

BO_NOK

V_CC

Initialization

Restarts at

next V

CC(on)

V

CC(on)

V

CC(min)

V

CC(off)

time

DRV

Figure 36. BO Event before Start−Up

The IC also includes over−voltage protection. If the

voltage on BO pin exceed V , the controller stops

pulsing after the 20 ms blanking time and until the voltage on

BO pin drops down under V (Figure 37).

LineOVP(on)

LineOVP(off)

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20

NCL30125

V

BO

V

LineOVP(on)

LineOVP(off)

LineOVP

blanking

V

BO(on)

LineOVP

blanking

time

V

Restarts at

next V

CC

CC(on)

V

CC(on)

V

CC(min)

V

CC(off)

time

DRV

time

Figure 37. Brown−out Input Functionality with Line OVP Function

There is the possibility to disable the BO protection if this

function is not needed. To implement this feature, the BO pin

If the BO voltage is still below V

disabled. Please note that all functions linked to the BO pin

will be disabled too.

, the BO function is

BO(en)

voltage is checked when V crosses V

threshold

cc

cc(min)

during the first start−up sequence or after a V

event.

cc(reset)

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21

NCL30125

Ramp Compensation

converters. These oscillations take place at half the

switching frequency and occur only during CCM with a

duty−cycle close or greater than 50%. To lower the current

loop gain, one usually injects between 50% and 100% of the

inductor downslope. Figure 38 depicts how internally the

ramp is generated. Please note that the ramp signal will be

disconnected from the CS pin, during the off time.

The NCL30125 includes an internal ramp compensation

signal. This is the buffered oscillator clock delivered only

during the on time. Its amplitude is around 3.5 V at the

maximum duty−cycle. Ramp compensation is a known

means used to cure sub harmonic oscillations in Continuous

Conduction Mode (CCM) operated current−mode

3.5 V

0 V

Ramp

Rramp

26.5 kW

Clock

S

R

CS

Q

LEB

DRV

R

comp

R

sense

From FB

divider

Figure 38. Ramp Compensation Setup

In the NCL30125 controller, the oscillator ramp features

a 3.5 V swing reached at a 48% duty−ratio. If the clock

operates at a 100 kHz frequency, then the available oscillator

slope corresponds to:

If the natural ramp compensation (δ

) is higher than

natural

the needed ramp compensation (δ

) defined by the

comp

designer, the power supply does not need additional ramp

compensation. If not, the natural compensation has to be

subtracted to the compensation brought by the controller in

order to avoid over compensation.

V_ramp(pk)

3.5

0.48 10 m

S_ramp

+

+ 729 mVńms

(eq. 9)

D_maxT_sw

d_comp(final)+ d_comp* d_natural

(eq. 13)

In a two−switch forward application, the secondary−side

downslope is seen on primary side:

The required amount of ramp compensation, δ

,

comp(final)

will help to define the needed ramp injection:

(V_out) V_f)

N_s

N_p

S_p

+

(eq. 10)

L_out

S_inj+ d_comp(final) S_p

(eq. 14)

where:

Our internal compensation being of 729 mV/ms, the

• V is output voltage level

divider ratio (Ratio) between R

resistor is:

and the internal 26.5 kW

out

comp

• V the freewheel diode forward drop

f

S_inj

• L , the secondary inductor value

out

Ratio +

(eq. 15)

S_ramp

• N /N the transformer turns ratio

s

p

The series compensation resistor value is thus:

• R

: the sense resistor on the primary side

sense

R_comp+ R_ramp.Ratio

(eq. 16)

A particularity of the forward converter is the natural

slope compensation created by the transformer magnetizing

inductance. The natural ramp is extracted from the

following equation:

A resistor of the above value will be inserted from the

sense resistor to the current sense pin. We recommend

adding a small capacitor of 100 pF, from the current sense

pin to the controller ground for an improved immunity to the

noise. Please make sure both components are located very

close to the controller.

V_bulk

L_mag

S_natural

+

(eq. 11)

The above natural ramp brings a natural compensation:

S_natural

d_natural

+

(eq. 12)

S_p

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22

NCL30125

Autorecovery Overload Protection

elapsed, the controller purposely ignores the re−start when

crosses V and waits the end of the timer. By

In case of output short−circuit or if the power supply

experiences a severe overloading situation, an internal error

flag is raised and starts a countdown timer. If the flag is

asserted longer than its programmed value (15 ms typical),

the driving pulses are stopped and 1−s autorecovery timer

V

cc

cc(on)

lowering the duty ratio in fault condition, it naturally reduces

the average input power and the rms current in the output

cable. Illustration of such principle appears in Figure 39.

The soft−start is activated upon re−start attempt. Please note

that the OCP timer is also activated by the maximum duty

starts. If V voltage is below V

, HV current source is

cc

cc(min)

activated to build up the voltage to V

. On the contrary,

cycle protection. This maxDC is affected by the t

cc(on)

delay1

if V voltage is above V

, HV current source is not

cc(min)

parameter when the FW is activated during the normal

operation. Higher the switching frequency is, lower will be

the maximum duty cycle. Please refer to the parametric

table.

cc

activated, V falls down as the auxiliary pulses are missing

cc

and the controller waits that V

is crossed to enable the

cc(min)

start−up current source. Until autorecovery timer is not

OCP

timer

End of OCP

timer

time

V

CC

V

CC(on)

V

CC(min)

CC(off)

HV Start−up is

immediatly

activated

time

DRV

Controller

stops

time

Autorecovery

Timer

t

time

restart

Figure 39. An Auto−recovery Hiccup Mode is Entered in Case a Faulty event Longer than 15 ms is

Acknowledged by the Controller

The hiccup is operating regardless of the brown−out level.

However, when the internal comparator toggles indicating

that the controller recovers from a brown−out situation (the

input line was ok, then too low and back again to normal),

the hiccup is interrupted and the controller re−starts to the

waveform: the controller is protecting the converter against

an overload. The mains suddenly went down, and then back

again at a normal level. Right at this moment, the hiccup

logic receives a reset signal and ignores the next hiccup to

immediately initiate a re−start signal.

next available V . Figure 40 displays the resulting

cc(on)

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23

NCL30125

BO_NOK

time

OCP

timer

End of OCP

timer

HV Start−up is

immediatly

activated

time

V

CC

V

CC(on)

V

CC(min)

time

DRV

time

Autorecovery

Timer

Autorecovery

timer ended by

the BO event

time

Figure 40. The BO Event Reset the Autorecovery Timer or the Latch State (Latching off OCP Protection)

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24

NCL30125

Latch Overload Protection

stopped and V hiccups between two voltage levels, given

cc

In some applications, the controller must be fully latched

in case of an output short circuit presence. In that case, you

would select a controller with an OCP latched option. When

the error flag is asserted, meaning the controller is asked to

deliver its full peak current, the controller latches off after

the elapse of fault timer – i.e. the pulses are immediately

by a V

level and added hysteresis V

. The device

cc(off)

cc(hyst)

cannot recover operation until V drops below V

brownout recovery signal is applied or Line OVP protection.

Practically, the power supply must be unplugged to be reset

or

cc

cc(reset)

(V < V

). The Figure 41 and Figure 42 depict the

cc

cc(reset)

controller behavior in these cases.

BO_NOK

time

OCP

timer

End of OCP

timer

HV Start−up is

immediatly

activated

HV Start−up is

immediatly

activated

time

V

CC

V

CC(on)

V

CC(min)

CC(hyst)

V

CC(off)

+ V

V

CC(off)

V

CC(off) − CC(reset_hyst)

time

DRV

time

Latch mode ended

by the BO event

Latch

Figure 41. BO Event Reset the Latch Mode Operation Activated by the OCP Protection

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25

NCL30125

OCP

timer

End of OCP

timer

time

V

CC

I

CC(fault)

V

CC(on)

I

CC(fault)

V

CC(min)

CC(hyst)

I

CC(start1)

I

CC(start1)

V

CC(off)

+ V

V

CC(off)

V

CC(off) − CC(reset_hyst)

PSU

unplugged

time

DRV

PSU

plugged

Latch

Latch mode ended

by the V

cc(reset)

time

Figure 42. The Latch Mode Operation, Activated by the OCP Protection, is Reset by Low Vcc Voltage

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26

NCL30125

A 2^ndOver−Current Comparator for Abnormal

Over−Current Protection

A severe fault like a winding short−circuit can cause the

switch current to increase very rapidly during the on−time.

means of a Zener diode generally in series with a small

resistor (see Figure 43).

Neglecting the resistor voltage drop, the OVP threshold is

then:

The current sense signal significantly exceeds V

. But,

ILimit

V_AUX(OVP)+ V_Z) V_Fault(OVP)

(eq. 17)

because the current sense signal is blanked by the LEB

circuit during the switch turn on, the power switch current

can become huge causing system damage.

The NCL30125 protects against this fault by adding an

additional comparator for Abnormal Over−current Fault

where V is the Zener diode voltage.

Z

The controller can also be latched off if the Fault pin

voltage, V , is pulled below the lower fault threshold,

Fault

V

, typically 0.4 V. This capability is normally used

Fault(OTP)

for detecting an overtemperature fault by means of an NTC

detection. The current sense signal is blanked with a shorter

thermistor. A pull up current source I , (typically 50 mA)

nd

OTP

LEB duration, t

, before applying it to the 2

LEB2

generates a voltage drop across the thermistor. The

resistance of the NTC thermistor decreases at higher

temperatures resulting in a lower voltage across the

thermistor. The controller detects a fault once the thermistor

Over−Current Comparator. The voltage threshold of the

comparator, V , typically 0.75 V, is set 50 % higher

CS(stop)

than V , to avoid interference with normal operation.

ILimit

Four consecutive Abnormal Over−Current faults cause the

controller to enter latch mode. The count to 4 provides noise

immunity during surge testing. The counter is reset each

time a DRV pulse occurs without activating the Fault

Overcurrent Comparator.

voltage drops below V

.

Fault(OTP)

The circuit detects an overtemperature situation when:

R_{NTC OTP}+ V_Fault(OTP)

I

(eq. 18)

Hence, the OTP protection trips when

Please note that like timer−based short−circuit protection,

some versions are latching off and others are auto−recovery.

V_Fault(OTP)

R_NTC

+

(eq. 19)

I_OTP

Fault Input

The controller bias current is reduced during power up by

disabling most of the circuit blocks including I . This

The NCL30125 includes a dedicated fault input

accessible via the Fault pin. Figure 43 shows the architecture

of the Fault input. The controller can be latching off by

pulling up the pin above the upper fault threshold,

OTP

current source is enabled once V reaches V

. A

cc(min)

cc

bypass capacitor is usually connected between the Fault and

GND pins. It will take some time for V to reach its steady

Fault

V

, typically 2.5 V. An active clamp prevents the

Fault(OVP)

state value once I

is enabled. Therefore, the lower fault

OTP

Fault pin voltage from reaching the V

if the pin is

Fault(OVP)

comparator (i.e. overtemperature detection) is ignored

during t duration. In addition, in order to speed up

left open. To reach the upper threshold, the external pull−up

current has to be higher than the pull−down capability of the

clamp (typically 1.5 mA). This OVP function is typically

OTP(blank)

this fault pin capacitor, OTP current is doubled during the

same period.

used to detect a V or auxiliary winding overvoltage by

cc

Vaux

V_DD

10 ms

Blanking

Boost

V_Fault(OVP)

V_Z

Fault

ms

10

Up Counter

Blanking

Fault

NTC

4

Clock

Reset

V_Fault(OTP)

S

Latch

Boost

OVP/OTP gone

Q

Start−up

t_OTP(blank)

R

V_CC(Reset)

BO_NOK

Figure 43. Fault Detection Schematic

As a matter of fact, the controller operates normally while

the Fault pin voltage is maintained within the upper and

lower fault thresholds. Upper and lower fault detectors have

blanking delays to prevent noise from triggering them. Both

OVP and OTP comparator outputs are validated only if its

high−state duration lasts a minimum of 10 ms. Below this

value, the event is ignored. Then, a counter ensures that

OVP/OTP events occurred for 4 successive drive clock

pulses before actually latching the part.

When the part is latched−off, the drive is immediately

turned off and V goes in endless hiccup mode. The power

cc

supply needs to be un−plugged to reset the part as a result of

a BO_NOK (BO fault condition) if Brown−Out feature is

enabled or Line OVP otherwise V

.

cc(Reset)

www.onsemi.com

27

NCL30125

Over voltage protection on V_ccpin

The NCL30125 hosts a dedicated comparator on the V

pin. When the voltage on this pin exceeds V

than 20 ms, a signal is sent to the internal latch and the

incorporates an active voltage clamp to limit the gate voltage

on the external MOSFETs. The DRV voltage clamp,

cc

for more

V

is typically 13.5 V with a maximum limit of

cc(OVP)

DRV(high)

16 V.

controller immediately stops the driving pulses while

The High Side Driver Using the Bootstrap Technique

The driver features a traditional bootstrap circuitry,

requiring an external high voltage diode with resistor in

series for the capacitor refueling path. This technique is

normally used in half−bridge application. Indeed, compared

to the two−switch forward topology, the low−side driver is

turned on in opposition compared to the high−side driver.

This operation is useful to refresh the bootstrap capacitor but

the two−switch forward topology is less friendly. To be able

to use the bootstrap technique, an external switch is added

to refresh the capacitor during startup or in skip mode. In

normal operation, the MOSFET body diode will replaced

the freewheel diode. The current capability of this additional

switch is adjusted to handle the magnetization current

during the off time. Please note that the freewheel diode

connected between the HB node and the ground is not

needed anymore. Figure 44 shows the internal architecture

of the drivers section. The device incorporates an upper

remaining in a lockout state. This OVP on V pin activates

the autorecovery mode. This technique offers a simple and

cheap means to protect the converter against optocoupler.

cc

Protecting from a failure of the current sensing

A 60 mA (typically) pull−up current source, I , pulls up

CS

the CS pin to disable the controller at start−up if the pin is left

open.

In addition, the maximum duty cycle (48% typically)

avoids that the MOSFET stays permanently ON if the switch

current cannot reach the current setpoint when for instance,

the input voltage is low or if the CS pin is grounded. In this

case, the 15−ms OCP timer is activated. If the timer elapses,

the controller enters in auto−recovery or endless hiccup

mode depending on the controller option.

Driver

The NCL30125 maximum supply voltage, V

, is

cc(max)

35 V. Typical high−voltage MOSFETs have a maximum

gate−source voltage rating of 20 V. The DRV_LO pin

UVLO circuitry that makes sure enough V voltage is

GS

available for the upper side MOSFET.

V

bulk

Boot

C_boot

Pulse

Trigger

Level

Shifter

S

R

Q

Vcc

M₁

DRV_HI

D

1

UVLO

Detect

R_boot

DRV_cmd

HB

UVLO

Detect

D_boot

Vcc

DRV_LO

M₃

M₂

GND

Bootstrap Refresh

Logic

FW

Figure 44. Internal Drive stage with Bootstrap Capacitor Refresh Switch

In order to charge the bootstrap capacitor voltage to the

threshold during the startup sequence, the purposed

timer to charge the capacitor to the V voltage and then

generate the first driver pulse with soft start as depicted in

Figure 45.

cc

V

cc

circuit will activate the external switch during t

boot(start)

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28

NCL30125

Soft Start

Fixed T

Magnetization

current

Fixed T

sw

time

Cross conduction

Delay

DRV

time

FW signal

t_boot(start)

FW is maintained

high until V_cc(on)

Bootstrap

capacitor

voltage

UVLO

time

V

CC

voltage

V

CC(on)

V

CC(off)

time

Figure 45. Bootstrap Switch Activated during Startup Sequence

In normal operation, at the nominal switching frequency,

the bootstrap capacitor voltage is charged during the

demagnetization on the primary side. When the magnetizing

For this reason, the FW pin is maintained on during the off

time. In skip cycle mode, the dead time between the core

reset and the next off time cycle where the capacitor is

refreshed again can be long, the high side driver UVLO

protection will be trigged. To avoid this unexpected

current circulates in the freewheel diode and the M

3

MOSFET body diode (both power MOSFETs M and M

1

2

are off), the HB pin drops to −V that create a path to refuel

behavior, the M switch will be turned on during the skip

f

3

the capacitor. However, when the core is fully reset, both

diodes stop conducting and the HB node turns to a

high−impedance state. The capacitor is no more refreshed.

mode to perform the bootstrap capacitor refresh during large

off time duration, the Figure 46 illustrates the controller

behavior in normal operation and during the skip mode.

www.onsemi.com

29

NCL30125

Magnetization

current

time

Cross conduction

Delay - t_delay2

Cross conduction

Delay - t_Delay1

DRV

time

FW signal

Bootstrap

capacitor

voltage

Charged by

the MOSFET

(turned ON)

UVLO

Charged by

the MOSFET

body diode

during t

Total gate

charge

MOSFET drop

delay1

time

Figure 46. Bootstrap Refresh in Normal Operation

As shown in the two previous waveforms, the bootstrap

capacitor voltage is not constant so the capacitor must be

calculated to avoid UVLO protection activation. We can

identify three phases on the bootstrap voltage. The first one,

when the MOSFETS are turned on, is due to the total gate

According to the V voltage and the high−side driver

cc

UVLO threshold, C

design margin:

can be calculated by including some

boot

V_CC)V

R_PD

^f) I_DRV

ǒ

Ǔ

Q_G) D_maxT_SW

(eq. 21)

C_boot

w

charge Q of the upper MOSFET. The energy is transferred

G

DV

from the capacitor to the MOSFET. The second phase is

during the on time duration. The negative slope is introduced

where:

− DV = V − V − UVLO − Margin

by the driver current consumption I

(internal bias) and

DRV

CC

f

also the external pull down resistor R connected between

PD

− R is the gate−source pull down resistor.

PD

the gate and the source of the upper−side transistor Q . The

DC

last portion is related to the charge sequence when the power

MOSFETS are turned off.

Please note that the maximum voltage between V

and

cc

Boot

V

is 20 V. If the bootstrap capacitor is supplied by the V

HB

The total gate charge taken from the bootstrap capacitor

during the on time is:

voltage through a diode and V > 20 V, a network has to be

inserted to protection the high−side driver.

cc

V_cc) V

R_PD

ǒ

Ǔ

Q_total+ Q_G) Q_DC+ Q_G) D_maxT_SW

^f) I_DRV

(eq. 20)

www.onsemi.com

30

NCL30125

Skip Mode

decreasing further down and starts to blank the output

pulses: the IC enters the so–called skip cycle mode, also

named controlled burst operation. Because this operation

takes place at low peak currents, you will not hear any

acoustic noise in your transformer.

The NCL30125 automatically skips switching cycles

when the output power demand drops below a given level.

This is accomplished by monitoring the FB pin. In normal

operation, pin 5 imposes a peak current accordingly to the

load value. If the load demand decreases, the internal loop

asks for lower peak current. When this setpoint reaches a

determined level, the IC prevents the current from

When the IC enters the skip cycle mode, the peak current

cannot go below V /4.

skip

Frozen peak

current

1/4

V

Skip

Skip mode

FB

50 mV

hysteresis

Figure 47. Skip Mode and Frozen Peak Current

Adjustable Switching Frequency

switching frequency range goes from 50 kHz to 300 kHz to

give more design flexibility. The curve in the Figure 48 gives

an idea of the needed resistor according to the selected

switching frequency.

The controller operates at fixed switching frequency

where the duty ratio is adjusted according to the power

demand. The switching frequency can be selected by

playing on the resistor connected on the RT pin. The

5

2×10

5

1.763×10

5

1.525×10

5

1.288×10

R

(W)

RT

5

1.05×10

4

8.125×10

5.75×10

4

3.375×10

4

1×10

4

5

5×10

7.5×10

1×10

1.25×10

1.5×10

1.75×10

2×10

2.25×10

2.5×10

2.75×10

3×10

f

(Hz)

SW

Figure 48. Switching Frequency versus RT Pin Resistance

The RT resistance can be calculated more precisely by

using the following equation:

1

10

₊ǒ _{* 120 ns}Ǔ

R_RT

10

(eq. 22)

f_SW

www.onsemi.com

31

NCL30125

Adaptive Leading Edge Blanking

With 1 ms period, the classical 300 ns LEB cannot be used.

For this reason, the NCL30125 introduced an adaptive LEB

duration according to the switching frequency set on the RT

pin. The blanking duration is 300 ns for 50−kHz frequency

and it is linearly reduced as shown in the Figure 49.

The leading edge blanking (LEB) used on CS pin at the

MOSFET turn on is present to blank the parasitic peak

voltage and avoid false primary peak current. Normally, the

time is fixed around 300 ns. However, due to the RT pin, the

switching frequency range is large, from 50 kHz to 300 kHz.

LEB1 + * 3.33.10^*13f_SW) 316.6.10^*9

(eq. 23)

−7

3.5×10

−7

3.0×10

−7

2.5×10

LEB1 (s)

−7

2.0×10

1.5×10

1×10

−7

−8

5×10

4

5

5×10

7.778×10

1.056×10

1.333×10

1.611×10

1.889×10

2.167×10

2.444×10

2.722×10

3×10

f

(Hz)

SW

Figure 49. Leading Edge Blanking (LEB1) versus Switching Frequency (f_SW

)

www.onsemi.com

32

NCL30125

The same principle is used for the LEB2. This LEB is only

and it is linearly reduced. The curve in the Figure 50 depicts

the LEB2 evolution according to the switching frequency.

nd

used for the 2 Over−Current Comparator (V ). The

CS(stop)

blanking duration LEB2 is now 100 ns for 50 kHz frequency

LEB2 + * 1.44.10^*13f_SW) 107.2.10^*9

(eq. 24)

−7

1.5×10

−7

1.375×10

−7

1.25×10

−7

1.125×10

−7

LEB2 (s)

1×10

−8

8.75×10

−8

7.5×10

−8

6.25×10

−8

5×10

4

5

5×10

7.778×10

1.056×10

1.333×10

1.611×10

1.889×10

2.167×10

2.444×10

2.722×10

3×10

f

(Hz)

SW

Figure 50. Leading Edge Blanking (LEB2) versus Switching Frequency (fsw)

Thermal Shutdown

reaching the gate via the DRV_LO pin. The current returns

to ground trough the sense resistance. At turn off, the gate

stored energy is depleted by a current that now enters the IC

DRV_LO pin and circulates to ground to flow, again, in the

sense resistance. Same path is visible on the high side driver.

All decoupling components as well as other small

low−current devices (timing capacitors, feedback

decoupling…) must be placed as close as possible to the

main control IC. Failure to respect this rule will 1) affect the

converter stability 2) degrade its susceptibility to external

events such as input surges or ESD zaps.

An internal thermal shutdown circuit monitors the

junction temperature of the IC. The controller is disabled if

the junction temperature exceeds the thermal shutdown

threshold, T

, typically 150°C. A continuous V

SHDN

cc

hiccup is initiated after a thermal shutdown fault is detected.

The controller restarts at the next V

temperature drops below below T

shutdown hysteresis, T

once the IC

by the thermal

cc(on)

SHDN

, typically 20°C.

SHDN(HYS)

The thermal shutdown is also cleared if V drops below

cc

V

or a brown−out fault is detected. A new power up

cc(reset)

sequences commences at the next V

are removed.

once all the faults

Keep noisy (from power loop or auxiliary signal) and

quiet grounds separated. The optocoupler emitter must

absolutely return to the IC ground. Do not connect it to an

intermediate point. Keep the optocoupler collector close to

its return ground and make sure these two lines are away

from noisy sources (MOSFETs, transformer). Don’t cross

noisy tracks. A small capacitor connected between FB and

GND pins will not only place the high−frequency pole you

need for compensation but it will also locally filter the noise

picked up by the feedback and return lines. As mentioned

above, the capacitor has to be placed as close as possible to

the pin controller.

cc(on)

Layout Guideline

In order to avoid noise around the controller and

unexpected behavior, we recommend to take care about the

layout. The first thing is to identify the high−current paths

and make sure the area they encompass is kept as small as

possible. When both power MOSFETs are turned on, current

is delibered by the bulk capacitor and crosses the high−side

MOSFET, the transformer primary inductance, the power

low side MOSFET and finally, the sense resistance before

returning to the bulk negative connection. Another loop will

be around the auxiliary winding to refuels the auxiliary

capacitor. Finally, the MOSFETs drives draw currents from

rd

The 3 MOSFET used to refresh the bootstrap capacitor

has to be placed as closed as possible to the high side driver

in order to avoid large noise peak current. Short connection

should be used between the HB pin and the drain and

between IC GND and source pin.

the auxiliary capacitor that enter the IC via its V pin before

cc

www.onsemi.com

33

NCL30125

VBulk

AC1 AC2

U115

1

16

15

14

HV

BOOT

HB

Cboot

Rbo_h

M3

3

4

5

6

7

8

FAULT DRV_HI

BO

12

FB

RT

SS

FW

DRV_LO

GND

VCC

11

Rbo_l

Cpole

Rrt

10

9

Vcc

Cbo

Sense

CS

Css

Rcomp

Ccs

NCL30125

0

Figure 51. Typical Schematic with Components that Should be Placed Close to the IC

ORDERING INFORMATION

†

Device

OCP

FW in Normal

Operation

Marking

Package

Shipping

NCL30125A2DR2G

NCL30125B2DR2G

Latched

Enabled

30125A2

30125B2

SOIC*16

(Pb*Free)

2500 / Tape & Reel

Autorecovery

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

34

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOIC−16 NB MISSING PINS 2 AND 13

CASE 751DU

ISSUE O

DATE 18 OCT 2013

SCALE 1:1

NOTE 5

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

D

A

2X

16

9

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE PROTRUSION SHALL BE 0.10 mm IN EXCESS OF

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS

OR GATE BURRS SHALL NOT EXCEED 0.25 mm PER SIDE. DIMEN

SIONS D AND E ARE DETERMINED AT DATUM F.

5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING

PLANE TO THE LOWEST POINT ON THE PACKAGE BODY.

0.10 C D

F

NOTE 4

E

E1

NOTE 6

A1

L

L2

C A-B D

1

8

0.20 C

SEATING

PLANE

C

MILLIMETERS

B

NOTE 5

14X b

DETAIL A

2X 4 TIPS

DIM MIN

MAX

1.75

0.25

0.49

0.25

10.00

M

0.25

A

A1

b

1.35

0.10

0.35

0.17

9.80

TOP VIEW

2X

c

0.10 C A-B

DETAIL A

D

E

6.00 BSC

0.10 C

E1

e

3.90 BSC

1.27 BSC

0.10 C

L

0.40

1.27

L2

0.203 BSC

e

END VIEW

A

SEATING

PLANE

C

GENERIC

SIDE VIEW

MARKING DIAGRAM*

RECOMMENDED

SOLDERING FOOTPRINT

16

14X

XXXXXXXXXX

AWLYWWG

1.52

1

16

1

9

XXXXX = Specific Device Code

A

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

7.00

WL

Y

WW

G

8

*This information is generic. Please refer

to device data sheet for actual part

marking. Pb−Free indicator, “G”, may

or not be present.

14X

0.60

1.27

PITCH

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON77502F

SOIC−16 NB MISSING PINS 2 AND 13

PAGE 1 OF 1

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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

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1


型号：	NCL30125A2
厂家：	ONSEMI
描述：	Current-Mode Controller, Fixed Frequency, for Two-Switch Forward Converter
文件：	总36页 (文件大小：804K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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