NCL30388A1DR2G [ONSEMI]
Power Factor Corrected LED Driver Featuring Primary Side CC / CV Control;
| 型号： | NCL30388A1DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Power Factor Corrected LED Driver Featuring Primary Side CC / CV Control |
| 文件： | 总18页 (文件大小：373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Power Factor Corrected
LED Driver Featuring
Primary Side CC / CV
Control
NCL30388
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The NCL30388 is a power factor corrected controller targeting
isolated and non−isolated constant current LED drivers. Designed to
support flyback, buck−boost and SEPIC topologies, the controller
operates in a quasi−resonant mode to provide high efficiency. Due to a
novel control method, the device is able to tightly regulate a constant
LED current from the primary side and provides near−unity power
factor. This removes the need for secondary side feedback circuitry, its
biasing and for an optocoupler.
The device is highly integrated with a minimum number of external
components. A robust suite of safety protection is built in to simplify
the design. This device is specifically intended for very compact space
efficient designs and also provides a constant voltage regulation of the
output if no load is connected to the LED driver.
MARKING
DIAGRAM
8
1
L30388x
ALYWX
G
SOIC−7
CASE 751U
L30388
= Specific Device Code
= Version
= Assembly Location
= Wafer Lot
x
A
L
Features
• High Voltage Startup
Y
W
G
= Year
= Work Week
• Quasi−resonant Peak Current−mode Control Operation
• Primary Side Feedback
= Pb−Free Package
• CC / CV Control
• Tight LED Constant Current Regulation of 2% Typical
• Digital Power Factor Correction
• Cycle by Cycle Peak Current Limit
PIN CONNECTIONS
8
1
2
COMP
ZCD
HV
• Wide Operating V Range
CC
• −40 to + 125°C
• Robust Protection Features
6
5
3
4
VCC
DRV
CS
♦ Brown−Out
♦ OVP on V
GND
CC
♦ Constant Voltage / LED Open Circuit Protection
♦ Winding Short Circuit Protection
♦ Secondary Diode Short Protection
♦ Output Short Circuit Protection
♦ Thermal Shutdown
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
Typical Applications
• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
February, 2020 − Rev. 3
NCL30388/D
NCL30388
.
.
.
NCL30388
1
2
3
4
8
6
5
Figure 1. Typical Application Schematic in a Flyback Converter
PIN FUNCTION DESCRIPTION NCL30388
Pin No
Pin Name
COMP
ZCD
Function
Pin Description
1
2
OTA output for CV loop
Zero crossing Detection
This pin receives a compensation network to stabilize the CV loop
This pin connects to the auxiliary winding and is used to detect the
core reset event.
V
sensing
aux
This pin also senses the auxiliary winding voltage for accurate out-
put voltage control
3
4
5
6
8
CS
GND
DRV
VCC
HV
Current sense
−
This pin monitors the primary peak current.
The controller ground
Driver output
The driver’s output to an external MOSFET
This pin is connected to an external auxiliary voltage.
Supplies the controller
High Voltage sensing
This pin connects after the diode bridge to provide the startup cur-
rent and internal high voltage sensing function.
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2
NCL30388
INTERNAL CIRCUIT ARCHITECTURE
CS_shorted
Enable
V
V
REF
STOP
OFF
DD
Internal
Thermal
VCC
UVLO
Latch
Shutdown
Fault
Management
VCC Management
COMP
Aux_SCP
VCC_max
VCC Ov er Voltage
Ipkmax
Protection
HV
STUP
W OD_SCP
BO_NOK
Constant Voltage Control
V
CV
V
HVdiv
FF_mode
Qdrv
V
V
HVdiv
REF
HV
BO_NOK
Brown−Out
FF_mode
Zero Crossing Detection Logic
ZCD
ValleySelection
(ZCD Blanking , Time−Out, ...)
FrequencyFoldback
VCC
Aux. W inding Short Circuit Prot.
S
Qdrv
Aux_SCP
Q
Q
Clamp
Circuit
V
HVdiv
V
VLY
DRV
R
Line
feed-fo rward
STOP
V
REF(PFC)
CS
Leading
Edge
CS_reset
Constant-C urrent Control
Blanking
Ipkmax
STOP
Enable
V
CV
Max. Peak
Current
Ipkmax
Limit
VREF
setpoint
CS Short
Protection
V
CS_shorted
REF
Generation of the
Reference Voltage
for Power Factor Corr.
W inding and
Output diode
Short Circuit
Protection
V
V
HVdiv
REF(PFC)
W OD_SCP
GND
Figure 2. Internal Circuit Architecture NCL30388
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3
NCL30388
MAXIMUM RATINGS TABLE
Symbol
Rating
Value
Unit
V
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3 to 30
Internally limited
V
mA
CC(MAX)
CC(MAX)
I
V
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3, V
(Note 1)
V
mA
DRV(MAX)
DRV(MAX)
DRV
I
−300, +500
V
Maximum voltage on HV pin
Maximum current for HV pin (dc current self−limited if operated within the allowed range)
−0.3, +700
V
mA
HV(MAX)
HV(MAX)
I
20
V
Maximum voltage on low power pins (except pins HV, DRV and VCC)
Current range for low power pins (except pins HV, DRV and VCC)
−0.3, 5.5 (Notes 2 and 6)
−2, +5
V
mA
MAX
MAX
I
R
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
180
°C/W
°C
θ
J−A
T
150
J(MAX)
−40 to +125
°C
Storage Temperature Range
−65 to +150
°C
ESD Capability, HBM model (Note 3)
ESD Capability, MM model (Note 3)
ESD Capability, CDM model (Note 3)
2
300
1
kV
V
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. V
is the DRV clamp voltage V
when V is higher than V
. V
is V otherwise.
DRV
DRV(high)
CC
DRV(high) DRV CC
2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages
can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Charged Device Model 2000 V per JEDEC Standard JESD22−C101D
4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, , V = 0 V) For min/max values
CS
J
CC
ZCD
T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
HIGH VOLTAGE SECTION
High voltage current source
High voltage current source
V
CC
= V
– 200 mV
I
I
3.3
4.7
300
2
6.1
mA
mA
V
CC(on)
HV(start2)
V
= 0 V
CC
HV(start1)
V
CC
level for I
to I
HV(start2)
transition
V
CC(TH)
HV(start1)
Minimum startup voltage
HV source leakage current
V
= 0 V
V
−
17
−
V
CC
HV(MIN)
HV(leak)
V
HV
= 450 V
I
4.5
10
mA
Vrms
Maximum rms input voltage for correct operation of the PFC
V
265
HV(OL)
loop (T = −20°C to 125°C)
J
SUPPLY SECTION
Supply Voltage
V
Startup Threshold
V
increasing
increasing
decreasing
decreasing
V
16
9.77
8.2
7.8
4
18
10.50
8.8
−
20
11.24
9.4
−
CC
CC
CC(on)
Threshold for turning off DSS (Note 5)
Minimum Operating Voltage
V
V
CC(on2)
V
CC
V
CC
V
CC(off)
CC(HYS)
CC(reset)
Hysteresis V
– V
V
V
CC(on)
CC(off)
Internal logic reset
5
6
Over Voltage Protection
CC
V
25.0
26.5
28
V
CC(OVP)
V
OVP threshold
V
V
noise filter (Note 6)
CC(reset)
t
−
−
5
20
−
−
ms
CC(off)
VCC(off)
noise filter− (Note 6)
t
VCC(reset)
Supply Current
mA
Device Disabled/Fault
V
> V
I
I
I
I
1.2
–
1.5
3.0
3.3
2.9
1.8
3.5
4.0
3.4
CC
sw
CC(off)
CC1
CC2
CC3
CC4
Device Enabled/No output load on pin 5
F
= 65 kHz
= 470 pF,
= 65 kHz
sw
Device Switching (F = 65 kHz)
C
−
sw
sw
DRV
Device switching (F = 15 kHz)
F
−
V
= 10%of max value
REFX
5. Refer to ordering table option at the end of the document
6. Guaranteed by design.
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4
NCL30388
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, , V = 0 V) For min/max values
CS
J
CC
ZCD
T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CURRENT SENSE
Maximum Internal current limit
V
1.31
270
−
1.38
330
100
39
1.45
390
150
49
V
ns
ns
ms
ms
V
ILIM
LEB
ILIM
Leading Edge Blanking Duration for V
t
ILIM
Propagation delay from current detection to gate off−state
Maximum on−time (option B)
t
t
29
on(MAX)
Maximum on−time (option A)
t
16
20
24
on(MAX2)
Threshold for immediate fault protection activation (140% of V
)
V
1.91
−
1.99
170
500
60
2.07
−
ILIM
CS(stop)
Leading Edge Blanking Duration for V
t
ns
mA
mV
CS(stop)
BCS
CS(short)
Current source for CS to GND short detection
Current sense threshold for CS to GND short detection
GATE DRIVE
I
400
20
600
100
V
CS
rising
V
CS(low)
Drive Resistance
DRV Sink
DRV Source
W
R
R
−
−
13
30
−
−
SNK
SRC
Drive current capability
DRV Sink (Note GBD)
DRV Source (Note GBD)
mA
I
−
−
500
300
−
−
SNK
I
SRC
Rise Time (10 % to 90 %)
Fall Time (90 % to 10 %)
DRV Low Voltage
C
C
= 470 pF
= 470 pF
t
–
–
8
30
20
–
−
−
−
ns
ns
V
DRV
r
t
DRV
f
V
= V
+0.2 V
V
CC
C
CC(off)
DRV(low)
= 470 pF,
DRV
R
=33 kW
DRV
DRV High Voltage
V
= V
V
10
12
14
V
CC
CC(MAX)
DRV(high)
C
= 470 pF,
DRV
R
=33 kW
DRV
ZERO VOLTAGE DETECTION CIRCUIT
Upper ZCD threshold voltage
V
rising
falling
V
−
35
90
55
150
−
mV
mV
mV
ns
ZCD
ZCD(rising)
V
ZCD(falling)
Lower ZCD threshold voltage
V
ZCD
ZCD hysteresis
V
15
−
−
ZCD(HYS)
ZCD(DEM)
Propagation Delay from valley detection to DRV high
Blanking delay after on−time (ZCD blank option B)
Blanking Delay at light load (ZCD blank option B)
Blanking delay after on−time (ZCD blank option A)
Blanking Delay at light load (ZCD blank option A)
Timeout after last DEMAG transition
Pulling−down resistor
V
decreasing
t
−
−
150
1.9
1.0
1.25
0.75
8
ZCD
V
> 0.35 V
< 0.25 V
> 0.35 V
< 0.25 V
t
t
t
t
1.1
0.6
0.75
0.45
5
1.5
0.8
1.0
0.6
6.5
200
ms
REFX
REFX
REFX
REFX
ZCD(blank1)B
ZCD(blank2)B
ZCD(blank1)A
ZCD(blank2)A
V
ms
V
V
ms
ms
t
ms
TIMO
V
= V
R
ZCD(pd)
kW
ZCD
ZCD(falling)
CONSTANT CURRENT CONTROL
Reference Voltage at T = 25°C to 85°C
V
V
0.326
0.323
20
0.333
0.333
50
0.340
0.343
100
V
V
J
REF
Reference Voltage T = −40°C to 125°C
J
REF
Current sense lower threshold for detection of the leakage in-
ductance reset time
V
CS
falling
V
mV
CS(low)
Blanking time for leakage inductance reset detection
CONSTANT VOLTAGE SECTION
t
−
120
−
ns
CS(low)
Internal voltage reference for constant voltage regulation
T = 25°C
J
V
V
2.42
2.38
2.48
2.48
2.54
2.58
V
V
REF(CV)
Internal voltage reference for constant voltage regulation
T = −40°C to 125°C
J
REF(CV)
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NCL30388
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, , V = 0 V) For min/max values
CS
J
CC
ZCD
T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
CONSTANT VOLTAGE SECTION
CV Error amplifier Gain
G
40
50
60
60
mS
mA
V
EA
Error amplifier current capability
COMP pin lower clamp voltage
COMP pin higher clamp voltage
V
=V
I
EA
REFX
REF
V
0.6
4.1
2
CV(clampL)
CV(clampH)
V
V
ZCD pin voltage below which the CV OTA is boosted
Error amplifier current capability during boost phase
V
* 80%
V
1.88
2.69
2.12
3.04
V
REF(CV)
boost(CV)
I
140
2.87
1.5
2.625
3.43
2
mA
V
EAboost
ZCD slow OVP threshold (V
*115%)
V
OVP1
ref(CV)
Switching period during slow OVP
T
ms
V
sw(OVP1)
ZCD voltage at which slow OVP is exit (V
ZCD fast OVP threshold
*105%)
V
OVP1rst
ref(CV)
V
OVP2
3.29
1.88
3.57
2.12
V
ZCD pin voltage below which the CV OTA is boosted
V
* 80%
V
V
REF(CV)
boost(CV)
LINE FEED FORWARD
V
to I
conversion ratio
K
0.153
76
0.185
95
0.217
114
42
mA/V
mA
HV
CS(offset)
LFF
I
offset(MAX)
Offset current maximum value
V
> 400 V
HV
Line feed−forward current
DRV high, V = 200 V
I
32
37
mA
HV
FF
VALLEY LOCKOUT SECTION
Threshold for line range detection V increasing
V
increases
decreases
V
HL
252
241
15
264
253
25
276
265
35
V
V
in
HV
Threshold for line range detection V decreasing
in
V
HV
V
LL
Blanking time for line range detection
t
ms
%
HL(blank)
Valley thresholds (expressed as a percentage of V
)
REF
st
nd
nd
rd
1
to 2 valley transition at LL and 2 to 3 valley HL, V
decr.
incr.
decr.
incr.
decr.
incr.
decr.
incr.
V
decreases
V
V
V
V
V
V
V
V
80
90
65
75
50
60
35
45
REF
REF
REF
REF
REF
REF
REF
REF
REF
VLY1−2/2−3
VLY2−1/3−2
VLY2−3/3−4
VLY3−2/4−3
VLY3−4/4−5
VLY4−3/5−4
VLY4−5/5−6
VLY5−4/6−5
nd
nd
st
rd
nd
th
th
th
rd
rd
th
th
th
th
nd
th
rd
th
th
th
2
to 1 valley transition at LL and 3 to 2 valley HL, V
V
increases
decreases
increases
decreases
increases
decreases
increases
REF
REF
2
to 3 valley transition at LL and 3 to 4 valley HL, V
V
rd
3
to 2 valley transition at LL and 4 to 3 valley HL, V
V
REF
REF
rd
3
to 4 valley transition at LL and 4 to 5 valley HL, V
V
th
4
to 3 valley transition at LL and 5 to 4 valley HL, V
V
REF
REF
th
4
to 5 valley transition at LL and 5 to 6 valley HL, V
V
th
th
th
th
5
to 4 valley transition at LL and 6 to 5 valley HL, V
V
REF
V
REF
V
REF
value at which the FF mode is activated
value at which the FF mode is removed
V
decreases
increases
V
V
25
35
%
%
REF
FFstart
V
REF
FFstop
FREQUENCY FOLDBACK
Added dead time
V
= 25%V
t
1.4
2.0
40
2.6
−
ms
ms
ms
ms
ms
REFX
REF
FF1LL
Added dead time
V
= 8% V
t
−
REFX
REF
FFchg
FFend
Dead−time clamp (Maximum dead−time option C)
Dead−time clamp (Maximum dead−time option B)
Dead−time clamp (Maximum dead−time option A)
FAULT PROTECTION
V
V
< 1 mV
< 3 mV
t
1.4
687
250
−
REFX
REFX
t
−
−
−
FFend2
FFend3
V
< 11.2 mV
t
−
REFX
Thermal Shutdown
Device switching (F
around 65 kHz)
T
SHDN
130
150
170
°C
SW
Thermal Shutdown Hysteresis
T
−
50
–
°C
SHDN(HYS)
Threshold voltage for output short circuit or aux. winding short
circuit detection
V
0.8
1.0
1.2
V
ZCD(short)
Short circuit detection Timer
V
ZCD
< V
t
OVLD
70
3
90
4
110
5
ms
s
ZCD(short)
Auto−recovery Timer
t
recovery
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NCL30388
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T = 25°C, V = 12 V, V
= 0 V, , V = 0 V) For min/max values
CS
J
CC
ZCD
T = −40°C to +125°C, Max T = 150°C, V = 12 V)
J
J
CC
Description
Test Condition
Symbol
Min
Typ
Max
Unit
BROWN−OUT AND LINE SENSING
Brown−Out ON level (IC start pulsing)
Brown−Out OFF level (IC stops pulsing)
BO comparators delay
V
increasing
decreasing
V
104
93
110
99
30
25
55
5
116
105
V
V
HV
HVBO(on)
HVBO(off)
BO(delay)
BO(blank)
V
HV
V
t
t
ms
ms
V
Brown−Out blanking time
15
35
HV pin voltage above which the sampling of ZCD is enabled
Sampling Enable comparator hysteresis
V
HV
decreasing
increasing
V
sampEN
V
HV
V
V
sampHYS
TYPICAL CHARACTERISTICS
18.30
18.25
18.20
18.15
18.10
8.90
8.88
8.86
8.84
8.82
8.80
18.05
18.00
8.78
8.76
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 3. VCC(on) vs. Junction Temperature
Figure 4. VCC(off) vs. Junction Temperature
28.0
27.5
27.0
26.5
1.45
1.43
1.41
1.39
1.37
1.35
26.0
25.5
25.0
1.33
1.31
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. VCC(OVP) vs. Junction Temperature
Figure 6. VILIM vs. Junction Temperature
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NCL30388
TYPICAL CHARACTERISTICS
100
90
80
70
60
50
40
2.07
2.05
2.03
2.01
1.99
1.97
1.95
30
20
1.93
1.91
−50
−25
0
25
50
75
100
125
125
125
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
T , JUNCTION TEMPERATURE (°C)
J
J
Figure 7. VCS(low)F vs. Junction Temperature
Figure 8. VCS(stop) vs. Junction Temperature
144
134
124
114
104
94
335.5
334.5
333.5
332.5
84
331.5
330.5
74
64
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
T , JUNCTION TEMPERATURE (°C)
J
J
Figure 9. tILIM vs. Junction Temperature
Figure 10. VREF vs. Junction Temperature
60
58
56
54
52
50
48
46
44
2.511
2.506
2.501
2.496
2.491
2.486
2.481
2.476
2.471
2.466
42
40
−50
−50
−25
0
25
50
75
100
−25
0
25
50
75
100 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. VREF(CV) vs. Junction Temperature
Figure 12. GEA vs. Junction Temperature
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NCL30388
TYPICAL CHARACTERISTICS
3.46
2.883
2.878
2.873
2.868
2.863
2.858
2.853
2.848
3.45
3.44
3.43
3.42
3.41
3.40
2.843
2.838
−50
−25
0
25
50
75
100
125
125
125
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
T , JUNCTION TEMPERATURE (°C)
J
J
Figure 13. VOVP1 vs. Junction Temperature
Figure 14. VOVP2 vs. Junction Temperature
0.190
0.188
0.186
0.184
37.8
37.6
37.4
37.2
37.0
36.8
36.6
36.4
0.182
0.180
36.2
36.0
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 15. KLFF vs. Junction Temperature
Figure 16. IFF vs. Junction Temperature
100.2
99.7
99.2
111.2
110.7
110.2
98.7
98.2
109.7
109.2
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100 125
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 17. VHVBO(on) vs. Junction Temperature
Figure 18. VHVBO(off) vs. Junction Temperature
www.onsemi.com
9
NCL30388
APPLICATION INFORMATION
The NCL30388 implements a current−mode architecture
while keeping accurate constant current and constant
operating in quasi−resonant mode. Due to proprietary
circuitry, the controller is able to accurately regulate the
secondary side current and voltage of the fly−back converter
without using any opto−coupler or measuring directly the
secondary side current or voltage.
voltage control.
• Line Feed−forward: allows compensating the variation
of the output current caused by the propagation delay.
• V Over Voltage Protection: if the V pin voltage
CC
CC
exceeds an internal limit, the controller shuts down and
waits 4 seconds before restarting pulsing.
The controller provides near unity power factor
correction.
• Fast Over Voltage Protection: If the voltage of ZCD pin
exceeds 130% of its regulation level, the controller
shuts dwon and waits 4 s before trying to restart.
• Brown−Out: the controller includes a brown−out circuit
which safely stops the controller in case the input
voltage is too low. The device will automatically restart
if the line recovers.
• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30388 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Due to an internal algorithm
control, the controller locks−out in a selected valley and
remains locked until the input voltage or the output
current set point significantly changes.
• Primary Side Constant Current Control: thanks to a
proprietary circuit, the controller is able to take into
account the effect of the leakage inductance of the
transformer and allows an accurate control of the
secondary side current regardless of the input voltage
and output load variation
• Primary Side Constant Voltage Regulation: By
monitoring the auxiliary winding voltage, it is possible
to regulate accurately the output voltage. The output
voltage regulation is typically within 2%.
• Load Transient Compensation: Since PFC has low loop
bandwidth, abrupt changes in the load may cause
excessive over or under−shoot. The slow Over Voltage
Protection contains the output voltage when it tends to
become excessive. In addition, the NCL30388 speeds
up the constant voltage regulation loop when the output
voltage goes below 80% of its regulation level.
• Cycle−by−cycle peak current limit: when the current
sense voltage exceeds the internal threshold V
, the
ILIM
MOSFET is turned off for the rest of the switching
cycle.
• Winding Short−Circuit Protection: an additional
comparator senses the CS signal and stops the
controller if V reaches 1.4 x V
(after a reduced
CS
ILIM
LEB of t ). This additional comparator is enabled
BCS
only during the main LEB duration t
immunity reason.
, for noise
LEB
• Output Under Voltage Protection: If a too low voltage is
applied on ZCD pin for 90−ms time interval, the
controllers assume that the output or the ZCD pin is
shorted to ground and shutdown. After waiting 4
seconds, the IC restarts switching.
• Thermal Shutdown: an internal circuitry disables the
gate drive when the junction temperature exceeds
150°C (typically). The circuit resumes operation once
the temperature drops below approximately 100°C.
• Power Factor Correction: A proprietary concept allows
achieving high power factor correction and low THD
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10
NCL30388
POWER FACTOR AND CONSTANT CURRENT
CONTROL
The NCL30388 embeds an analog/digital block to control
the power factor and regulate the output current by
monitoring the ZCD, CS and HV pin voltages (signals
Where:
♦ N is the secondary to primary transformer turns
sp
ratio: N = N / N .
sp S P
♦ R
♦ V
V
is the current sense resistor
sense
is the output current reference: V
=
REFX
REFX
V
ZCD
, V
, V ). This circuit generates the current
if V
≥ 4 V
HV_DIV
CS
REF
COMP
setpoint V
and compares it to the current sense
The output current reference (V
) is V
unless the
CTRL_DIV
REFX
REF
signal to turn the MOSFET off. The HV pin provides the
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half line period, it is equal to the
constant voltage mode is activated.
CONSTANT VOLTAGE CONTROL
The auxiliary winding voltage is sampled internally
through the ZCD pin.
A precise internal voltage reference V
voltage target for the CV loop.
output current reference (V
). The modulation and
REFX
sets the
REF(CV)
averaging process is made internally by a digital circuit. If
the HV pin properly conveys the sinusoidal shape, power
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low especially if the output voltage ripple is
small.
The sampled voltage is applied to the negative input of the
CV OTA and compared to V
.
REFCV
A type 2 compensator is needed at the CV OTA output to
stabilize the loop. The COMP pin voltage modify the the
output current internal reference in order to regulate the
output voltage.
The output current will be well regulated,
following the equation below:
VREFX
When V
When V
≥ 4 V, V
= V
.
COMP
COMP
REFX
< 0.6 V, V
REF
(eq. 1)
IOUT
+
2NspRsense
= 0 V
REFX
Gm
RZCDU
ZCD
VZCDsamp
ZCD & signal
sampling
COMP
.
R1
C1
RZCDL
OTA
VREF(CV)
C2
Aux.
Figure 19. Constant Voltage Feedback Circuit
STARTUP PHASE (HV STARTUP)
To speed−up the output voltage rise, the following is
implemented:
It is generally requested that the LED driver starts to emit
light in less than 1 s and possibly within 300 ms. It is
challenging since the start−up consists of the time to charge
• The digital OTA output is increased until V
REF(PFC)
. Again, this is to speed−up the
signal reaches V
REFX
the V capacitor and that necessary to charge the output
CC
control signal rise to their steady state value.
capacitor until sufficient current flows into the LED string.
This second phase can be particularly long in dimming cases
where the secondary current is a portion of the nominal one.
The NCL30388 features a high voltage startup circuit that
allows charging VCC capacitor very fast.
• At the beginning of each operating phase of a V
CC
cycle, the digital OTA output is set to 0. Actually, the
digital OTA output is set to 0 in the case of a cold
start−up or in the case of a start−up sequence following
an operation interruption due to a fault. On the other
When the power supply is first connected to the mains
outlet, the internal current source is biased and charges up
hand, if the V hiccups just because the system fails to
CC
start−up in one V cycle (DSS option not activated),
CC
the V capacitor. When the voltage on this V capacitor
CC
CC
the digital OTA output is not reset to ease the second
(or more) attempt.
reaches the V
level, the current source turns off. At this
CC(on)
time, the controller is only supplied by the V capacitor,
CC
• If the load is shorted, the circuit will operate in hiccup
and the auxiliary supply should take over before V
CC
mode with V oscillating between V
and
CC
CC(off)
collapses below V
.
CC(off)
V
CC(on)
until the output under voltage protection (UVP)
The HV startup circuitry is made of two startup current
levels, I and I . This helps to protect the
trips. UVP is triggered if the ZCD pin voltage does not
exceed 1 V within a 90 ms operation of time. This
indicates that the ZCD pin is shorted to ground or that
an excessive load prevents the output voltage from
rising.
HV(start1)
HV(start1)
controller against short−circuit between V and GND. At
CC
power−up, as long as V is below V
, the source
CC
CC(TH)
delivers I
(around 300 mA typical). Then, when
HV(start1)
V
CC
reaches V
, the source smoothly transitions to
CC(TH)
I
and delivers its nominal value.
HV(start2)
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11
NCL30388
CYCLE−BY−CYCLE CURRENT LIMIT
When the current sense voltage exceeds the internal
threshold V , the MOSFET is turned off for the rest of the
VALLEY LOCKOUT
Quasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequency
increases when the output load decreases or when the input
voltage increases. The switching frequency of such systems
must be limited.
ILIM
switching cycle.
WINDING AND OUTPUT DIODE SHORT−CIRCUIT
PROTECTION
In parallel to the cycle−by−cycle sensing of the CS pin,
The NCL30388 changes valley as V
decreases and as
REFX
the input voltage increases and as the output current setpoint
is varied during dimming. This limits the frequency
excursion.
By default, when the output current is not dimmed, the
controller operates in the first valley at low line and in the
second valley at high line.
another comparator with a reduced LEB (t ) and a
BCS
threshold of (V
= 140% *V ) monitors the CS pin
ILIM
CS(stop)
to detect a winding or an output diode short circuit. The
controller shuts down if it detects four consecutive pulses
during which the CS pin voltage exceeds V
CS(stop).
The controller goes into auto−recovery mode.
HV pin voltage for valley change
REFX value at which the
controller changes valley
(Iout decreasing)
VREFX value at which the
controller changes valley
(Iout increasing)
0
−−LL −− 230 V −−HL −− 400 V
100%
80%
100%
85%
1st
2nd
2nd
3rd
3rd
4th
65%
50%
35%
70%
55%
40%
4th
5th
5th
6th
25%
0%
30%
0%
FF mode
FF mode
0
−−LL −− 240 V −−HL −− 400 V
HV pin voltage for valley change
Figure 20. TABLE II: Valley Selection
ZERO CROSSING DETECTION BLOCK
At startup, the output voltage reflected on the auxiliary
winding is low. Because of the ZCD resistor bridge setting
the constant voltage regulation target, the voltage on the
ZCD pin is very low and the ZCD comparator might be
unable to detect the valleys. In this condition, setting the
DRV Latch with the 6.5−ms time−out leads to a continuous
conduction mode operation (CCM) at the beginning of the
soft−start. This CCM operation only last a few cycles until
the voltage on ZCD pin becomes high enough and trips the
ZCD comparator.
The ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.
A valley is detected when the ZCD pin voltage crosses
below the 55 mV internal threshold.
At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, the NCL30388 a
Time−Out circuit that generates pulses if the voltage on ZCD
pin stays below the 55 mV threshold for 6.5 ms.
The Time−out also acts as a substitute clock for the valley
detection and simulates a missing valley in case of too
damped free oscillations.
www.onsemi.com
12
NCL30388
VZCD
VZCD(th)
low
3
4
high
14
12
I
out decreases or Vin
Vin increases
high
ZCD comp
high
low
15
low
TimeOut
16
2nd , 3rd
high
VVIN
increases
Clock
low
17
Figure 21.
If the ZCD pin or the auxiliary winding happen to be
shorted the time−out function would normally make the
controller keep switching and hence lead to improper
regulation of the LED current.
The Under Voltage Protection (UVP) is implemented to
avoid these scenarios: a secondary timer starts counting
features a slow over voltage protection (slow OVP) and a
fast over voltage protection (fast OVP) on ZCD pin.
Slow OVP
If ZCD voltage exceed V
for four consecutive
ZCD(OVP1)
switching cycles, the controller stops switching during
1.4 ms. After 1.4 ms, the controller initiates a new DRV
when the ZCD voltage is below the V
threshold. If
ZCD(short)
pulse to refresh ZCD sampling voltage. If V
is still too
ZCD
this timer reaches 90 ms, the controller detects a fault and
enters the auto−recovery fault mode.
high (V
> 110%V
), the controller continues to
ZCD
REF(CV)
switch with a 1.4 ms period. The controller resumes its
normal operation when V
< 110%V
.
ZCD PIN OVER VOLTAGE PROTECTION.
ZCD
REF(CV)
Because of the power factor correction, it is necessary to
set the crossover frequency of the CV loop very low (target
10 Hz, depending on power stage phase shift). Because the
loop is slow, the output voltage can reach high value during
startup or during an output load step. It is necessary to limit
the output voltage excursion. For this, the NCL30388
Fast OVP
If ZCD voltage exceeds V
for 4 consecutive switching cycles (slow OVP not triggered)
or for 2 switching cycles if the slow OVP has already been
triggered, the controller detects a fault and starts the
auto−recovery fault mode (cf: Protections Section)
(130% of V
)
ZCD(OVP2)
REF(CV)
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13
NCL30388
LINE FEEDFORWARD
HV
vDD
vVS
CS
RLFF
ICS(offset)
KLFF
Rsense
Q_drv
+
25 ms
Blanking
BO_NOK
−
1 V / 0.9 V
Figure 22. Line Feed−Forward and Brown−out Schematic
The line voltage is sensed by the HV pin and converted
into a current. By adding an external resistor in series
between the sense resistor and the CS pin, a voltage offset
proportional to the line voltage is added to the CS signal. The
offset is applied only during the MOSFET on−time in order
to not influence the detection of the leakage inductance
reset.
ESD diode is conducting. Practically, the ESD diode of
CS pin is monitored. If such a fault is detected for
200 ms, the circuit stops generating DRV pin.
• Output short circuit situation (Output Under Voltage
Protection)
Overload is detected by monitoring the ZCD pin
voltage: if it remains below V
for 90 ms, an
ZCD(short)
The offset is always applied even at light load in order to
improve the current regulation at low output load.
output short circuit is detected and the circuit stops
generating pulses for 4 s. When this 4 s delay has
elapsed, the circuit attempts to restart.
BROWN−OUT
• ZCD pin incorrect connection:
In order to protect the supply against a very low input
voltage, the NCL30388 features a brown−out circuit with a
fixed ON/OFF threshold. The controller is allowed to start
if a voltage higher than 100 V is applied to the HV pin and
shuts−down if the HV pin voltage decreases and stays below
90 V for 25 ms typical. Exiting a brown−out condition
♦ If the ZCD pin grounded, the circuit will detect an
output short circuit situation when 90 ms delay has
elapsed.
♦ A 200 kW resistor pulls down the ZCD pin so that
the output short circuit detection trips if the ZCD pin
is not connected (floating).
overrides the hiccup on V (V does not wait to reach
CC
CC
• Winding or Output Diode Short Circuit protection
The circuit detects this failure when 4 consecutive DRV
pulses occur within which the CS pin voltage exceeds
V
) and the IC immediately goes into startup mode.
CC(off)
PROTECTIONS
The circuit incorporates a large variety of protections to
make the LED driver very rugged.
(V =140% *V ). In this case, the controller
CS(stop) ILIM
enters auto−recovery mode (4 s operation interruption
Among them, we can list:
between active bursts).
• Fault of the GND connection
• V Over Voltage Protection
CC
If the GND pin is properly connected, the supply
The circuit stops generating pulses if the V exceeds
CC
current drawn from the positive terminal of the V
V
and enters auto−recovery mode (4 s operation
CC
CC(OVP)
capacitor, flows out of the GND pin to return to the
interruption between active bursts).
This feature protects the circuit if output LEDs happen
to be disconnected.
negative terminal of the V capacitor. If the GND pin
CC
is not connected, the circuit ESD diodes offer another
return path. The accidental non connection of the GND
pin can hence be detected by detecting that one of this
www.onsemi.com
14
NCL30388
• ZCD fast OVP
• CS pin short to ground
The CS pin is checked at start−up (cold start−up or after
a brown−out event). A current source (I ) is
If ZCD voltage exceeds V
for 4 consecutive
ZCD(OVP2)
switching cycles (slow OVP not triggered) or for 2
switching cycles if the slow OVP has already been
triggered, the controller detects a fault and enters
auto−recovery mode (4−s operation interruption
between active bursts).
cs(short)
applied to the pin and no DRV pulse is generated until
the CS pin exceeds V . I and V are
cs(low) cs(short)
cs(low)
500 mA and 60 mV typically (V rising). The typical
CS
minimum impedance to be placed on the CS pin for
operation is then 120 W. In practice, it is recommended
to place more than 250 W to take into account possible
parametric deviations.
Also, along the circuit operation, the CS pin could
happen to be grounded. If it is grounded, the MOSFET
conduction time is limited by the maximum on−time. If
such an event occurs, a new pin impedance test is
made.
• Die Over Temperature (TSD)
The circuit stops operating if the junction temperature
(T ) exceeds 150°C typically. The controller remains
J
off until T goes below nearly 100°C.
J
• Brown−Out Protection (BO)
The circuit prevents operation when the line voltage is
too low to avoid an excessive stress of the LED driver.
Operation resumes as soon as the line voltage is high
enough and V is higher than V
.
CC
CC(on)
ORDERING TABLE OPTION
Line Range
Detector
DSS
Maximum Dead−time
V
REF
Max. On−time
ZCD Blanking
Y
On
x
N
A
B
C
U
V
A
B
A
B
1.5 ms
x
Y
N
Off
x
Off
250 ms 687 ms 1.4 ms 250 mV 333 mV 20 ms
33 ms
1 ms
On
OPN #
NCL30388A1
NCL30388B1
x
x
x
x
x
x
x
x
x
ORDERING INFORMATION2
Device
†
Marking
L30388A1
L30388B1
Package type
Shipping
NCL30388A1DR2G
NCL30388B1DR2G
SOIC8 – P7 COMP VHV PBFH
SOIC8 – P7 COMP VHV PBFH
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
SCALE 1:1
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
S
M
M
B
−B−
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189 0.197
4.00 0.150 0.157
1.75 0.053 0.069
0.51 0.013 0.020
0.050 BSC
0.25 0.004 0.010
0.25 0.007 0.010
1.27 0.016 0.050
C
R X 45
_
1.27 BSC
J
0.10
0.19
0.40
0
−T−
SEATING
PLANE
K
8
0
8
_
_
_
_
M
H
D 7 PL
0.25
5.80
0.50 0.010 0.020
6.20 0.228 0.244
M
S
S
0.25 (0.010)
T
B
A
GENERIC
MARKING DIAGRAM
SOLDERING FOOTPRINT*
8
XXXXX
ALYWX
1.52
0.060
G
1
XXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
7.0
0.275
4.0
0.155
Y
W
G
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12199D
7−LEAD SOIC
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−7
CASE 751U−01
ISSUE E
DATE 20 OCT 2009
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6.
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. EMITTER, #2
7. NOT USED
8. EMITTER, #1
6. SOURCE, #2
7. NOT USED
8. SOURCE, #1
7. NOT USED
8. EMITTER
STYLE 4:
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5.
STYLE 6:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. NOT USED
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6.
6.
7. NOT USED
8. SOURCE
7. NOT USED
8. SOURCE
8. COMMON CATHODE
STYLE 7:
STYLE 8:
PIN 1. COLLECTOR (DIE 1)
2. BASE (DIE 1)
STYLE 9:
PIN 1. INPUT
PIN 1. EMITTER (COMMON)
2. COLLECTOR (DIE 1)
3. COLLECTOR (DIE 2)
4. EMITTER (COMMON)
5. EMITTER (COMMON)
6. BASE (DIE 2)
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
3. BASE (DIE 2)
4. COLLECTOR (DIE 2)
5. COLLECTOR (DIE 2)
6. EMITTER (DIE 2)
7. NOT USED
7. NOT USED
7. NOT USED
8. FIRST STAGE Vd
8. COLLECTOR (DIE 1)
8. EMITTER (COMMON)
STYLE 10:
PIN 1. GROUND
2. BIAS 1
STYLE 11:
PIN 1. SOURCE (DIE 1)
2. GATE (DIE 1)
3. SOURCE (DIE 2)
4. GATE (DIE 2)
5. DRAIN (DIE 2)
6. DRAIN (DIE 2)
7. NOT USED
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. NOT USED
8. GROUND
8. DRAIN (DIE 1)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON12199D
7−LEAD SOIC
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
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