NCL30486B2DR2G_技术文档

DATA SHEET

www.onsemi.com

Dimmable Power Factor

Corrected LED Driver

9

1

SOIC−9 NB

CASE 751BP

Product Preview

NCL30486B

MARKING DIAGRAM

The NCL30486B is a power factor corrected flyback controller

targeting isolated constant current LED drivers. The controller

operates in a quasi−resonant mode to provide high efficiency. Thanks

to a novel control method, the device is able to tightly regulate a

constant LED current from the primary side. This removes the need

for secondary side feedback circuitry, its biasing and for an

optocoupler.

10

L30486XX

ALYW

G

1

The device is highly integrated with a minimum number of external

components. A robust suite of safety protection is built in to simplify

the design. This device is specifically intended for very compact space

efficient designs and supports analog and digital dimming with two

dedicated dimming inputs control ideal for Smart LED Lighting

applications.

L30486

XX

A

= Specific Device Code

= Version

= Assembly Location

= Wafer Lot

= Assembly Start Week

= Pb−Free Package

L

YW

G

Features

• High Voltage Startup

PIN CONNECTIONS

• Quasi−resonant Peak Current−mode Control Operation

• Primary Side Feedback

ADIM

HV

1

2

3

4

5

10

• CC / CV Accurate Control V up to 320 V rms

in

• Tight LED Constant Current Regulation of 2% Typical

• Digital Power Factor Correction

• Analog and Digital Dimming

COMP

PDIM

VCC

DRV

ZCD

CS

8

7

6

• Dimming Standby Mode (Dim CV Mode)

• Standby Mode

• Cycle by Cycle Peak Current Limit

GND

• Wide Operating V Range

CC

• −40 to +125°C

• Robust Protection Features

♦ Brown−Out

♦ OVP on V

CC

♦ Constant Voltage / LED Open Circuit Protection

♦ Winding Short Circuit Protection

♦ Secondary Diode Short Protection

♦ Output Short Circuit Protection

♦ Thermal Shutdown

ORDERING INFORMATION

See detailed ordering and shipping information on page 30 of

this data sheet.

♦ Line over Voltage Protection

• This is a Pb−Free Device

Typical Applications

• Integral LED Bulbs

• LED Power Driver Supplies

• LED Light Engines

This document contains information on a product under development. onsemi reserves

the right to change or discontinue this product without notice.

1

Publication Order Number:

December, 2021 − Rev. P1

NCL30486B/D

NCL30486B

.

Aux

.

V_ADIM

NCL30486

1

2

3

4

5

10

9

8

7

6

PWM signal

Figure 1. Typical Application Schematic for NCL30486B

PIN FUNCTION DESCRIPTION NCL30486B

Pin N5

1

Pin Name

Function

Pin Description

ADIM

Analog dimming

This pin is used for analog control of the output current. Applying a voltage varying

between V and V will dim the output current from 0% to 100%.

DIM(EN)

DIM100

2

3

COMP

ZCD

OTA output for CV loop This pin receives a compensation network to stabilize the constant voltage loop

Zero crossing Detection This pin connects to the auxiliary winding and is used to detect the core reset event.

V

sensing

This pin also senses the auxiliary winding voltage for accurate output voltage control

aux

4

5

6

7

8

CS

Current sense

−

This pin monitors the primary peak current.

GND

DRV

VCC

PDIM

The controller ground

Driver output

Supplies the controller

PWM dimming

The driver’s output to an external MOSFET

This pin is connected to an external auxiliary voltage.

This pin is used for PWM dimming control. An optocoupler can be connected directly

to the pin if the PWM control signal is from the secondary side

9

NC

HV

creepage

10

High Voltage sensing

This pin connects after the diode bridge to provide the startup current and internal

high voltage sensing function.

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2

NCL30486B

INTERNAL CIRCUIT ARCHITECTURE

STOP

L_OVP

VCC

COMP

Aux_SCP

Fast_OVP

Enable

Standby

V_CV

OFF

Fault

Management

VCC Management

UVLO

Constant Voltage

Control

Slow_OVP

Fast_OVP

Thermal

Shutdown

VCC

OVP

HV

Startup

VCC_OVP

CS_short

_HVdivSlow_OVP

V

V_REFX

dimCV_mode

HV

BO_NOK

L_OVP

Brown−Out

Line OVP

Zero crossing detection Logic

Z(CD blanking, Time−Out, ...)

ZCD

Valley Selection

Frequency foldback

Aux. Winding Short Circuit Prot.

Aux_SCP

V_HVdiv

Q_drv

V_HVdiv

Line

feed−forward

S

R

Q

Standby V_DIMAV_HVdivdc_DIM

DRV

Driver

and

Clamp

Enable

STOP

CS

V_REFX

Leading

Edge

Blanking

Power factor and

Constant−current control

CS_reset

Ipk_max

Maximum

on−time

Max. Peak

Current Limit

STOP

Winding /

Output diode

ADIM

PDIM

WOD_SCP

Analog

Dimming

SCP

V_DIMA

dimCV_mode

Enable

CS Short

Protection

CS_short

GND

PWM

Dimming

dc_DIM

dimCV_mode

Figure 2. Internal Circuit Architecture NCL30486B

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3

NCL30486B

MAXIMUM RATINGS TABLE

Symbol

Rating

Value

Unit

V

Maximum Power Supply Voltage, VCC Pin, Continuous Voltage

Maximum Current for VCC Pin

−0.3 to 30

Internally limited

V

mA

CC(MAX)

I

V

Maximum Driver Pin Voltage, DRV Pin, Continuous Voltage

Maximum Current for DRV Pin

−0.3, V

(Note 1)

V

mA

DRV(MAX)

DRV

I

−300, +500

V

Maximum Voltage on HV Pin

Maximum Current for HV Pin (dc Current Self−limited if Operated within the Allowed Range)

−0.3, +700

V

mA

HV(MAX)

I

20

V

Maximum Voltage on Low Power Pins (Except Pins DRV and VCC)

Current Range for Low Power Pins (Except Pins DRV and VCC)

−0.3, 5.5 (Note 2)

−2, +5

V

mA

MAX

I

R

Thermal Resistance Junction−to−Air

Maximum Junction Temperature

210

°C/W

°C

q

J−A

T

150

J(MAX)

Operating Temperature Range

−40 to +125

°C

Storage Temperature Range

−60 to +150

°C

ESD Capability, HBM Model Except HV Pin (Note 3)

ESD Capability, HBM Model HV Pin

ESD Capability, CDM Model (Note 3)

4

1.5

1

kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. V

is the DRV clamp voltage V

when V is higher than V

. V

is V otherwise.

DRV

DRV(high)

CC

DRV(high) DRV CC

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages

can be applied if the pin current stays within the −2 mA / 5 mA range.

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.

Charged Device Model 1000 V per JEDEC Standard JESD22−C101D.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V.

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

HIGH VOLTAGE SECTION

High Voltage Current Source

V

= V

– 200 mV

I

3.4

−

4.6

300

0.8

15

6.2

−

mA

CC

CC(on)

HV(start2)

I

HV(start1)

= 0 V

CC

V

CC

Level for I

to I

Transition

V

CC(TH)

−

V

HV(start1)

HV(start2)

Minimum Startup Voltage

HV Source Leakage Current

V

= 0 V

V

−

V

CC

HV(MIN)

HV(leak)

= 450 V

I

−

4.5

−

10

−

mA

HV

Maximum Input Voltage (rms) for Correct Operation of

the PFC Loop

V

320

V rms

HV(OL)

SUPPLY SECTION

Supply Voltage

V

Startup Threshold

V

CC

V

CC

V

CC

increasing

decreasing

V

16

9.3

7.6

4

18

10.2

−

20

10.7

−

CC(on)

CC(off)

Minimum Operating Voltage

Hysteresis V

– V

V

CC(on)

CC(off)

CC(HYS)

CC(reset)

Internal Logic Reset

V

5

6

Over Voltage Protection

VCC OVP Threshold

V

25

26.5

28

V

CC(OVP)

V

Noise Filter (Note 5)

CC(reset)

t

−

5

20

−

ms

CC(off)

VCC(off)

nOise Filter (Note 5)

t

VCC(reset)

Supply Current

mA

Device Disabled/Fault

V

> V

I

1.1

–

1.4

3.3

3.6

1.7

3.9

4.3

2

CC

sw

CC(off)

CC1

CC2

CC3

CC4

Device Enabled/No Output Load on Pin 5

F

= 65 kHz

Device Switching (F = 65 kHz)

C

= 470 pF, F = 65 kHz

−

sw

DRV

sw

Device Switching (F = 700 Hz)

V

COMP

≤ 0.9 V

−

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4

NCL30486B

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V.

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

CURRENT SENSE

Maximum Internal Current Limit

V

1.28

240

−

1.40

300

50

1.50

360

150

V

ILIM

LEB

ILIM

Leading Edge Blanking Duration for V

t

ns

ILIM

Propagation Delay from Current Detection to Gate

Off−state

t

Maximum On−time OPN1

Maximum On−time OPN2

t

10.5

16

14.0

20

17.5

24

ms

V

on(MAX)1

on(MAX)2

Maximum On−time V

< 0.15 V (OPN1)

< 0.15 V (OPN2)

t

5.3

8

7.0

10

8.7

12

REFX

on(MAX)12

on(MAX)22

t

Threshold for Immediate Fault Protection Activation

(140% of V

V

1.9

2.0

2.1

CS(stop)

)

ILIM

Leading Edge Blanking Duration for V

t

−

170

500

60

−

ns

mA

CS(stop)

BCS

Current Source for CS to GND Short Detection

I

400

20

600

90

CS(short)

Current Sense Threshold for CS to GND Short Detection

V

CS

rising

V

mV

CS(low)

Maximum Peak Current in Standby Mode

V

CS(SBY)

Option 1

Option 2

Option 3

342

297

252

380

330

280

418

363

308

GATE DRIVE

Drive Resistance

DRV Sink

DRV Source

W

R

SNK

R

SRC

−

13

30

−

Drive Current Capability

DRV Sink (Note GBD)

DRV Source (Note GBD)

mA

I

−

500

300

−

SNK

SRC

I

Rise Time (10% to 90%)

Fall Time (90 %to 10%)

DRV Low Voltage

C

= 470 pF

t

–

8

30

20

–

−

ns

V

DRV

CC

r

t

f

V

= V

+0.2 V

V

CC(off)

DRV(low)

C

DRV

= 470 pF, R

= 33 kW

DRV

DRV High Voltage

V

= V

V

10

12

14

V

CC

DRV

CC(MAX)

DRV(high)

C

= 470 pF, R

DRV

ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD Threshold Voltage

V

rising

falling

V

−

35

−

90

55

0.7

−

150

−

mV

V

ZCD

ZCD(rising)

V

ZCD(falling)

Lower ZCD Threshold Voltage

ZCD

Threshold to Force V

ZCD Hysteresis

Maximum During Startup

V

−

REFX

ZCD(start)

ZCD(HYS)

ZCD(DEM)

V

15

−

mV

ns

ms

Propagation Delay from Valley Detection to DRV High

Equivalent Time Constant for ZCD Input (GBD)

Blanking Delay after On−time (option 1)

Blanking Delay after On−time (option 2)

Blanking Delay at Light Load (option 1)

Blanking Delay at Light Load (option 2)

Timeout after Last DEMAG Transition

V

ZCD

decreasing

t

−

150

−

t

−

20

1.5

1.0

0.8

0.6

6.5

50

PAR

V

REFX

V

REFX

V

REFX

V

REFX

> 0.35 V

< 0.25 V

t

1.1

0.75

0.6

0.45

5

1.9

1.25

1.0

0.75

8

ZCD(blank1)

ZCD(blank2)

t

TIMO

Time−out after Last DEMAG Transition V

(Note 5)

< V

t

TIMOstart

−

ZCD

ZCD(start)

Pulling−down Resistor

V

= V

R

−

200

165

−

kW

mA

ZCD

ZCD(falling)

ZCD(pd)

ZCD Pin Current Source for Forcing CV Mode when

Minimum Dimming

V

ADIM

= 0.5 V

I

140

190

ZCDdim

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5

NCL30486B

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V.

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

CONSTANT CURRENT CONTROL

Reference Voltage

T = 25°C − 85°C

V

327.9 334.2 341.2

324.1 334.2 346.0

mV

j

REF/3

Reference Voltage

T = −40°C to 125°C

j

REF/3

10% Reference Voltage

5% Reference Voltage

T = 25°C − 85°C

j

V

30

33.33 36.66

REF10/3

REF05/3

T = −40°C to 125°C

j

27.33 33.33 39.33

T = 25°C − 85°C

j

14.17

13.34

20

17

50

19.17

20

T = −40°C to 125°C

j

Current Sense Lower Threshold for Detection of the

Leakage Inductance Reset Time

V

CS

falling

V

100

CS(low)

Blanking Time for Leakage Inductance Reset Detection

t

−

120

−

ns

CS(low)

POWER FACTOR CORRECTION

Clamping Value for V

T = 0°C to 125°C

V

REF(PFC)CLP

2.06

−

2.20

240

230

2.34

−

V

REF(PFC)

J

Line Range Detector for PFC Loop

CONSTANT VOLTAGE SECTION

V

HV

increases

decreases

V

Vdc

HL(PFC)

V

−

LL(PFC)

Internal Voltage Reference for Constant Voltage

Regulation

V

3.41

3.52

3.63

V

REF(CV)

CV Error Amplifier Gain

G

40

−

50

60

−

mS

mA

V

EA

Error Amplifier Current Capability

V

= V

(no dimming)

I

EA

REFX

REF

COMP Pin Lower Clamp Voltage

V

−

0.6

−

CV(clampL)

CV(clampH)

COMP Pin Higher Clamp Voltage

T = 0°C to 125°C

J

V

4.05

4.01

4.12

4.25

V

COMP Pin Higher Clamp Voltage

T = −40°C to 125°C

J

V

Internal ZCD Voltage below which the CV OTA is Boosted

Threshold for Releasing the CV Boost

Error Amplifier Current Capability During Boost Phase

V

* 85%

* 90%

V

2.796 2.975 3.154

V

REF(CV)

boost(CV)

V

2.96

3.15

140

3.34

V

boost(CV)RST

I

−

mA

V

EAboost

st

ZCD OVP 1 Level (Slow OVP) Option 1

V

* 115%

* 105%

V

OVP1

3.783 4.025 4.267

REF(CV)

ZCD Voltage at which Slow OVP is Exit (Option 1)

Switching Period During Slow OVP

ZCD Fast OVP Option 1

V

−

3.675

1.5

−

V

REF(CV)

OVP1rst

T

ms

V

sw(OVP1)

V

ref(CV)

* 125% + 150 mV

V

4.253 4.525 4.797

OVP2

OVP2_CNT

Number of Switching Cycles before Fast OVP

Confirmation

T

−

4

−

Duration for Disabling DRV Pulses During ZCD Fast OVP

T

−

4

−

s

recovery

COMP Pin Voltage below which Standby Mode is

Entered (Note 5)

V

decreasing

increasing

V

0.895

V

COMP

CMP(SBY)

COMP Standby Comparator Hysteresis (Note 5)

V

−

18

−

mV

COMP

CMP(SBY)HYS

LINE FEED FORWARD

V

HV

to I

Conversion Ratio

K

LFF

0.189 0.21 0.231 mA/V

CS(offset)

Offset Current Maximum Value

Line Feed−forward Current

V

> (450 V or 500 V)

I

76

35

95

40

114

45

mA

HV

offset(MAX)

DRV high, V = 200 V

I

FF

HV

VALLEY LOCKOUT SECTION

Threshold for Line Range Detection V Increasing

V

increases

decreases

V

HL

228

218

15

240

230

25

252

242

35

V

HV

> 80% V

HV

st

nd

(1 to 2 Valley Transition for V

)

REFX

REF

st

rd

(Prog. Option: 1 to 3 Valley Transition)

Threshold for Line Range Detection V Decreasing

V

LL

HV

nd

st

(2 to 1 Valley Transition for V

> 80% V

)

REFX

REF

rd

st

(Prog. Option: 3 to 1 Valley Transition)

Blanking Time for Line Range Detection

t

ms

HL(blank)

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6

NCL30486B

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V.

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

VALLEY LOCKOUT SECTION

Valley Thresholds

V

st

nd

rd

1

to 2 Valley Transition at LL and 2 to 3 Valley HL,

V

decreases

increases

decreases

increases

decreases

increases

decreases

increases

V

−

0.80

0.90

0.65

0.75

0.50

0.60

0.35

0.45

−

REF

VLY1−2/2−3

VLY2−1/3−2

VLY2−3/3−4

VLY3−2/4−3

VLY3−4/4−5

VLY4−3/5−4

VLY4−5/5−6

VLY5−4/6−5

rd

th

V

Decr. (Prog. Option: 3 to 4 Valley HL)

REF

nd

st

rd

nd

2

to 1 Valley Transition at LL and 3 to 2 Valley HL,

th

rd

V

Incr. (Prog. Option: 4 to 3 Valley HL)

REF

nd

rd

th

2

to 3 Valley Transition at LL and 3 to 4 Valley HL,

th

V

Decr. (Prog. Option: 4 to 5 Valley HL)

REF

rd

nd

th

rd

3

to 2 Valley Transition at LL and 4 to 3 Valley HL,

th

V

Incr. (Prog. Option: 5 to 4 Valley HL)

REF

rd

th

3

to 4 Valley Transition at LL and 4 to 5 Valley HL,

th

V

Decr. (Prog. Option: 5 to 6 Valley HL)

REF

th

4

to 3 Valley Transition at LL and 5 to 4 vAlley HL,

th

V

Incr. (Prog. Option: 6 to 5 Valley HL)

REF

th

4

to 5 Valley Transition at LL and 5 to 6 Valley HL,

th

V

Decr. (Prog. Option: 6 to 7 Valley HL)

REF

th

5

to 4 Valley Transition at LL and 6 to 5 Valley HL,

th

V

REF

V

REF

V

REF

Incr. (Prog. Option: 7 to 6 Valley HL)

Value at which the FF Mode is Activated

Value at which the FF Mode is Removed

V

decreases

increases

V

−

0.25

0.35

−

V

REF

FFstart

REF

FFstop

FREQUENCY FOLDBACK

Added Dead Time (Note 5)

V

REFX

V

REFX

V

REFX

V

REFX

V

REFX

V

REFX

= 0.25 V

= 0.08 V

< 3 mV

< 11.2 mV

= 0

t

−

2

−

ms

FF1LL

Added Dead Time (Note 5)

t

35

FFchg

Dead−time Clamp (Option 1) (Note 5)

Dead−time Clamp (Option 2) (Note 5)

Minimum Added Dead−time in Standby (Note 5)

t

687

250

640

1.8

FFend1

FFend2

t

DT(min)SBY

Maximum Added Dead−time in Standby (Option 2)

(Note 5)

= 0, V

< 0.7 V

t

DT(max)SBY2

COMP

V

Threshold below which Valley Synchronization in

V

REFX

V

REFX

decreasing

increasing

V

REFXsyncD

0.14

0.15

0.16

V

REFX

Frequency Foldback is Turned Off (Note 5)

V

Threshold above which Valley Synchronization in

V

0.165 0.18 0.195

REFX

REFXsyncI

Frequency Foldback is Turned On (Note 5)

DIMMING SECTION

DIM Pin Voltage for Zero Output Current (OFF Voltage)

ADIM Pin Voltage for 1% Reference Voltage

Minimum Dimming Level (Option 1)

V

0.475

0.5

0.7

0

0.525

V

ADIM(EN)

V

0.668

0.732

ADIM(MIN)

K

−

%

V

DIM(MIN)1

DIM(MIN)2

DIM(MIN)3

DIM(MIN)4

Minimum Dimming Level (Option 2)

K

1

Minimum Dimming Level (Option 3)

K

5

−

Minimum Dimming Level (Option 4)

8

−

ADIM Pin Voltage for Maximum Output Current

V

3.0

3.1

ADIM100

(V

REFX

= 1 V)

Dimming Range

V

−

2.3

6.8

10

70

153

1080

3

−

V

ADIM(range)

Clamping Voltage for DIM Pin

V

ADIM(CLP)

Dimming Pin Pull−up Current Source

Current Comparator Low Threshold for PDIM

Current Comparator High Threshold for PDIM

Cascode Current Limit for PDIM

I

8

12

80

175

−

mA

V

ADIM(pullup)1

I

60

131

−

PDIM(THR)

PDIM(THD)

I

PDIM(LIM)

PDIM Pin Voltage

V

PDIM

−

Maximum Period of the PWM Dimming Signal

Minimum On−time for PWM Signal Applied on PDIM

−

6

−

ms

−

8

−

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7

NCL30486B

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T = 25°C, V = 12 V, V

= 0 V, V = 0 V.

CS

J

CC

ZCD

For min/max values T = −40°C to +125°C, Max T = 150°C, V = 12 V) (continued)

J

CC

Parameter

Test Condition

Symbol

Min

Typ

Max

Unit

FAULT PROTECTION

Thermal Shutdown (Note 5)

Device switching (F

65 kHz)

around

T

SHDN

130

150

170

°C

SW

Thermal Shutdown Hysteresis

T

−

20

–

°C

SHDN(HYS)

Threshold Voltage for Output Short Circuit or Aux.

Winding Short Circuit Detection

V

0.6

0.65

0.7

V

ZCD(short)

Short Circuit Detection Timer

V

ZCD

< V

t

OVLD

70

3

90

4

110

5

ms

s

ZCD(short)

Auto−recovery Timer

t

recovery

Line OVP Threshold

V

increasing

decreasing

V

457

430

210

469

443

340

485

465

470

Vdc

ms

HV

HV(OVP)

HV Pin Voltage at which Line OVP is Reset

Blanking Time for Line OVP Reset

BROWN−OUT AND LINE SENSING

Brown−Out ON Level (IC Start Pulsing)

Brown−Out ON Level (IC Start Pulsing) Option 2

Brown−Out OFF Level (IC Stops Pulsing)

Brown−Out OFF Level (IC Stops Pulsing) Option 2

V

HV(OVP)RST

HV

T

LOVP(blank)

V

HV

V

HV

V

HV

V

HV

V

HV

increasing

decreasing

V

101.5

129.7

92

108

138

99

114.5

146.3

106

137

−

Vdc

V

HVBO(on)

V

HVBO(on)2

V

HVBO(off)

V

121

−

129

55

HVBO(off)2

HV Pin Voltage above which the Sampling of ZCD is

Enabled Low Line

decreasing, low line

decreasing, highline

increasing

V

sampENLL

HV Pin Voltage above which the Sampling of ZCD is

Enabled Highline

V

−

105

−

V

HV

sampENHL

ZCD Sampling Enable Comparator Hysteresis

BO Comparators Delay

V

−

5

−

V

HV

sampHYS

BO(delay)

BO(blank)

t

30

25

ms

Brown−Out Blanking Time

15

35

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Guaranteed by design.

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8

NCL30486B

TYPICAL CHARACTERISTICS

4,9

4,8

4,7

4,6

4,5

4,4

4,3

4,2

4,1

4

296

291

286

281

276

271

266

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 3. I_HV(start2)vs. Temperature

Figure 4. I_HV(start1)vs. Temperature

18,31

18,3

10,218

10,213

10,208

10,203

10,198

10,193

10,188

10,183

10,178

10,173

10,168

18,29

18,28

18,27

18,26

18,25

18,24

18,23

18,22

−50

−25

0

25

50

75

−50

−25

0

25

50

75

TEMPERATURE (°C)

Figure 5. V_CC(on)vs. Temperature

Figure 6. V_CC(off)vs. Temperature

1,47

1,45

1,43

1,41

1,39

1,37

1,35

1,33

26,91

26,89

26,87

26,85

26,83

26,81

26,79

−50

−25

0

25

50

75

−50

−25

0

25

50

75

TEMPERATURE (°C)

Figure 7. V_CC(OVP)vs. Temperature

Figure 8. I_CC1vs. Temperature

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9

NCL30486B

TYPICAL CHARACTERISTICS (continued)

1,0505

1,0495

1,0485

1,0475

1,0465

1,0455

1,0445

1,0435

1,0425

1,0415

1,765

1,755

1,745

1,735

1,725

1,715

1,705

1,695

1,685

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 9. I_CC4vs. Temperature

Figure 10. t_FF1LLvs. Temperature

358

357

356

355

354

353

352

351

350

2,214

2,209

2,204

2,199

2,194

2,189

2,184

2,179

2,174

2,169

2,164

−50

−25

0

25

50

75

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 11. V_HV(OL)vs. Temperature

Figure 12. V_REF(PFC)CLPvs. Temperature

1,3755

1,3735

1,3715

1,3695

1,3675

1,3655

1,3635

54,2

53,7

53,2

52,7

52,2

51,7

51,2

50,7

50,2

−50

−25

0

25

50

75

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 13. V_ILIMvs. Temperature

Figure 14. V_CS(low)Fvs. Temperature

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10

NCL30486B

TYPICAL CHARACTERISTICS (continued)

2,005

2,004

2,003

2,002

2,001

2

379

378,5

378

377,5

377

1,999

1,998

1,997

1,996

1,995

376,5

376

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 15. V_CS(stop)vs. Temperature

Figure 16. V_{CS(SBY)_opn1}vs. Temperature

280,2

330,6

329,6

328,6

327,6

326,6

325,6

279,7

279,2

278,7

278,2

277,7

277,2

276,7

276,2

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 17. V_{CS(SBY)_opn2}vs. Temperature

Figure 18. V_{CS(SBY)_opn3}vs. Temperature

14,1

20,1

14,05

14

20,05

20

13,95

13,9

13,85

13,8

19,95

19,9

19,85

19,8

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 19. t_on(MAX)1vs. Temperature

Figure 20. t_on(MAX)2vs. Temperature

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11

NCL30486B

TYPICAL CHARACTERISTICS (continued)

183

182

181

180

179

178

177

176

310

308

306

304

302

300

298

296

294

292

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 21. t_LEBvs. Temperature

Figure 22. t_BCSvs. Temperature

49

47

45

43

41

39

37

11

10

9

8

7

6

5

4

3

−50

−25

0

25

50

75

−25

0

25

50

75

TEMPERATURE (°C)

Figure 23. t_ILIMvs. Temperature

Figure 24. R_SNKvs. Temperature

37

35

33

31

29

27

25

23

21

19

22

17

12

7

2

−50

−25

0

25

50

75

−50

−25

0

25

50

75

TEMPERATURE (°C)

Figure 25. R_SRCvs. Temperature

Figure 26. t_rvs. Temperature

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12

NCL30486B

TYPICAL CHARACTERISTICS (continued)

86,2

86,1

86

22

20

18

16

14

12

85,9

85,8

85,7

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 27. t_fvs. Temperature

Figure 28. V_ZCD(rising)vs. Temperature

0,6685

0,6675

0,6665

0,6655

0,6645

0,6635

0,6625

0,6615

0,6605

57,4

56,9

56,4

55,9

55,4

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 29. V_ZCD(falling)vs. Temperature

Figure 30. V_ZCD(short)vs. Temperature

121

116

111

106

101

96

1,63

1,62

1,61

1,6

1,59

1,58

1,57

1,56

91

86

81

76

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 31. t_ZCD(DEM)vs. Temperature

Figure 32. t_{ZCD(blank1)OPN1}vs. Temperature

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13

NCL30486B

TYPICAL CHARACTERISTICS (continued)

0,876

0,871

0,866

0,861

0,856

0,851

0,846

0,841

0,836

1,084

1,079

1,074

1,069

1,064

1,059

1,054

1,049

1,044

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 33. t_{ZCD(blank1)OPN2}vs. Temperature

Figure 34. t_{ZCD(blank1)OPN1}vs. Temperature

6,895

0,584

6,875

6,855

6,835

6,815

6,795

0,579

0,574

0,569

0,564

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 35. t_{ZCD(blank2)OPN2}vs. Temperature

Figure 36. t_TIMOvs. Temperature

341

35

34,5

34

340,5

340

339,5

339

338,5

338

33,5

33

337,5

337

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 37. V_REF/3vs. Temperature

Figure 38. V_REF10/3vs. Temperature

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14

NCL30486B

TYPICAL CHARACTERISTICS (continued)

18,4

18,2

18

3,528

3,523

3,518

3,513

3,508

3,503

3,498

3,493

3,488

17,8

17,6

17,4

17,2

17

16,8

16,6

16,4

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 39. V_REF5/3vs. Temperature

Figure 40. V_REF(CV)vs. Temperature

4,121

4,116

4,111

4,106

4,101

4,096

615,5

613,5

611,5

609,5

607,5

605,5

603,5

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 41. V_CV(clampL)vs. Temperature

Figure 42. V_CV(clampH)vs. Temperature

4,529

4,524

4,519

4,514

4,509

4,058

4,048

4,038

4,028

4,018

4,008

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 43. V_OVP1vs. Temperature

Figure 44. V_OVP2vs. Temperature

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NCL30486B

TYPICAL CHARACTERISTICS (continued)

102,7

102,2

101,7

101,2

100,7

100,2

99,7

0,2074

0,2064

0,2054

0,2044

0,2034

0,2024

99,2

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 45. K_LFFvs. Temperature

Figure 46. I_offset(MAX)vs. Temperature

41,6

41,4

41,2

41

470,2

469,7

469,2

468,7

468,2

467,7

467,2

466,7

466,2

465,7

465,2

40,8

40,6

40,4

40,2

40

−50

−25

0

25

50

75

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 47. I_FFvs. Temperature

Figure 48. V_HV(OVP)vs. Temperature

443,9

443,4

442,9

442,4

441,9

441,4

440,9

440,4

439,9

439,4

108,15

108,05

107,95

107,85

107,75

107,65

107,55

107,45

107,35

107,25

−50

−25

0

25

50

75

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 49. V_HV(OVP)RSTvs. Temperature

Figure 50. V_HVBO(on)1vs. Temperature

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16

NCL30486B

TYPICAL CHARACTERISTICS (continued)

99,15

99,05

98,95

98,85

98,75

98,65

98,55

98,45

98,35

98,25

138,45

138,25

138,05

137,85

137,65

137,45

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 51. V_HVBO(off)1vs. Temperature

Figure 52. V_HVBO(on)2vs. Temperature

127,4

127,2

127

0,5042

0,5037

0,5032

0,5027

0,5022

0,5017

0,5012

126,8

126,6

126,4

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 53. V_HVBO(off)2vs. Temperature

Figure 54. V_ADIM(EN)vs. Temperature

151,7

151,2

150,7

150,2

149,7

149,2

148,7

148,2

70,5

70

69,5

69

68,5

68

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 55. I_PDIM(THR)vs. Temperature

Figure 56. I_PDIM(THD)vs. Temperature

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17

NCL30486B

TYPICAL CHARACTERISTICS (continued)

1,077

1,072

1,067

1,062

1,057

1,052

3,003

3,001

2,999

2,997

2,995

2,993

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 57. I_PDIM(LIM)vs. Temperature

Figure 58. V_PDIMvs. Temperature

0,704

0,703

0,702

0,701

0,7

3,006

3,004

3,002

3

0,699

0,698

0,697

0,696

2,998

2,996

2,994

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 59. V_ADIM(MIN)vs. Temperature

Figure 60. V_ADIM100vs. Temperature

168,5

166,5

164,5

162,5

160,5

158,5

156,5

−50

−25

0

25

50

75

100

TEMPERATURE (°C)

Figure 61. I_ZCD(DIM)vs. Temperature

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18

NCL30486B

Application Information

The NCL30486B implements

if V reaches 1.5 x V

(after a reduced LEB of t ).

BCS

CS

ILIM

a

current−mode

This additional comparator is enabled only during the

main LEB duration t , for noise immunity reason.

architecture operating in quasi−resonant mode. Thanks to

proprietary circuitry, the controller is able to accurately

regulate the secondary side current and voltage of the

fly−back converter without using any opto−coupler or

measuring directly the secondary side current or voltage.

The controller provides near unity power factor correction

LEB

• Output Under Voltage Protection: If a too low voltage is

applied on ZCD pin for 90 ms time interval, the

controllers assume that the output or the ZCD pin is

shorted to ground and shutdown. After waiting 4 seconds,

the IC restarts switching.

• Analog Dimming: the ADIM pin is dedicated to analog

dimming. There are several options for the minimum

dimming level. Pulling the pin voltage lower than

• Quasi−Resonance

Current−Mode

Operation:

implementing quasi−resonance operation in peak

current−mode control, the NCL30486B optimizes the

efficiency by switching in the valley of the MOSFET

drain−source voltage. Thanks to an internal algorithm

control, the controller locks−out in a selected valley and

remains locked until the input voltage or the output

current set point significantly changes.

V

disables the controller.

ADIM(EN)

• PWM Dimming: the PDIM pin is dedicated to PWM

dimming. The controller measures the duty ratio of a

signal applied to the pin and reduces the output current

accordingly. If this pin is left open, the controller delivers

the maximum output current. If the pin is pulled down, the

controller is disabled.

• Thermal Shutdown: an internal circuitry disables the gate

drive when the junction temperature exceeds 150°C

(typically). The circuit resumes operation once the

temperature drops below approximately 100°C.

• Standby Mode: In order to decrease the power

consumption of the SMPS if no load conditions, the

controller features a standby mode, where its own

consumption is decreased.

• Dimming Standby Mode (dimCV Mode) Option: by

pulling ADIM or PDIM down, the controller goes in

constant voltage mode with a reduced regulation setpoint.

• Primary Side Constant Current Control: thanks to a

proprietary circuit, the controller is able to take into

account the effect of the leakage inductance of the

transformer and allows an accurate control of the

secondary side current regardless of the input voltage and

output load variation.

• Primary Side Constant Voltage Regulation: By

monitoring the auxiliary winding voltage, it is possible to

regulate accurately the output voltage. The output voltage

regulation is typically within 2%.

• Load Transient Compensation: Since PFC has low loop

bandwidth, abrupt changes in the load may cause

excessive over or under−shoot. The slow Over Voltage

Protection contains the output voltage when it tends to

become excessive. In addition, the NCL30486B speeds

up the constant voltage regulation loop when the output

voltage goes below 80% or 85% of its regulation level.

• Power Factor Correction: A proprietary concept allows

achieving high power factor correction and low THD

while keeping accurate constant current and constant

voltage control.

POWER FACTOR AND CONSTANT CURRENT

CONTROL

The NCL30486B embeds an analog/digital block to

control the power factor and regulate the output current by

monitoring the ZCD, CS and HV pin voltages (signals

V

, V

, V ). This circuit generates the current

HV_DIV CS

ZCD

setpoint signal and compares it to the current sense signal to

turn the MOSFET off. The HV pin provides the sinusoidal

reference necessary for shaping the input current. The

obtained current reference is further modulated so that when

averaged over a half line period, it is equal to the output

• Line Feed−forward: allows compensating the variation of

the output current caused by the propagation delay.

• V Over Voltage Protection: if the V pin voltage

CC

exceeds an internal limit, the controller shuts down and

waits 4 seconds before restarting pulsing.

current reference (V

). The modulation and averaging

REFX

process is made internally by a digital circuit. If the HV pin

properly conveys the sinusoidal shape, power factor will be

close to 1. Also, the Total Harmonic Distortion (THD) will

be low especially if the output voltage ripple is small.

• Fast Over Voltage Protection: If the voltage of ZCD pin

exceeds 130% of its regulation level, the controller shuts

down and waits 4 s before trying to restart.

• Brown−Out: the controller includes a brown−out circuit

which safely stops the controller in case the input voltage

is too low. The device will automatically restart if the line

recovers.

V_REF

(eq. 1)

I_OUT

+

2N_spR_sense

Where:

• Cycle−by−cycle Peak Current Limit: when the current

• N is the secondary to primary transformer turns ratio:

sp

sense voltage exceeds the internal threshold V

, the

ILIM

N

• R

• V

= N / N

S P

sp

MOSFET is turned off for the rest of the switching cycle.

• Winding Short−Circuit Protection: an additional

comparator senses the CS signal and stops the controller

is the current sense resistor

sense

is the output current reference: V

= V

if

REFX

REF

no dimming

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19

NCL30486B

The output current reference (V

) is V

unless the

The sampled voltage is applied to the negative input of the

constant voltage (CV) operational transconductance

REFX

REF

constant voltage mode is activated or ADIM pin voltage is

below V or a PWM signal with a duty−cycle below

amplifier (OTA) and compared to V

.

ADIM(100)

REFCV

95% is applied on PDIM.

A type 2 compensator is needed at the CV OTA output to

stabilize the loop. The COMP pin voltage modify the the

output current internal reference in order to regulate the

output voltage.

PRIMARY SIDE CONSTANT VOLTAGE CONTROL

The auxiliary winding voltage is sampled internally

through the ZCD pin.

A precise internal voltage reference V

voltage target for the CV loop.

When V

≥ 4 V, V

= V

.

COMP

REFX

< 0.9 V, V

REF

sets the

REF(CV)

= 0 V.

REFX

G_m

R_ZCDU

ZCD

V

ZCDsamp

ZCD & signal

sampling

COMP

.

R₁

C₁

R

OTA

ZCDL

V_REF(CV)

C₂

Aux.

Figure 62. Constant Voltage Feedback Circuit

STARTUP PHASE (HV STARTUP)

• At the beginning of each operating phase of a V cycle,

CC

It is generally requested that the LED driver starts to emit

light in less than 1 s and possibly within 300 ms. It is

challenging since the start−up consists of the time to charge

the digital OTA output is set to 0. Actually, the digital

OTA output is set to 0 in the case of a cold start−up or in

the case of a start−up sequence following an operation

the V capacitor and that necessary to charge the output

CC

interruption due to a fault. On the other hand, if the V

CC

capacitor until sufficient current flows into the LED string.

This second phase can be particularly long in dimming cases

where the secondary current is a portion of the nominal one.

The NCL30486B features a high voltage startup circuit

that allows charging VCC capacitor very fast.

hiccups just because the system fails to start−up in one

cycle, the digital OTA output is not reset to ease the

V

CC

second (or more) attempt. But, the digital OTA stops

integrating if V < V . The compensator output

CC

CC(off)

then restarts from its setpoint before the UVLO, thus

avoiding any output current overshoot if a resistor is

inserted in series with HV pin.

When the power supply is first connected to the mains

outlet, the internal current source is biased and charges up

the V capacitor. When the voltage on this V capacitor

CC

• If the load is shorted, the circuit will operate in hiccup

reaches the V

level, the current source turns off. At this

CC(on)

mode with VCC oscillating between V

and V

CC(on)

CC(off)

time, the controller is only supplied by the V capacitor,

CC

until the output under voltage protection (UVP) trips.

UVP is triggered if the ZCD pin voltage does not exceed

and the auxiliary supply should take over before V

CC

collapses below V

.

CC(off)

V

within a 90 ms operation of time. This

ZCD(short)

The HV startup circuitry is made of two startup current

levels, I and I . This helps to protect the

indicates that the ZCD pin is shorted to ground or that an

excessive load prevents the output voltage from rising.

HV(start1)

HV(start2)

controller against short−circuit between V and GND. At

CC

power−up, as long as V is below V

, the source

CC

CC(TH)

HV Startup Power Dissipation

delivers I

(around 300 mA typical). Then, when

HV(start1)

At high line (305 V rms and above) the power dissipated

by the HV startup in case of fault or when the controller is

disabled with PDIM becomes high. Indeed, in case of fault,

the NCL30486B is directly supplied by the HV rail. When

the controller is disabled with PDIM, the optocoupler

collector current is also supplied by the controller, since the

NCL30486B allows directly connecting the optocoupler

transistor to PDIM pin. Thus, the HV startup circuit also

supplies the optocoupler transistor in case of faults. The

current flowing through the HV startup will heat the

controller. It is highly recommended adding enough copper

V

reaches V

, the source smoothly transitions to

CC

CC(TH)

I

and delivers its nominal value. As a result, in case

HV(start2)

of short−circuit between V and GND occurring at high

line (V = 305 V rms), the maximum power dissipation will

be 431 x 300 m = 130 mW instead of 1.5 W if there was only

one startup current level.

To speed−up the output voltage rise, the following is

implemented:

CC

in

• The digital OTA output is increased until V

REF(PFC)

signal reaches V

. Again, this is to speed−up the

REFX

control signal rise to their steady state value.

around the controller to decrease the R

of the controller.

qJA

www.onsemi.com

20

NCL30486B

2

Winding and Output Diode Short−Circuit Protection

In parallel to the cycle−by−cycle sensing of the CS pin,

Adding a minimum pad area of 215 mm of 35 mm copper

(1 oz) drops the R to around 120°C/W (no air flow, R

qJA

another comparator with a reduced LEB (t ) and a

measured at ADIM pin)

The PCB layout shown in Figure 63 is a layout example

to achieve low R

BCS

threshold of (V

= 140% x V

) monitors the CS pin

CS(stop)

ILIM

to detect a winding or an output diode short circuit. The

controller shuts down if it detects 4 consecutives pulses

.

qJA

during which the CS pin voltage exceeds V

CS(stop).

The controller goes into auto−recovery mode.

PWM Dimming

The NCL30486B has a dedicated pin for PWM dimming.

The controller directly measures the duty ratio of a PWM

signal applied to PDIM.

Two counters with a high frequency clock are used for this

purpose. A first counter measure the high state duration of

the PWM signal (t ) and the second counter measures

on_PDIM

its period (T

). A divider computes (t

/

sw_PDIM

on_PDIM

T

) and the result is directly the output current

sw_PDIM

setpoint (V

set point). A filter is added after the digital

REFX

divider to remove the ripple of the signal. A cascode

configuration on PDIM pin allows decreasing the fall time

of the signal.

Thanks to this circuit, the LED current is controlled in an

analog way, even if a PWM signal is used for dimming. This

allows having a good PF during dimming.

Figure 63. PCD Layout Example

The application note AND90120 gives more details about

strategies to decrease the power dissipation of the HV

startup circuit.

Cycle−by−Cycle Current Limit

When the current sense voltage exceeds the internal

threshold V , the MOSFET is turned off for the rest of the

ILIM

switching cycle.

V_{DIM_sec}

I_PDIM

I_PDIM(THD)

I_PDIM(THR)

V_{PDIM_int}

T_on

T_sw

Figure 64. PDIM Internal Waveforms

www.onsemi.com

21

NCL30486B

Practically, the controller extracts the duty−cycle by

If a voltage lower than V

is applied to the DIM

ADIM(EN)

measuring the current inside PDIM pin which is directly the

opto coupler collector current.

pin, the DRV pulses are disabled for controllers without the

dimming CV mode option.

If PDIM pin is left open, the controller delivers 100% of

The DIM pin is pulled up internally by a small current

source or resistor. Thus, if the pin is left open, the controller

is able to start.

I

. If the pin is pulled down for longer than 25 ms, the

out

controller is disabled.

If the PWM dimming signal is removed during dimming,

NOTE:

the controller delivers 100% of I

.

out

• Interaction between ADIM and PDIM: if ADIM and

The NCL30486B set 100% of output current when the

duty−cycle of the signal applied on PDIM is above 93%.

PDIM are both used at the same time, the resulting

dimming set point if a multiplication of V

and the

ADIM

duty−ratio of PDIM signal.

Analog Dimming

• During dimming, when the “Enable” signal is OK, the

The pin ADIM pin allows implementing analog dimming

of the LED light.

controller starts pulsing after first valley, even if a higher

valley number is selected by V

. This is to avoid too

If the power supply designer applies an analog signal

REFX

varying from V

output current will increase or decrease proportionally to the

voltage applied. For V = V , the power supply

to V

to the DIM pin, the

long startup time while dimming at low output current

value. After ZCD voltage during DRV off time is higher

DIM(EN)

DIM100

than 0.65 V, the number of valley is selected by V

.

DIM

DIM100

REFX

delivers the maximum output current (V

= 1 V).

REFX

• In order to minimize discrete output current variation

caused by valley change in deep dimming, valley

synchronization is removed when the dimming setpoint is

below 15%.

If a voltage lower than V

is applied to ADIM

ADIM(MIN)

pin, the output current is clamped to the selected dimming

clamp value (see Dimming clamp section below)

V_REF

100% V_REF

8% V

REF

5% V

REF

1% V_REF

V_ADIM(EN)

V_ADIM100

V_ADIM

V_ADIM(MIN)

Figure 65. ADIM Pin Dimming Curves

www.onsemi.com

22

NCL30486B

Dimming Clamp

For smart dimming applications, need to bias the

secondary−side MCU. This can be achieved by clamping

There are 4 options for the dimming clamp:

• No dimming clamp

• 1%

• 5%

• 8%

V

REFX

when the dimming setpoint is small.

V

REFX

(%)

100%

8%

5%

1%

0.01 0.05

1.0

0.08

Scaled dimming voltage or

dimming duty−ratio

Figure 66. Dimming Clamp Options

Dimming Curves

By default, there is a linear relationship between the

voltage applied on ADIM pin and V setpoint. In the

same way, there is a linear relationship between the

duty−ratio of the signal applied on PDIM and V

An internal memory allows selecting a root square

relationship between dimming and V

The square like curve is based on CIE 1931 lightness

formula.

.

REFX

setpoint.

Output Current vs. Dimming

100

90

80

70

60

50

40

30

20

10

0

linear

CIE 1931

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Scaled Dimming Voltage or Dimming Duty Ratio

Figure 67. Dimming Curves

www.onsemi.com

23

NCL30486B

Dimming Standby Mode (dimCV Mode)

• R

is the resistor connected between ZCD and GND

is the auxiliary winding voltage corresponding to

ZCDL

pins

The NCL30486B features an option to force constant

voltage regulation by pulling ADIM or PDIM pin down.

This can be useful to provide some energy to secondary side

circuitry while the LED are turned off. In this mode, the

regulation target is set lower than the regulation threshold is

normal CV mode.

• V

auxCV1

the nominal CV setpoint

• V

is the auxiliary winding voltage corresponding to

auxCV2

the CV setpoint in reduced CV mode: V

< V

auxCV2

auxCV1

Concretely, when V

internal PDIM signal on−time is below 10 ms during 20 ms,

the “dimCVmode” signal becomes high and the I

current source is applied to ZCD pin during the

demagnetization time only (this is to allow correct valley

detection). This current sources increases ZCD voltage and

consequently a new regulation point is set for the CV loop.

The ZCD pin resistors set directly the regulation threshold

in normal CV mode and in dimming CV mode.

< V

or when the

ADIM

ADIM(EN)

Valley Lockout

Quasi−Square wave resonant systems have a wide

switching frequency excursion. The switching frequency

increases when the output load decreases or when the input

voltage increases. The switching frequency of such systems

must be limited.

ZCD(dim)

The NCL30486B changes valley as V

decreases and

REFX

as the input voltage increases and as the output current

setpoint is varied during dimming. This limits the frequency

excursion.

By default, when the output current is not dimmed, the

controller operates in the first valley at low line and in the

second valley at high line.

There is an option to have the valley thresholds

incremented by 1 at high line for better I control at

305 V rms.

V

_REF(CV)(V_auxCV1* V_auxCV2)

(eq. 2)

R_ZCDL

+

I

_ZCD(dim)(V_auxCV1* V_REF(CV))

V_auxCV1

ǒ Ǔ

(eq. 3)

R_ZCDU+ R_ZCDL

* 1

V_REF(CV)

out

Where:

• R

is the resistor from auxiliary winding to ZCD pin

ZCDU

Table 1. VALLEY SELECTION

V

Voltage for Valley Change

HV_DIV

V

REFX

Value at which the Controller

V

REFX

Value at which the Controller

0

−−LL−−

2.3 V

−−HL−−

5 V

Changes Valley (I

Decreasing)

Changes Valley (I

Increasing)

out

st

nd rd

100%

1

2

3

4

5

6

(3 )

90%

75%

60%

45%

80%

65%

50%

35%

nd

rd th

2

(4 )

rd

th th

3

(5 )

th

th th

4

(6 )

th

th th

5

(7 )

25%

0%

35%

0%

FF mode

0

−−LL−−

2.3 V

−−HL−−

5 V

Internal V

Voltage for Valley Change

HV_DIV

Zero Crossing Detection Block

the valleys. To avoid such a situation, NCL30486B features

a Time−Out circuit that generates pulses if the voltage on

ZCD pin stays below the 55 mV threshold for 6.5 ms.

The Time−out also acts as a substitute clock for the valley

detection and simulates a missing valley in case of too

damped free oscillations.

The ZCD pin allows detecting when the drain−source

voltage of the power MOSFET reaches a valley.

A valley is detected when the ZCD pin voltage crosses

below the 55 mV internal threshold.

At startup or in case of extremely damped free

oscillations, the ZCD comparator may not be able to detect

www.onsemi.com

24

NCL30486B

V_ZCD

V_ZCD(th)

low

3

4

high

14

12

I

decreases or V

out

in

high

increases

ZCD comp

high

low

15

low

TimeOut

16

17

2^nd, 3 ^rd

high

V_VIN

increases

Clock

low

Figure 68. Valley Detection and Time−out Chronograms

If the ZCD pin or the auxiliary winding happen to be

shorted the time−out function would normally make the

controller keep switching and hence lead to improper

regulation of the LED current.

The Under Voltage Protection (UVP) is implemented to

avoid these scenarios: a secondary timer starts counting

10 Hz, depending on power stage phase shift). Because the

loop is slow, the output voltage can reach high value during

startup or during an output load step. It is necessary to limit

the output voltage excursion. For this, the NCL30486B

features a slow OVP and a fast OVP on ZCD pin.

Slow OVP

when the ZCD voltage is below the V

threshold. If

ZCD(short)

If ZCD voltage exceeds V

for 4 consecutive

OVP1

this timer reaches 90 ms, the controller detects a fault and

enters the auto−recovery fault mode.

switching cycles, the controller stops switching during

1.4 ms. The PFC loop is not reset. After 1.4 ms, the

controller initiates a new DRV pulse to refresh ZCD

Minimum Off−time at Startup

At startup, the output voltage reflected on the auxiliary

winding is low. Thus, the voltage on the ZCD pin is very low

and the ZCD comparator might be unable to detect the

valleys. In this condition, setting the DRV latch with the

6.5−ms time−out leads to a continuous conduction mode

operation (CCM).

sampling voltage. If V

is still too high (V

> 115%

ZCD

V

), the controller continues to switch with a 1.4 ms

REF(CV)

period. The controller resumes its normal operation when

< 105% V

V

ZCD

.

REF(CV)

During slow OVP, the peak current setpoint is COMP pin

voltage scaled down by a fixed ratio.

To avoid CCM pulses during startup, a minimum off time

Fast OVP

If ZCD voltage exceeds V

for 4 consecutive switching cycles (slow OVP not triggered)

or for 2 switching cycles if the slow OVP has already been

triggered, the controller detects a fault and starts the

auto−recovery fault mode (cf: Fault Management Section)

(typ. 50 ms) is forced when V

< V

during 8 ms.

ZCD

ZCD(short)

(130% of V

)

ZCD(OVP2)

REF(CV)

This minimum off time is also present when the controller

restart after a fault, if V < V

.

ZCD(short)

ZCD

ZCD Over Voltage Protection

Because of the power factor correction, it is necessary to

set the crossover frequency of the CV loop very low (target

www.onsemi.com

25

NCL30486B

HV

v_DD

v_VS

CS

R_LFF

I _CS(offset)

K_LFF

R_sense

Q_drv

+

25 ms

BO_NOK

Blanking

−

1 V / 0.9 V

Figure 69. Line Feed−Forward and Brown−out Schematic

Line Feedforward

if a voltage higher than V

is applied to the HV pin

HVBO(on)

The line voltage is sensed by the HV pin and converted

into a current. By adding an external resistor in series

between the sense resistor and the CS pin, a voltage offset

proportional to the line voltage is added to the CS signal. The

offset is applied only during the MOSFET on−time in order

to not influence the detection of the leakage inductance

reset.

and shuts−down if the HV pin voltage decreases and stays

below V for 25 ms typical.

An option with higher brown−out levels is also available

HVBO(off)

(see ordering table and electricals parameters)

Line OVP

In order to protect the power supply in case of too high

input voltage, the NCL30486B features a line over voltage

The offset is always applied even at light load in order to

improve the current regulation at low output load.

protection. When the voltage on HV pin exceeds V

HV(OVP)

the controller stops switching; V hiccups.

CC

Brown−out

When V becomes lower than V

for more

HV

HV(OVP)RST

In order to protect the supply against a very low input

voltage, the controller features a brown−out circuit with a

fixed ON/OFF threshold. The controller is allowed to start

than 340 ms, the controller initiates a clean startup sequence

and re−starts switching.

www.onsemi.com

26

NCL30486B

V_HV

V_HV(OVP)

V_HV(OVP)RST

t _LOVP(blank)

V_CC

V_CC(on)

V_CC(off)

V_DRV

I_out

Figure 70. Line OVP Chronograms

Standby Mode

to keep the output voltage regulated (pink curve in

Figure 71).

In order to decrease the power consumption of the

converter when no output load is connected to its output, the

NCL30486B versions features a standby mode.

In standby mode, the current consumption of the

controller is reduced to I

The peak current is frozen to a fixed value V

The regulation of V is based on COMP pin voltage

out

varying between 700 mV to 913 mV.

Standby mode is entered if V

< 895 mV, V

COMP

(1.7 mA typ.)

decreasing and exit if V

> 913 mV, V

increasing.

CC4

COMP

(See AND90120 for more details concerning the standby

mode)

CS(STBY)

(27% or below of V

switching frequency, more specifically the dead−time (DT)

) and the controller adjust the

ILIMIT

DT (ms)

t

, 1800

DT(max)SBY2

Standby mode curve

t

, 687

FFend1

t , 640

DT(min)SBY

560

Simplified FF curve for 675 ms DT clamp

t

, 35

FFchg

t

, 2

FF1LL

700

895

913

1.758

250

V_COMP(V)

V

CMP(SBY)

0 5.848

V_REFX(mV)

V

FFstart

Figure 71. Dead−time Setpoint as a Function of V_COMP

www.onsemi.com

27

NCL30486B

Variable Maximum On−time

Around line zero−crossing, the primary inductor slope is

too low to reach the peak current setpoint imposed by the CC

control. The DRV pulse is terminated by the max. on−time.

This creates sudden variation of the on−time and creates

an input current spike (EMI filter inductance responds to

rate of change of current).

Varying the maximum on−time with V^REFXhelps

decreasing this spike over the output load range. Figure 72

and Figure 73 shows the maximum on−time curve as a

function of V^REFX.

T

(ms)

on,MAX

20

18

16

14

12

10

7

0.15

0.18 0.25

0.5

0.6

0.8

0.9

1

V

REFX

(V)

0.35

0.45

0.65

0.75

Figure 72. Variable Maximum On−time, 20−ms Option

T

(ms)

on,MAX

20

18

16

14

12

11

10

9

8

7

0.15

0.18 0.25 0.35

0.5

0.6

0.65

0.8

0.9

1

V

REFX

(V)

0.45

0.75

Figure 73. Variable Maximum On−time, 14−ms Option

www.onsemi.com

28

NCL30486B

Protections

• V Over Voltage Protection

CC

The circuit incorporates a large variety of protections to

make the LED driver very rugged.

Among them, we can list:

The circuit stops generating pulses if the V exceeds

CC

V

and enters auto−recovery mode. This feature

CC(OVP)

protects the circuit if output LEDs happen to be

disconnected.

• Fault of the GND connection

If the GND pin is properly connected, the supply current

• ZCD fast OVP

drawn from the positive terminal of the V capacitor,

flows out of the GND pin to return to the negative terminal

CC

If ZCD voltage exceeds V

for 4 consecutive

ZCD(OVP2)

switching cycles (slow OVP not triggered) or for 2

switching cycles if the slow OVP has already been

triggered, the controller detects a fault and enters

auto−recovery mode (4 s operation interruption between

active bursts).

of the V capacitor. If the GND pin is not connected, the

CC

circuit ESD diodes offer another return path. The

accidental non connection of the GND pin can hence be

detected by detecting that one of this ESD diode is

conducting. Practically, the ESD diode of CS pin is

monitored. If such a fault is detected for 200 ms, the circuit

stops generating DRV pin.

• Die Over Temperature (TSD)

The circuit stops operating if the junction temperature

(T ) exceeds 150°C typically. The controller remains off

J

• Output short circuit situation (Output Under Voltage

until T goes below nearly 130°C.

J

Protection)

• Brown−Out Protection (BO)

Overload is detected by monitoring the ZCD pin voltage:

if it remains below V

circuit is detected and the circuit stops generating pulses

for 4 s. When this 4 s delay has elapsed, the circuit

attempts to restart.

The circuit prevents operation when the line voltage is too

low to avoid an excessive stress of the LED driver.

Operation resumes as soon as the line voltage is high

for 90 ms, an output short

ZCD(short)

enough and V is higher than V

.

CC

CC(on)

• CS pin short to ground

• ZCD pin incorrect connection:

The CS pin is checked at start−up (cold start−up or after

♦ If the ZCD pin grounded, the circuit will detect an

output short circuit situation when 90 ms delay has

elapsed.

a brown−out event). A current source (I

) is applied

cs(short)

to the pin and no DRV pulse is generated until the CS pin

exceeds V . I and V are 500 mA and

cs(low) cs(short)

cs(low)

♦ A 200 kW resistor pulls down the ZCD pin so that

the output short circuit detection trips if the ZCD pin

is not connected (floating).

60 mV typically (V rising). The typical minimum

CS

impedance to be placed on the CS pin for operation is then

120 W. In practice, it is recommended to place more than

250W to take into account possible parametric deviations.

Also, along the circuit operation, the CS pin could happen

to be grounded. If it is grounded, the MOSFET

conduction time is limited by the 20 ms maximum

on−time. If such an event occurs, a new pin impedance

test is made.

• Winding or Output Diode Short Circuit protection

The circuit detects this failure when 4 consecutive DRV

pulses occur within which the CS pin voltage exceeds

(V

= 140% x V

). In this case, the controller

CS(stop)

ILIM

enters auto−recovery mode (4−s operation interruption

between active bursts).

• Line overvoltage protection

(see Line OVP section)

www.onsemi.com

29

NCL30486B

ORDERING TABLE OPTION

Valley

Transition

from LL to HL Standby Mode

Line Range

Detector

Dead−time Clamp

V

Max. On−time

20 ms 14 ms

ZCD Blanking

REF

st

OPN #

NCL30486_ _

1.4 ms 200 mV 333 mV

1

to

1

to

On

Off

On

Off

250 ms 687 ms

1 ms

1.5 ms

nd

rd

2

3

NCL30486B1

NCL30486B2

x

Frozen Peak Current

During Standby Mode

Dimming

Line OVP

V

Brown−out Levels

Dimming Clamp

Curve

dimCV Mode

CS(SBY)

OPN #

NCL30486_ _

On

Off

380 mV 330 mV 280 mV On: 108 V On: 138 V

Off: 98 V Off: 129 V

0%

1%

5%

8%

Linear Square

On

Off

NCL30486B1

NCL30486B2

x

ORDERING INFORMATION

Device

†

Marking

L30486B1

L30486B2

Package Type

Shipping

NCL30486B1

SOIC9 – P7 COMP VHV PBFH

2500 / Tape & Reel

(Pb−Free)

NCL30486B2

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

30

NCL30486B

PACKAGE DIMENSIONS

SOIC−9 NB

CASE 751BP

ISSUE A

2X

NOTES:

0.10

C A-B

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

D

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’

AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15mm

PER SIDE. DIMENSIONS D AND E ARE DE-

TERMINED AT DATUM F.

D

H

A

2X

0.20

C

4 TIPS

0.10 C A-B

F

10

6

E

1

5. DIMENSIONS A AND B ARE TO BE DETERM-

INED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE

FROM THE SEATING PLANE TO THE LOWEST

POINT ON THE PACKAGE BODY.

5

L2

A3

SEATING

PLANE

L

C

0.20

C

9X b

DETAIL A

B

5 TIPS

M

MILLIMETERS

0.25

C A-B D

DIM MIN

MAX

1.75

0.25

0.51

5.00

4.00

TOP VIEW

A

A1

A3

b

D

E

1.25

0.10

0.17

0.31

4.80

3.80

9X

h

X 45

_

0.10

C

0.10

C

M

e

1.00 BSC

H

h

L

5.80

0.37 REF

0.40

6.20

1.27

A

DETAIL A

e

SIDE VIEW

A1

SEATING

PLANE

L2

M

0.25 BSC

C

0

8

_

END VIEW

RECOMMENDED

SOLDERING FOOTPRINT*

1.00

PITCH

9X

0.58

6.50

1

9X

1.18

DIMENSION: MILLIMETERS

*For additional information on our Pb−Free strategy

and soldering details, please download the

onsemi Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

www.onsemi.com

31

NCL30486B

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Email Requests to: orderlit@onsemi.com

TECHNICAL SUPPORT

North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada

Phone: 011 421 33 790 2910

Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910

For additional information, please contact your local Sales Representative

onsemi Website: www.onsemi.com

◊

www.onsemi.com

32


型号：	NCL30486B2DR2G
厂家：	ONSEMI
描述：	Smart-Dimmable CC/CV PSR Controller
文件：	总32页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCL30486B2DR2G [ONSEMI]

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